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  to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics.
user?s manual v850e/dx3 - dj3/dl3 32-bit single-chip microcontroller hardware v850e/dj3: pd70f3421 pd70f3422 pd70f3423 pd70f3424 pd70f3425 pd70f3426a document no. u17566ee5v1um00 date published 9/11/09 ? nec electronics 2009 printed in germany v850e/dl3: pd70f3427
2 v850e/dx3 user?s manual u17566ee5v1um00
3 user?s manual u17566ee5v1um00 notes for cmos devices (1) precaution against esd for semiconductors strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. (2) handling of unused input pins for cmos no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. (3) status before initialization of mos devices power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
4 v850e/dx3 user?s manual u17566ee5v1um00 legal notes ? the information in this document is current as of . the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. ? no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. ? nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such nec electronics products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. ? descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. ? while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire- containment and anti-failure features. ? nec electronics products are classified into the following three quality grades: ?standard?, ?special? and ?specific?. the "specific" quality grade applies only to nec electronics products developed based on a customer-designated ?quality assurance program? for a specific application. the recommended applications of nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc.
5 user?s manual u17566ee5v1um00 the quality grade of nec electronics products is ?standard? unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact nec electronics sales representative in advance to determine nec electronics 's willingness to support a given application. note 1. "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. 2. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above).
6 v850e/dx3 user?s manual u17566ee5v1um00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044 4355111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554,| u.s.a. tel: 408 5886000 http://www.am.necel.com/ [europe] nec electronics (europe) gmbh arcadiastrasse 10 0472 dsseldorf, germany tel: 0211 65030 http://www.eu.necel.com/ united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908 691133 succursale fran?aise 9, rue paul dautier, b.p. 52 78142 velizy-villacoublay cdex france tel: 01 30675800 sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091 5042787 tyskland filial t?by centrum entrance s (7th floor) 18322 t?by, sweden tel: 08 6387200 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02 667541 branch the netherlands steijgerweg 6 5616 hs eindhoven, the netherlands tel: 040 2654010 [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china tel: 010 82351155 http://www.cn.necel.com/ nec electronics shanghai ltd. room 2511-2512, bank of china to w e r, 200 yincheng road central, pudong new area, shanghai 200120, p.r. china tel: 021 58885400 http://www.cn.necel.com/ nec electronics hong kong ltd. 12/f., cityplaza 4, 12 taikoo wan road, hong kong tel: 2886 9318 http://www.hk.necel.com/ nec electronics taiwan ltd. 7f, no. 363 fu shing north road ta i p e i , ta i w a n , r . o. c. tel: 02 27192377 nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253 8311 http://www.sg.necel.com/ nec electronics korea ltd. 11f., samik lavied?or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 http://www.kr.necel.com/
7 user?s manual u17566ee5v1um00 preface readers this manual is intended for users who want to understand the functions of the concerned microcontrollers. purpose this manual presents the hardware manual for the concerned microcontrollers. organization this system specification describes the following sections: ? pin function ? cpu function ? internal peripheral function module instances these microcontrollers may contain several instances of a dedicated module. in general the different instances of such modules are identified by the index ?n?, where ?n? counts from 0 to the number of instances minus one. legend symbols and notation are used as follows: ? weight in data notation: left is high order column, right is low order column ? active low notation: xxx (pin or signal name is over-scored) or /xxx (slash before signal name) ? memory map address: high order at high stage and low order at low stage note additional remark or tip caution item deserving extra attention numeric notation: ? binary: xxxx or xxx b ? decimal: xxxx ? hexadecimal: xxxx h or 0x xxxx prefixes representing powers of 2 (address space, memory capacity): ?k (kilo): 2 10 = 1024 ? m (mega): 2 20 = 1024 2 = 1,048,576 ?g (giga): 2 30 = 1024 3 = 1,073,741,824 register contents: x, x = don?t care diagrams block diagrams do not necessarily show the exact wiring in hardware but the functional structure. timing diagrams are for functional explanation purposes only, without any relevance to the real hardware implementation. further information for further information see http://www.eu.necel.com .
8 v850e/dx3 user?s manual u17566ee5v1um00
1 user?s manual u17566ee5v1um00 table of contents chapter 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.3 product series overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 chapter 2 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.1.2 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.1.3 noise elimination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2 port group confi guration registers . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.2 pin function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.3 pin data input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.4 configuration of electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.2.5 alternative input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.3 port types diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.4 port group configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.4.1 port group configuration lists. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.4.2 alphabetic pin function list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.4.3 external memory interface of pd70f3427 . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.4.4 port group 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.4.5 port group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4.6 port group 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.4.7 port group 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.8 port group 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.4.9 port group 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.4.10 port group 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.4.11 port group 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.4.12 port group 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.4.13 port group 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.4.14 port group 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.4.15 port group 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 2.4.16 port group 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 2.4.17 port group 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 2.4.18 port group 14 (pd70f3427 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.4.19 port group al . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 2.4.20 port group ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 2.4.21 port group cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2 table of contents user?s manual u17566ee5v1um00 2.4.22 port group ct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.4.23 port group dl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.4.24 port group dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 2.5 noise elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.5.1 analog filtered inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.5.2 digitally filtered inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.6 pin functions in rese t and power save modes . . . . . . . . . . . 108 2.7 recommended connec tion of unused pins . . . . . . . . . . . . . . 109 2.8 package pins assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 2.8.1 pd70f3421, pd70f3422, pd70f3423. . . . . . . . . . . . . . . . . . . . . . . . . 110 2.8.2 pd70f3424, pd70f3425, pd70f3426a . . . . . . . . . . . . . . . . . . . . . . . 111 2.8.3 pd70f3427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 chapter 3 cpu system functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.2 cpu register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3.2.1 general purpose registers (r0 to r31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 3.2.2 system register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.3 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 3.3.1 normal operation mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 3.3.2 flash programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 3.4 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 3.4.1 cpu address space and physical address space . . . . . . . . . . . . . . . . . . . . 126 3.4.2 program and data space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.5 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 3.5.1 memory areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 3.5.2 fixed peripheral i/o area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 3.5.3 recommended use of data address space. . . . . . . . . . . . . . . . . . . . . . . . . 134 3.6 write protec ted registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.7 instructions and data access times . . . . . . . . . . . . . . . . . . . . . 136 chapter 4 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 4.1.2 clock monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.1.3 power save modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.1.4 start conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.1.5 start-up guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 4.2 clock generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 4.2.1 general clock generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.2.2 sscg control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
3 table of contents user?s manual u17566ee5v1um00 4.2.3 control registers for peripheral clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.2.4 control registers for power save modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 4.2.5 clock monitor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 4.3 power save modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 4.3.1 power save modes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 4.3.2 clock generator state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.3.3 power save mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 4.3.4 cpu operation after power save mode release . . . . . . . . . . . . . . . . . . . . . 193 4.4 clock generator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 4.4.1 internal and sub oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 4.4.2 watch timer and watch calibration timer clocks . . . . . . . . . . . . . . . . . . . 196 4.4.3 clock output foutclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 4.4.4 default clock generator setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 4.4.5 operation of the clock monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 chapter 5 interrupt controller (intc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 5.2 non-maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 5.2.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 5.2.2 restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 5.2.3 non-maskable interrupt status flag (np) . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 5.2.4 nmi0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 5.3 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 5.3.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 5.3.2 restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.3.3 priorities of maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 5.3.4 xxic - maskable interrupts control register . . . . . . . . . . . . . . . . . . . . . . . . . 239 5.3.5 imr0 to imr6 - interrupt mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 5.3.6 ispr - in-service priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 5.3.7 maskable interrupt status flag (id) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 5.3.8 external maskable interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 5.3.9 software interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 5.4 edge and level dete ction configuration . . . . . . . . . . . . . . . . . 257 5.5 software exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 5.5.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 5.5.2 restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 5.5.3 exception status flag (ep). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 5.6 exception trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 5.6.1 illegal opcode definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 5.6.2 debug trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 5.7 multiple interrupt processing control . . . . . . . . . . . . . . . . . . . . 264 5.8 interrupt response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 5.9 periods in which inte rrupts are not acknowledged . . . . . . 267
4 table of contents user?s manual u17566ee5v1um00 chapter 6 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 6.1.1 flash memory address assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 6.1.2 flash memory erasure and rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 6.1.3 flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 6.1.4 boot block swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 6.2 flash self-programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 6.2.1 flash self-programming registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 6.2.2 interrupt handling during flash self-programming . . . . . . . . . . . . . . . . . . . . 277 6.3 flash programming via n-wire . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 6.4 flash programming with flash programmer . . . . . . . . . . . . . . 279 6.4.1 programming environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 6.4.2 communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 6.4.3 pin connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 6.4.4 programming method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 chapter 7 bus and memory control (bcu, memc) . . . . . . . . . . . . 289 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 7.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 7.2.1 memory banks and chip select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 7.2.2 chips select priority control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 7.2.3 peripheral i/o area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 7.2.4 npb access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 7.2.5 bus properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 7.2.6 boundary operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 7.2.7 initialization for access to external devices . . . . . . . . . . . . . . . . . . . . . . . . . 299 7.2.8 external bus mute function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 7.3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 7.3.1 bcu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 7.3.2 memory controller registers (pd70f3427 only) . . . . . . . . . . . . . . . . . . . . 311 7.4 page rom controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 7.5 configuration of memory access . . . . . . . . . . . . . . . . . . . . . . . . . 322 7.5.1 endian format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 7.5.2 wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 7.5.3 idle state insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 7.6 external devices interface timing . . . . . . . . . . . . . . . . . . . . . . . . 324 7.6.1 writing to external devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 7.6.2 reading from external devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 7.6.3 read-write operation on external devices . . . . . . . . . . . . . . . . . . . . . . . . . . 329 7.6.4 write-read operation on external devices . . . . . . . . . . . . . . . . . . . . . . . . . . 330 7.7 page rom access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 7.7.1 half word/word access with 8-bit bus or word access with 16-bit bus . . . . 332 7.7.2 byte access with 8-bit bus or byte/half word access with 16-bit bus. . . . . . 334
5 table of contents user?s manual u17566ee5v1um00 7.8 data access order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 7.8.1 access to 8-bit data busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 7.8.2 access to 16-bit data busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 chapter 8 dma controller (dmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 8.2 peripheral and cpu clock settings . . . . . . . . . . . . . . . . . . . . . . . 351 8.3 dmac registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 8.3.1 dma source address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 8.3.2 dma destination address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 8.3.3 dbcn - dma transfer count registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 8.3.4 dadcn - dma addressing control registers . . . . . . . . . . . . . . . . . . . . . . . . 358 8.3.5 dchcn - dma channel control registers . . . . . . . . . . . . . . . . . . . . . . . . . . 360 8.3.6 drst - dma restart register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 8.3.7 dtfrn - dma trigger source select register . . . . . . . . . . . . . . . . . . . . . . . . 362 8.4 dma setup and retrigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 8.4.1 dma initial setup (status after system reset). . . . . . . . . . . . . . . . . . . . . . . . 365 8.4.2 dma retrigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 8.5 automatic restart function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 8.6 transfer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 8.7 transfer object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 8.8 dma channel priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 8.9 dma transfer start factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 8.10 forcible interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 8.11 forcible termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 8.12 dma transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 8.13 transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 8.13.1 single transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 8.13.2 block transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 8.14 cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 8.14.1 simultaneous program execution and dma transfer with internal ram . . . 374 chapter 9 rom correction function (romc) . . . . . . . . . . . . . . . . . . 375 9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 9.2 ?data replacement? rom correction unit . . . . . . . . . . . . . . . . 376 9.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 9.2.2 ?data replacement? rom correction operation . . . . . . . . . . . . . . . . . . . . . 377 9.2.3 setting of rom correction addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 9.2.4 ?data replacement? rom correction registers . . . . . . . . . . . . . . . . . . . . . . 382 9.3 ?dbtrap? rom correction unit . . . . . . . . . . . . . . . . . . . . . . . . . 387 9.3.1 ?dbtrap? rom correction operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
6 table of contents user?s manual u17566ee5v1um00 9.3.2 ?dbtrap? rom correction registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 chapter 10 code protection and security . . . . . . . . . . . . . . . . . . . . . . . 393 10.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 10.2 boot rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 10.3 n-wire debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 10.4 flash writer and se lf-programming protection . . . . . . . . . . . 395 10.5 additional firmware functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 10.5.1 id-field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 10.5.2 checksum calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 10.5.3 variable reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 chapter 11 16-bit timer/event counter p (tmp) . . . . . . . . . . . . . . . . 397 11.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 11.2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 11.3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 11.4 tmp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 11.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 11.5.1 interval timer mode (tpnmd2 to tpnmd0 = 000). . . . . . . . . . . . . . . . . . . . 412 11.5.2 external event count mode (tpnmd2 to tpnmd0 = 001). . . . . . . . . . . . . . 421 11.5.3 external trigger pulse output mode (tpnmd2 to tpnmd0 = 010) . . . . . . . 430 11.5.4 one-shot pulse output mode (tpnmd2 to tpnmd0 = 011) . . . . . . . . . . . . 441 11.5.5 pwm output mode (tpnmd2 to tpnmd0 = 100) . . . . . . . . . . . . . . . . . . . . 448 11.5.6 free-running timer mode (tpnmd2 to tpnmd0 = 101) . . . . . . . . . . . . . . . 457 11.5.7 pulse width measurement mode (tpnmd2 to tpnmd0 = 110) . . . . . . . . . 474 11.5.8 timer output operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 11.6 operating precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 11.6.1 capture operation in pulse width measurement and free-running mode . . 481 11.6.2 count jitter for pclk4 to pclk7 count clocks . . . . . . . . . . . . . . . . . . . . . . 481 chapter 12 16-bit interval timer z (tmz) . . . . . . . . . . . . . . . . . . . . . . . . . 483 12.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 12.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 12.1.2 principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 12.2 tmz registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 12.3 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 12.3.1 steady operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 12.3.2 timer start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 chapter 13 16-bit multi-purpose timer g (tmg) . . . . . . . . . . . . . . . . 493 13.1 features of timer g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
7 table of contents user?s manual u17566ee5v1um00 13.2 function overview of each timer gn . . . . . . . . . . . . . . . . . . . . . 494 13.3 basic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 13.4 tmg registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 13.5 output delay operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 13.6 explanation of basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . 506 13.7 operation in free-run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 13.8 match and clear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 13.9 edge noise elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 13.10 precautions timer gn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 chapter 14 16-bit timer y (tmy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 14.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 14.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 14.1.2 principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 14.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 14.3 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 14.4 output timing calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 chapter 15 watch timer (wt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 15.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 15.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 15.1.2 principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 15.2 watch timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 15.3 watch timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 15.3.1 timing of steady operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 15.3.2 watch timer start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 15.4 watch calibrati on timer registers . . . . . . . . . . . . . . . . . . . . . . . 557 15.5 watch calibration timer operation . . . . . . . . . . . . . . . . . . . . . . . 562 chapter 16 watchdog timer (wdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 16.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 16.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 16.1.2 principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 16.1.3 watchdog timer clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 16.1.4 reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 16.2 watchdog timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 chapter 17 asynchronous serial interface (uarta) . . . . . . . . . . . 575 17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
8 table of contents user?s manual u17566ee5v1um00 17.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 17.3 uarta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 17.4 interrupt request signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 17.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 17.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 17.5.2 sbf transmission/reception format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 17.5.3 sbf transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 17.5.4 sbf reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 17.5.5 uart transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 17.5.6 continuous transmission procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 17.5.7 uart reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 17.5.8 reception errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 17.5.9 parity types and operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 17.5.10 receive data noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 17.6 baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 17.6.1 baud rate generator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 17.6.2 baud rate generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 17.6.3 baud rate calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 17.6.4 baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 17.6.5 baud rate setting example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 17.6.6 allowable baud rate range during reception . . . . . . . . . . . . . . . . . . . . . . . . 603 17.6.7 baud rate during continuous transmission . . . . . . . . . . . . . . . . . . . . . . . . . 605 17.7 cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 17.7.1 uartan behaviour during and after power save mode . . . . . . . . . . . . . . . 606 17.7.2 uartan behaviour during debugger break . . . . . . . . . . . . . . . . . . . . . . . . 606 17.7.3 uartan operation stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 chapter 18 clocked serial interface (csib) . . . . . . . . . . . . . . . . . . . . . 609 18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 18.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 18.3 csib control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 18.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 18.4.1 single transfer mode (master mode, transmission/reception mode). . . . . . 620 18.4.2 single transfer mode (master mode, reception mode) . . . . . . . . . . . . . . . . 622 18.4.3 continuous mode (master mode, transmission/reception mode) . . . . . . . . 623 18.4.4 continuous mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . 624 18.4.5 continuous reception mode (error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 18.4.6 continuous mode (slave mode, transmission/reception mode) . . . . . . . . . 626 18.4.7 continuous mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . 628 18.4.8 clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 18.5 output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 18.6 operation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
9 table of contents user?s manual u17566ee5v1um00 18.7 baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 18.7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 18.7.2 baud rate generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 18.7.3 baud rate calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 18.8 cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 18.8.1 csibn behaviour during debugger break . . . . . . . . . . . . . . . . . . . . . . . . . . 641 18.8.2 csib operation stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 chapter 19 i 2 c bus (iic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 19.2 i2c pin c onfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 19.3 i2c pin c onfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 19.4 i2c pin c onfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 19.5 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 19.6 iic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 19.7 i 2 c bus pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 19.8 i 2 c bus definitions and control methods . . . . . . . . . . . . . . . . . 669 19.8.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 19.8.2 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 19.8.3 transfer direction specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 19.8.4 acknowledge signal (ack ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 19.8.5 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 19.8.6 wait signal (wait ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 19.9 i 2 c interrupt request signals (intiicn) . . . . . . . . . . . . . . . . . . . 677 19.9.1 master device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 19.9.2 slave device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 19.9.3 slave device operation (when receiving extension code) . . . . . . . . . . . . . . 684 19.9.4 operation without communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 19.9.5 arbitration loss operation (operation as slave after arbitration loss) . . . . . . 688 19.9.6 operation when arbitration loss occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 19.10 interrupt request signal (intiicn) . . . . . . . . . . . . . . . . . . . . . . . . 695 19.11 address match detection method . . . . . . . . . . . . . . . . . . . . . . . . 696 19.12 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 19.13 extension code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 19.14 arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698 19.15 wakeup function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 19.16 communication reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 19.16.1 communication reservation function is enabled (iicfn.iicrsvn bit = 0) . . 700 19.16.2 communication reservation function is disabled (iicfn.iicrsvn bit = 1). . 704 19.17 cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
10 table of contents user?s manual u17566ee5v1um00 19.18 communication operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 19.18.1 master operation with communication reservation . . . . . . . . . . . . . . . . . . . 706 19.18.2 master operation without communication reservation . . . . . . . . . . . . . . . . . 707 19.18.3 slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 19.19 timing of data communication . . . . . . . . . . . . . . . . . . . . . . . . . . 712 chapter 20 can controller (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 20.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 20.1.1 overview of functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 20.1.2 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 20.2 can protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 20.2.1 frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 20.2.2 frame types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 20.2.3 data frame and remote frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 20.2.4 error frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 20.2.5 overload frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 20.3 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 20.3.1 determining bus priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 20.3.2 bit stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 20.3.3 multi masters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 20.3.4 multi cast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 20.3.5 can sleep mode/can stop mode function . . . . . . . . . . . . . . . . . . . . . . . . . 734 20.3.6 error control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 20.3.7 baud rate control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 20.4 connection with target system . . . . . . . . . . . . . . . . . . . . . . . . . . 744 20.5 internal registers of can controller . . . . . . . . . . . . . . . . . . . . . 745 20.5.1 can module register and message buffer addresses . . . . . . . . . . . . . . . . 745 20.5.2 can controller configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 20.5.3 can registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 20.5.4 register bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 20.6 bit set/clear function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 20.7 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 20.8 can controller initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 20.8.1 initialization of can module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 20.8.2 initialization of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 20.8.3 redefinition of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 20.8.4 transition from initialization mode to operation mode. . . . . . . . . . . . . . . . . 792 20.8.5 resetting error counter cnerc of can module. . . . . . . . . . . . . . . . . . . . . 793 20.9 message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 20.9.1 message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 20.9.2 receive data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 20.9.3 receive history list function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 20.9.4 mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
11 table of contents user?s manual u17566ee5v1um00 20.9.5 multi buffer receive block function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 20.9.6 remote frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 20.10 message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 20.10.1 message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 20.10.2 transmit history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 20.10.3 automatic block transmission (abt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806 20.10.4 transmission abort process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 20.10.5 remote frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 20.11 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 20.11.1 can sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 20.11.2 can stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 20.11.3 example of using power saving modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 20.12 interrupt function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815 20.13 diagnosis functions and special operational modes . . . . . 816 20.13.1 receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 20.13.2 single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 20.13.3 self-test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 20.13.4 receive/transmit operation in each operation mode. . . . . . . . . . . . . . . . . . 819 20.14 time stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 20.14.1 time stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 20.15 baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 20.15.1 baud rate setting conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 20.15.2 representative examples of baud rate settings . . . . . . . . . . . . . . . . . . . . . 825 20.16 operation of can controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 chapter 21 a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 21.1 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 21.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 21.3 adc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 21.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 21.4.1 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 21.4.2 trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 21.4.3 operation modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 21.4.4 power-fail compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 21.5 cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876 21.6 how to read a/d converter characteristics table . . . . . . . . 878 chapter 22 stepper motor controller/driver (stepper-c/d) . . . . 883 22.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 22.1.1 driver overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 22.2 stepper motor controller/driver registers . . . . . . . . . . . . . . . . 886
12 table of contents user?s manual u17566ee5v1um00 22.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891 22.3.1 stepper motor controller/driver operation . . . . . . . . . . . . . . . . . . . . . . . . . 891 22.4 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894 22.4.1 timer counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894 22.4.2 automatic pwm phase shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 chapter 23 lcd controller/driver (lcd-c/d) . . . . . . . . . . . . . . . . . . . . 897 23.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897 23.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898 23.1.2 lcd panel addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899 23.2 lcd-c/d registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 23.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 23.3.1 common signals and segment signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 23.3.2 activation of lcd segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 23.4 display example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 chapter 24 lcd bus interface (lcd-i/f) . . . . . . . . . . . . . . . . . . . . . . . . . 911 24.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911 24.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912 24.1.2 lcd bus interface access modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 24.1.3 access types to the lbdata0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 24.1.4 interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 24.2 lcd bus interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 24.3 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922 24.3.1 timing dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922 24.3.2 lcd bus i/f states during and after accesses . . . . . . . . . . . . . . . . . . . . . . 923 24.3.3 writing to the lcd bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 24.3.4 reading from the lcd bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926 24.3.5 write-read-write sequence on the lcd bus . . . . . . . . . . . . . . . . . . . . . . . 928 chapter 25 sound generator (sg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 25.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 25.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930 25.1.2 principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931 25.2 sound generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 25.3 sound generator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 25.3.1 generating the tone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 25.3.2 generating the volume information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940 25.4 sound generator application hints . . . . . . . . . . . . . . . . . . . . . . 945 25.4.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 25.4.2 start and stop sound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 25.4.3 change sound volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
13 table of contents user?s manual u17566ee5v1um00 25.4.4 intsg0 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 25.4.5 constant sound volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946 25.4.6 generate special sounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946 chapter 26 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947 26.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947 26.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949 26.2.1 devices pd70f3421, pd70f3422, pd70f3423. . . . . . . . . . . . . . . . . . 949 26.2.2 devices pd70f3424, pd70f3425, pd70f3426a . . . . . . . . . . . . . . . . 950 26.2.3 device pd70f3427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 26.3 voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 chapter 27 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953 27.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953 27.1.1 general reset performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954 27.1.2 reset at power-on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957 27.1.3 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 27.1.4 reset by watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959 27.1.5 reset by clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959 27.1.6 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959 27.2 reset registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960 chapter 28 voltage comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 28.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 28.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 28.1.2 comparison results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 28.1.3 stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 28.2 voltage comparator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 28.3 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 chapter 29 on-chip debug unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 29.1 functional outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 29.1.1 debug functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 29.1.2 security function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 29.2 controlling the n-wire interface . . . . . . . . . . . . . . . . . . . . . . . . . . 974 29.3 n-wire enabling methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976 29.3.1 starting normal operation after reset and respoc . . . . . . . . . . . . . . . . 976 29.3.2 starting debugger after reset and respoc . . . . . . . . . . . . . . . . . . . . . . 976 29.3.3 n-wire activation by reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977 29.4 connection to n-wire emulator . . . . . . . . . . . . . . . . . . . . . . . . . . 978 29.4.1 kel connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978 29.5 restrictions and caut ions on on-chip debug function . . 982
14 table of contents user?s manual u17566ee5v1um00 appendix a registers access times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 appendix b special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . 997 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
15 user?s manual u17566ee5v1um00 chapter 1 introduction v850e/dx3 series the v850e/dx3 is a product series in nec electronics? v850 family of single- chip microcontrollers designed for automotive applications. beside the v850e/ dx3 - dj3/dl3 the product series comprises the v850e/dg3 devices. for further information about v850e/dg3 refer to the user?s manual ?v850e/dx3 - dg3? document number u18349ee 1.1 general the v850e/dx3 single-chip microcontroller devices make the performance gains attainable with 32-bit risc-based controllers available for embedded control applications. the integrated v850 cpu offers easy pipeline handling and programming, resulting in compact code size comparable to 16-bit cisc cpus. the v850e/dx3 provide an excellent combination of general purpose peripheral functions, like serial communication interfaces (uarts, clocked serial interfaces), timers, and measurement inputs (a/d converter), with dedicated can network support. the devices offer specific power-saving modes to manage the power consumption effectively under varying conditions. thus equipped, the v850e/dx3 product line is ideally suited for automotive applications, like dashboard or body. it is also an excellent choice for other applications where a combination of sophisticated peripheral functions and can network support is required. (1) v850e cpu the v850e cpu core is a risc processor. through the use of basic instructions that can be executed in one clock period combined with an optimized pipeline architecture, it achieves marked improvements in instruction execution speed. in addition, to make it ideal for use in digital control applications, a 32-bit hardware multiplier enables this cpu to support multiply instructions, saturated multiply instructions, bit operation instructions, etc. through two-byte basic instructions and instructions compatible with high level languages, the object code efficiency in a c compiler is increased, and program size can be reduced. further, because the on-chip interrupt controller provides high-speed interrupt response and processing, this device is well suited for high level real-time control applications. (2) on-chip flash memory the v850e/dx3 microcontrollers have on-chip flash memory. it is possible to program the controllers directly in the target environment where they are mounted. with this feature, system development time can be reduced and system maintainability after shipping can be markedly improved.
16 chapter 1 introduction user?s manual u17566ee5v1um00 (3) a full range of software development tools a development system is available that includes an optimized c compiler, debugger, in-circuit emulator, simulator, system performance analyzer, and other elements. 1.2 features summary the following table provides a quick summary of the most outstanding features. table 1-1 v850e/dx3 features summary (1/4) cpu core v850e1 number of instructions 81 minimum instruction execution time ? 15.625 ns (@  = 64 mhz) (pd70f3424, pd70f3425, pd70f3426a, pd70f3427) a ? 31.25 ns (@  = 32 mhz) ( pd70f3421, pd70f3422, pd70f3423) a general registers 32 registers (32 bits each) instruction set v850e (compatible with v850 plus additional powerful instructions for reducing code and increasing execution speed) signed multiplication (16 bits 16 bits  32 bits or 32 bits 32 bits  64 bits): 1 to 2 clocks saturated operation instructions (with overflow/underflow detection) 32-bit shift instructions: 1 clock bit manipulation instructions load/store instructions with long/short format signed load instructions internal flash memory size ? 2 mb (pd70f3426a) ? 1 mb (pd70f3427, pd70f3425) ? 512 kb (pd70f3424, pd70f3423) ? 384 kb (pd70f3422) ? 256 kb (pd70f3421) flash protection ? n-wire security function ? external programmer security function secure self programming internal data ram size ? 84 kb (pd70f3426a) ? 60 kb (pd70f3427) ? 32 kb (pd70f3425) ? 24 kb (pd70f3424) ? 20 kb (pd70f3423) ? 16 kb (pd70f3422) ? 12 kb (pd70f3421)
17 introduction chapter 1 user?s manual u17566ee5v1um00 clock generator internal spread-spectrum pll (sscg) 12-fold/16-fold, up to 64 mhz 5 % bc internal pll 8-fold, 32 mhz cpu frequency range ? up to 64 mhz (pd70f3424, pd70f3425, pd70f3426a, pd70f3427) ac ? up to 32 mhz (pd70f3421, pd70f3422, pd70f3423) ac peripheral frequency range up to 16 mhz main crystal frequency range (main oscillator) 4 mhz sub oscillator 32 khz (typ.) internal oscillator 240 khz (typ.) clock supervision 2 channels: ? main oscillator monitor ? sub oscillator monitor auxiliary frequency output built-in power saving modes halt / idle / watch / sub-watch / stop external memory bus interface (pd70f3427 only) address/data separated busses 24/32-bit chip select signals 4 dma controller number of channels 4 i/o ports input/output ports ? pd70f3427: 101 ? all others: 98 input ports 16 a/d converter number of channels ? 16 (pd70f3424, pd70f3425, pd70f3426a, pd70f3427) ? 12 (pd70f3421, pd70f3422, pd70f3423) resolution 10-bit conversion modes ? continuous select mode ? continuous scan mode ? timer trigger mode ? software trigger mode analog input channels shared with digital input port functionality table 1-1 v850e/dx3 features summary (2/4)
18 chapter 1 introduction user?s manual u17566ee5v1um00 serial interfaces synchronous: csi (csib) ? 3 channels (pd70f3424, pd70f3425, pd70f3426a, pd70f3427) ? 2 channels (pd70f3421, pd70f3422, pd70f3423) asynchronous: uart (uarta) 2 channels with lin support i 2 c (iic) 2 channels can (can) ? 3 channels with 32 message buffers each (pd70f3421, pd70f3422, pd70f3423, pd70f3424, pd70f3425, pd70f3427) ? 2 channels with 32 message buffers each (pd70f3426a) timers 16-bit multi purpose timer/event counter (tmp) 4 channels 16-bit multi purpose timer/counter (tmg) ? 3 channels 16-bit multi purpose timer/counter (tmz) ? 10 channels (pd70f3424, pd70f3425, pd70f3426a, pd70f3427) ? 6 channels (pd70f3421, pd70f3422, pd70f3423) 16-bit pwm/pfm timer (tmy) 1 channel watch timer (wt) 1 channel watch calibration timer (wct) 1 channel watchdog timer (wdt) 1 channel lcd controller/driver (pd70f3421, pd70f3422, pd70f3423) segment signal output max. 40 common signal output max. 4 modes 1/4 duty, 1/3 bias lcd bus interface bus width 8-bit parallel bus control modes 2 modes: ? rd strobe and wr strobe (?mod80?) ? rd/wr signal and data strobe (?mod68?) transfer speed 100 khz to 3.2 mhz stepper motor controller/driver number of channels 6 resolution 8-bit and 8-bit + 1 sound generator number of channels 1 volume 9-bit volume level accuracy sound frequency 245 hz to 6 khz with min. resolution of 20 hz sound duration 256 steps table 1-1 v850e/dx3 features summary (3/4)
19 introduction chapter 1 user?s manual u17566ee5v1um00 note the can controller of this device fulfils the requirements according iso 11898. additionally, the can controller was tested according to the test procedures required by iso 16845. the can controller has successfully passed all test patterns. beyond these test patterns, other tests like robustness tests and processor interface tests as recommended by c&s/fh wolfenbuettel have been performed with success. interrupts and exceptions non-maskable interrupts 2 sources maskable interrupts ? 92 sources (pd70f3424, pd70f3425, pd70f3426a, pd70f3427) ? 84 sources (pd70f3421, pd70f3422, pd70f3423) software exceptions 32 sources exception trap 2 sources rom correction number of channels 8 channels by dbtrap on-chip debug interface number of interfaces 1 connection of an external n-wire emulator internal voltage comparators number of channels 2 power supply supervision power-on-clear generates reset at power-up and in case of power loss single supply operating voltage range 4.0 v to 5.5 v a temperature range range t a = ?40 to +85c ? @  = 67.2 mhz (pd70f3424, pd70f3425, pd70f3426a, pd70f3427) a ? @  = 32 mhz (pd70f3421, pd70f3422, pd70f3423) a package package ? pd70f3427: 208-pin qfp ? all others: 144-pin qfp package size ? pd70f3427: 28 mm 28 mm ? all others: 20 mm 20 mm pin pitch 0.5 mm technology cmos a) refer to data sheet b) the maximum cpu frequency as specified in the data sheet must not be exceeded. c) center output frequency of the sscg, can be modulated up to +/- 5%. table 1-1 v850e/dx3 features summary (4/4)
20 chapter 1 introduction user?s manual u17566ee5v1um00 1.3 product series overview ta b l e 1 - 2 shows the common and different features of the microcontrollers. table 1-2 v850e/dx3 product series overview part number v850e/dl3 v850e/dj3 pd70f3427 pd70f3426a pd70f3425 pd70f3424 pd70f3423 pd70f3422 pd70f3421 internal memory flash 1 mb 1 mb + 1 mb a a) the additional 1 mb flash memory respectively 24 kb ram is accessible via the vsb, and thus the access requires an additional cpu clock cycle. 1 mb 512 kb 384 kb 256 kb ram 60 kb 60 kb + 24 kb a 32 kb 24 kb 20 kb 16 kb 12 kb external memory interface provided ? dma 4 ch operating clock b b) refer to the data sheet. main oscillator with sscg c c) sscg: spread spectrum clock generator 67.2 mhz max. 32 mhz max. internal oscillator 240 khz typ. sub oscillator 32 khz typ. i/o ports input/output 101 98 input 16 a/d converter 16 channels 12 channels timers tmz 10 channels 6 channels tmp 4 channels tmg 3 channels tmy 1 channel wdt 1 channel watch provided watch calibration provided serial interfaces can 3 channels 2 channels 3 channels uarta 2 channels csib 3 channels 2 channels i 2 c 2 channels interrupts external (maskable) 8 channels 7 channels internal (maskable) 84 channels 77 channels nmi 2 channels (1 external, 1 internal) other functions rom correction by dbtrap 8 channels 2 x 8 channels 8 channels power-on-clear provided voltage comparator 2 channels clock supervision 2 channels sound generator 1 channel stepper motor controller/driver 6 channels lcd-controller/driver none 40 x 4 lcd bus interface provided auxiliary frequency output provided on-chip debug provided operating voltage b 3.5 v to 5.5 v package 208-pin qfp 144-pin lqfp
21 introduction chapter 1 user?s manual u17566ee5v1um00 1.4 description figure 1-1 provides a functional block diagram of the v850e/dj3 (pd70f3421, pd70f3422, pd70f3423, pd70f3424, pd70f3425, pd70f3426a) microcontrollers. figure 1-1 v850e/dj3 (pd70f3421, pd70f3422, pd70f3423, pd70f3424, pd70f3425, pd70f3426a) block diagram 16-bit timer tmy0 bus control unit npb (nec peripheral bus) cpu core power supply interrupt controller nmi 2 x uarta rxda0, rxda1 txda0, txda1 3/2 x csib sib0, sib1, sib2 note 2 sob0, sob1, sob2 note 2 s ckb0, s ckb1, s ckb2 note 2 ports p00 to p07 p16 to p17 p90 to p97 p80 to p87 p70 to p715 p60 to p67 p50 to p57 p40 to p47 p30 to p37 p20 to p27 intp0 to intp6 brg brg dma p100 to p107 p110 to p1 17 p120 to p127 p130 to p137 dms ddi ddo dck drst n-wire debug i/f 16-bit timer wct watch and watch calibration timer 16-bit timer wt watchdog timer 3 /2 x can crxd0, crxd1, crxd2 ctxd0, ctxd1, ctxd2 stepper motor c/d sm41 to sm44 sm11 to sm14 sm21 to sm24 sm31 to sm34 sm61 to sm64 sm51 to sm54 note 2 note 1 lcd c/d seg0 to seg39 com0 to com3 lcd bus i/f dbd0 to dbd7 dbrd dbwr sg0 sgoa sgo/sgof av ref ani0-ani11 10-bit adc 16/12 channels 16-bit timer tmg0 - tmg2 tig01 to tig04 tig11 to tig14 tig20 to tig25 tog01 to tog04 tog11 to tog14 tog21 to tog24 16-bit timer tmp0 - tmp3 tip00, tip01 tip10, tip11 tip20, tip21 tip30, tip31 top00, top01 top10, top11 top20, top21 top30, top31 2 x i 2 c sda0, sda1 scl0, scl1 vcmp0, vcmp1 2 x voltage comparator vcmpo0, vcmpo1 reset clock generator xt1 xt2 sub oscillator internal oscillator fout main and sub oscillator supervision clock generator memory power and reset serial interfaces control interfaces timers auxiliary functions bus bridge system controller standby controller on-chip debug unit rom correction cpu reset poc fout ram not e 8 fl as h not e 7 not e 2 note 1 intp7 note 1 note 3 ani12-ani15 note 3 note 4 not e 6 16-bit timer tmz0 - tmz5 16-bit t imer tmz6 - tmz9 x1 x2 main oscillator spread spectrum pll pll rom correction 1 mb vsb flash not e 9 24 kb vsb ram not e 10 vsb (v850 system bus) not e 5 note 5 note 5
22 chapter 1 introduction user?s manual u17566ee5v1um00 ta b l e 1 - 3 summarizes the different features of the of the v850e/dj3 (pd70f3421, pd70f3422, pd70f3423, pd70f3424, pd70f3425, pd70f3426a) microcontrollers, marked as ?notes? in figure 1-1 . table 1-3 feature set differences note feature pd70f3426a pd70f3425 pd70f3424 pd70f3423 pd70f3422 pd70f3421 1intp7  ??? 2 csib2  ??? 3ani12 to ani15  ??? 4 lcd-c/d ? ? ?  5can2 ?  6tmz6 to tmz9  ??? 7 flash 1 mb 1 mb 512 kb 512 kb 384 kb 256 kb 8 ram 60 kb 32 kb 24 kb 20 kb 16 kb 12 kb 9 vsb flash 1 mb ? ? ? ? ? 10 vsb ram 24 kb ? ? ? ? ?
23 introduction chapter 1 user?s manual u17566ee5v1um00 figure 1-2 provides a functional block diagram of the v850e/dl3 pd70f3427 microcontroller. figure 1-2 v850e/dl3 (pd70f3427) block diagram b us control unit npb (nec peripher a l b us ) cpu core power su pply interr u pt controller nmi 2 x uarta rxda0, rxda1 txda0, txda1 3 x c s ib s ib0, s ib1, s ib2 s ob0, s ob1, s ob2 s ckb0, s ckb1, s ckb2 port s p00 to p07 p16 to p17 p90 to p97 p 8 0top 8 7 p70 to p715 p60 to p67 p50 to p57 p40 to p47 p 3 0top 3 7 p20 to p27 brg brg dma ram p100 to p107 p110 to p1 17 p120 to p127 p1 3 0top1 3 7 dm s ddi ddo dck dr s t n-wire de bu g i/f 16- b it timer wct w a tch a nd w a tch c a li b r a tion timer 16- b it timer wt w a tchdog timer 3 x can crxd0, crxd1, crxd2 ctxd0, ctxd1, ctxd2 s o u nd gener a tor s goa s go/ s gof 10- b it adc 16 ch a nnel s ani0-ani15 16- b it timer tmg0 - tmg2 16- b it timer tmp0 - tmp 3 tip00, tip01 tip10, tip11 tip20, tip21 tip 3 0, tip 3 1 top00, top01 top10, top11 top20, top21 top 3 0, top 3 1 2 x i 2 c s da0, s da1 s cl0, s cl1 vcmp0, vcmp1 2 x volt a ge comp a r a tor vcmpo0, vcmpo1 re s et clock gener a tor xt1 xt2 sub o s cill a tor intern a l o s cill a tor fout m a in a nd sub o s cill a tor su pervi s ion clock gener a tor memory power a nd re s et s eri a l interf a ce s control interf a ce s timer s a u xili a ry f u nction s b us bridge s y s tem controller s t a nd b y controller on-chip de bu g unit rom correction cpu re s et poc fout fl as h intp0 to intp7 16- b it timer tmz0 - tmz9 x1 x2 m a in o s cill a tor s pre a d s pectr u m pll pll memory controller bclk wait a0 to a2 3 d16 to d 3 1 wr rd be 3 to be0 c s3 , c s 4 c s 0, c s 1 d0 to d15 p140 to p142 tig01 to tig04 tig11 to tig14 tig20 to tig25 tog01 to tog04 tog11 to tog14 tog21 to tog24 lcd b us i/f dbwr dbd0 to dbd7 dbrd s m41 to s m44 s m11 to s m14 s m21 to s m24 s m 3 1 to s m 3 4 s m61 to s m64 s m51 to s m54 s tepper motor c/d 16- b it timer tmy0
24 chapter 1 introduction user?s manual u17566ee5v1um00 structure of the diagram in the diagram, the building blocks are grouped according to their function. at the top of the diagram, you find the functions for controlling power supply and reset. the upper right-hand section shows the building blocks of the cpu system and the memory interface components. the i/o ports are summarized below that section. the left-hand section of the block diagram identifies the interfaces to peripherals and also the built-in timers. all these components are connected to and can be controlled via the internal bus. the clock generator, depicted in the lower right-hand section, plays a central role. it generates and monitors not only the clocks for the cpu and the peripheral interfaces, but also governs the power save modes that can be entered when the device is not in use. structure of the manual this manual explains how to use the v850e/dx3 microcontroller devices. it provides comprehensive information about the building blocks, their features, and how to set registers in order to enable or disable specific functions. the manual provides individual chapters for the building blocks. these chapters are organized according to the grouping in the diagram. ? core functions ?pin functions? on page 27 ?cpu system functions? on page 113 ?clock generator? on page 139 ?interrupt controller (intc)? on page 201 ? memory access ?flash memory? on page 269 ?bus and memory control (bcu, memc)? on page 289 ?dma controller (dmac)? on page 349 ?rom correction function (romc)? on page 375 ?code protection and security? on page 393 ?timers ?16-bit timer/event counter p (tmp)? on page 397 ?16-bit interval timer z (tmz)? on page 483 ?16-bit multi-purpose timer g (tmg)? on page 493 ?watch timer (wt)? on page 545 ?watchdog timer (wdt)? on page 565 ? serial interfaces ?asynchronous serial interface (uarta)? on page 575 ?clocked serial interface (csib)? on page 609 ?i 2 c bus (iic)? on page 645 ?can controller (can)? on page 719 ? control interfaces ?a/d converter (adc)? on page 857 ?stepper motor controller/driver (stepper-c/d)? on page 883 ?lcd controller/driver (lcd-c/d)? on page 897 ?lcd bus interface (lcd-i/f)? on page 911 ?sound generator (sg)? on page 929
25 introduction chapter 1 user?s manual u17566ee5v1um00 ? power and reset ?power supply scheme? on page 1 ?reset? on page 953 ?voltage comparator? on page 963 ? auxiliary functions ?on-chip debug unit? on page 969 1.5 ordering information table 1-4 v850e/dx3 ordering information nec order code pin/package memory size remarks UPD70F3421gj(a)-gae-qs-ax 144 pin lqfp 256 kb flash ? upd70f3422gj(a)-gae-qs-ax 144 pin lqfp 384 kb flash ? upd70f3423gj(a)-gae-qs-ax 144 pin lqfp 512 kb flash ? upd70f3424gj(a)-gae-qs-ax 144 pin lqfp 512 kb flash ? upd70f3425gj(a)-gae-qs-ax 144 pin lqfp 1 mb flash ? upd70f3426agj(a)-gae-qs-ax 144 pin lqfp 2 mb flash vsb flash and ram upd70f3427gd(a)-lml-qs-ax 208 pin qfp 1 mb flash external bus i/f
26 chapter 1 introduction user?s manual u17566ee5v1um00
27 user?s manual u17566ee5v1um00 chapter 2 pin functions this chapter lists the ports of the microcontroller. it presents the configuration of the ports for alternative functions. noise elimination on input signals is explained and a recommendation for the connection of unused pins is given at the end of the chapter. 2.1 overview the microcontroller offers various pins for input/output functions, so-called ports. the ports are organized in port groups. to allocate other than general purpose input/output functions to the pins, several control registers are provided. for a description of the terms pin, port or port group, see ?terms? on page 32 . features summary ? number of ports and port groups: ? 5v i/o: can be used as 3v i/o with degraded electrical parameters. please refer to the data sheet. ? 24 high-drive ports for direct stepper motor drive. ? configuration possible for individual pins. ? the following features can be selected for most of the pins: ? one out of two input thresholds ? one out of two input characteristics (schmitt and non-schmitt) ? output current limit ? open drain emulation ? the following registers are offered for most of the ports: ? direct register for reading the pin values ? port register with selectable read source (for improved bit set / bit clear capabilities) device number of ports number of port groups i/o ports input ports pd70f3427 101 16 15 all others 98 16 14
28 chapter 2 pin functions user?s manual u17566ee5v1um00 2.1.1 description this microcontroller has the port groups shown below. figure 2-1 port groups port gro u p 2 p20 to p27 port gro u p 7 p70 to p715 port gro u p 0 p00 to p07 port gro u p 8 p 8 0 p 8 7 to por t gro u p 3 p 3 0 to p 3 7 port gro u p 1 p16 p17 por t gro u p 4 p40 to p47 port gro u p 5 p50 to p57 por t gro u p 6 p60 to p67 port gro u p 9 p90 p97 to port gro u p 10 p100 p107 to port gro u p 11 p110 p117 to por t gro u p 12 p120 p127 to port gro u p 1 3 p1 3 0 p1 3 7 to port gro u p 14 ( pd70f 3 427 only) p140 p142 to mem-i/f extern a l memor y interf a ce ( pd70f 3 427 only)
29 pin functions chapter 2 user?s manual u17566ee5v1um00 port group overview ta b l e 2 - 1 gives an overview of the port groups. for each port group it shows the supported functions in port mode and in alternative mode. any port group can operate in 8-bit or 1-bit units. port group 7 can additionally operate in 16-bit units. table 2-1 functions of each port group (1/2) port group name function port mode alternative mode 0 8-bit input/output ? external interrupt 0 to 6 ? non maskable interrupt ? n-wire debug interface reset ? output state of internal voltage comparators 0 and 1 1 2-bit input/output ? i 2 c0 data/clock line 2 8-bit input/output ? timer tmg0 to tmg1 channels ? i 2 c1 data/clock line ? lcd controller segment signal output (pd70f3421, pd70f3422, pd70f3423 only) 3 8-bit input/output ? uarta0 transmit/receive data, ? uarta1 transmit/receive data ? i 2 c1 data/clock line ? lcd controller segment signal output (pd70f3421, pd70f3422, pd70f3423 only) ? timer tmg2 channels ? timer tmp0 to tmp3 channels ? external memory interface data lines 18, 19 (pd70f3427 only) 4 8-bit input/output ? clocked serial interface csib0 data/clock line ? clocked serial interface csib1 data/clock line ? external interrupt 6 ? lcd controller segment signal output (pd70f3421, pd70f3422, pd70f3423 only) ? can0 transmit/receive data 5 8-bit input/output ? external interrupt 7 (pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only) ? sound generator outputs ? frequency output ? n-wire interface signals ? can1 transmit/receive data ? uarta1 transmit/receive data 6 8-bit input/output ? timer tmp0 to tmp3 channels ? timer tmg2 channels ? lcd controller segment signal output (pd70f3421, pd70f3422, pd70f3423 only) ? i 2 c0 data/clock line 7 16-bit input ? a/d converter input - pd70f3424, pd70f3425, pd70f3426a, pd70f3427: 16 channels - pd70f3421, pd70f3422, pd70f3423: 12 channels
30 chapter 2 pin functions user?s manual u17566ee5v1um00 8 8-bit input/output ? clocked serial interface csib2 data/clock line (pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only) ? lcd controller segment signal output (pd70f3421, pd70f3422, pd70f3423 only) ? timer tmy0 output ? frequency output ? inverted frequency output ? external interrupt 7 (pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only) ? uarta0 transmit/receive data ? external memory interface data lines 16, 17 (pd70f3427 only) 9 8-bit input/output ? lcd bus i/f data lines (pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only) ? clocked serial interface csib1 data/clock line ? clocked serial interface csib2 data/clock line (pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only) ? lcd controller segment/common signal output (pd70f3421, pd70f3422, pd70f3423 only) ? external memory interface data lines 24 to 31 (pd70f3427 only) 10 8-bit input/output ? timer tmp0 to tmp3 channels ? lcd bus i/f read/write strobe ? lcd controller segment signal output (pd70f3421, pd70f3422, pd70f3423 only) ? clocked serial interface csib0 data/clock line ? external memory interface data lines 20 to 23 (pd70f3427 only) 11 8-bit input/output ? stepper motor controller/driver outputs ? timer tmg2 channels (pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only) ? sound generator outputs 12 8-bit input/output ? stepper motor controller/driver outputs 13 8-bit input/output ? stepper motor controller/driver outputs ? timer tmg0 to tmg1 channels 14 3-bit input/output external memory interface for pd70f3427 only: ? bus clock ? byte enable 2, 3 mem-i/f ? external memory interface (pd70f3427 only): ? address lines 0 to 23 ? chip selects 0, 1, 3, 4 ? read/write strobe ? data wait request ? byte enable 0, 1 ? data lines 0 to 15 table 2-1 functions of each port group (2/2) port group name function port mode alternative mode
31 pin functions chapter 2 user?s manual u17566ee5v1um00 pin configuration to define the function and the electrical characteristics of a pin, several control registers are provided. ? for a general description of the registers, see ?port group configuration registers? on page 33 . ? for every port, detailed information on the configuration registers is given in ?port group configuration? on page 54 . there are three types of control circuits, defined as port types. for a description of the port types, see ?port types diagrams? on page 49 .
32 chapter 2 pin functions user?s manual u17566ee5v1um00 2.1.2 terms in this section, the following terms are used: ?pin denotes the physical pin. every pin is uniquely denoted by its pin number. a pin can be used in several modes. depending on the selected mode, a pin name is allocated to the pin. ? port group denotes a group of pins. the pins of a port group have a common set of port mode control registers. ? port mode / port a pin in port mode works as a general purpose input/output pin. it is then called ?port?. the corresponding name is pnm. for example, p07 denotes port 7 of port group 0. it is referenced as ?port p07?. ? alternative mode in alternative mode, a pin can work in various non-general purpose input/ output functions, for example, as the input/output pin of on-chip peripherals. the corresponding pin name depends on the selected function. for example, pin intp0 denotes the pin for one of the external interrupt inputs. note that for example p00 and intp0 denote the same physical pin. the different names indicate the function in which the pin is being operated. ? port type a control circuit evaluates the settings of the configuration registers. there are different types of control circuits, called ?port types?. 2.1.3 noise elimination the input signals at some pins are passing a filter to remove noise and glitches. the microcontroller supports both analog and digital filters. the analog filters are always applied to the input signals, whereas the digital filters can be enabled/disabled by control registers. see ?noise elimination? on page 104 for a detailed description.
33 pin functions chapter 2 user?s manual u17566ee5v1um00 2.2 port group configuration registers this section starts with an overview of all configuration registers and then presents all registers in detail. the configuration registers are classified in the following groups: ? ?pin function configuration? on page 34 ? ?pin data input/output? on page 39 ? ?configuration of electrical characteristics? on page 41 ? ?alternative input selection? on page 44 2.2.1 overview for the configuration of the individual pins of the port groups, the following registers are used: n = 0 to 14 table 2-2 registers for port group configuration register name shortcut function port mode register pmn pin function configuration port mode control register pmcn port function control register pfcn port lcd control register plcdcn on-chip debug mode register ocdm port register pn pin data input/output port read control register prcn port pin read register pprn port drive strength control register pdscn configuration of electrical characteristics port input characteristic control register piccn port input level control register pilcn port open drain control register podcn peripheral function select register pfsr0 to pfsr3 alternative input selection
34 chapter 2 pin functions user?s manual u17566ee5v1um00 2.2.2 pin function configuration the registers for pin function configuration define the general function of a pin: ? input mode or output mode ? port mode or alternative mode ? selection of one of the alternative output functions alt1-out/alt2-out ? pin usage for lcd controller/driver output lcd_out ? normal mode or on-chip debug mode (n-wire interface) an overview of the register settings is given in the table below. table 2-3 pin function configuration (overview) function registers i/o ocdm plcdc pmc pfc pm port mode (output) 0 0 0 x0o port mode (input) x 1 i alternative output 1 mode 1 00o alternative output 2 mode 1 0 o alternative input mode x 1 i lcd signal output (segment or common signal) 1xxxo on-chip debug mode a a) in on-chip debug mode, the corresponding pins are automatically set as input or output pins to provide the n-wire interface. in this mode the configuration of these pins can not be changed by the pin configuration registers. 1xxxxi/o
35 pin functions chapter 2 user?s manual u17566ee5v1um00 (1) pmn - port mode register the 8-bit pmn register specifies whether the individual pins of the port group n are in input mode or in output mode. access this register can be read/written in 8-bit and 1-bit units. address see ?port group configuration? on page 54 initial value ff h . this register is initialized by any reset. 76543210 pmn7 pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 r/w r/w r/w r/w r/w r/w r/w r/w table 2-4 pmn register contents bit position bit name function 7 to 0 pmn[7:0] specifies input/output mode of the corresponding pin 0: output mode (output enabled) 1: input mode (output disabled)
36 chapter 2 pin functions user?s manual u17566ee5v1um00 (2) pmcn - port mode control register the pmcn register specifies whether the individual pins of port group n are in port mode or in alternative mode. for port groups with up to eight ports, this is an 8-bit register. for port groups with up to 16 ports, this is a 16-bit register. access this register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. address see ?port group configuration? on page 54 initial value 00 h or 0000 h . this register is initialized by any reset. (3) pfcn - port function control register if a pin is in alternative mode and serves as an output pin (pmn.pmnm = 0) some pins offer two output functions alt1-out and alt2-out. the 8-bit pfcn register specifies which output function of a pin is to be used. access this register can be read/written in 8-bit and 1-bit units. address see ?port group configuration? on page 54 initial value pfc0: 20 h other pfcn: 00 h this register is initialized by any reset. 76543210 pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 r/w r/w r/w r/w r/w r/w r/w r/w 1514131211109876543210 pmcn15 pmcn14 pmcn13 pmcn12 pmcn11 pmcn10 pmcn9 pmcn8 pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 2-5 pmcn register contents bit position bit name function 7 to 0 or 15 to 0 pmcn[7:0] or pmc[15:0] specifies the operation mode of the corresponding pin 0: port mode 1: alternative mode 76543210 pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 r/w r/w r/w r/w r/w r/w r/w r/w table 2-6 pfcn register contents bit position bit name function 7 to 0 pfcn[7:0] specifies the output function of the pin 0: alternative output mode 1 (alt1-out) 1: alternative output mode 2 (alt2-out) see ?port group configuration? on page 54 for a list of the possible output modes.
37 pin functions chapter 2 user?s manual u17566ee5v1um00 (4) plcdcn - port lcd control register some port groups comprise pins for signal output of the lcd controller driver. for those port groups, the 8-bit plcdcn register specifies whether an individual pin of port group n serves as an output pin of the lcd controller/ driver or not. access this register can be read/written in 8-bit and 1-bit units. address see ?port group configuration? on page 54 initial value 00 h . this register is initialized by any reset. note if plcdcn.plcdcnm = 1, the settings of the bits m in registers pmn, pmcn, and pfcn are neglected. 76543210 plcdcn7 plcdcn6 plcdcn5 plcdcn4 plcdcn3 plcdcn2 plcdcn1 plcdcn0 r/w r/w r/w r/w r/w r/w r/w r/w table 2-7 plcdcn register contents bit position bit name function 7 to 0 plcdcn[7:0] enables lcd function of the pin: 0: pin is not allocated to the lcd controller/driver. pin function is specified in pmn, pmcn and pfcn 1: pin serves as an output pin of the lcd controller/ driver. data is output directly from buffers of the lcd controller/driver. bit pn.pnm is neglected.
38 chapter 2 pin functions user?s manual u17566ee5v1um00 (5) ocdm - on-chip debug mode register the 8-bit ocdm register specifies whether dedicated pins of the microcontroller operate in normal operation mode or can be used for on-chip debugging (n-wire interface). the setting of this register concerns only those pins that can be used for the n-wire interface: p05/drst , p52/ddi, p53/ddo, p54/dck, and p55/dms. to make these pins available for on-chip debugging, bit ocdm.ocdm0 must be set while pin drst is high. if the on-chip debug mode is selected, the corresponding pins are automatically set as input or output pins, respectively. setting of bits pmn.pmnm is not necessary. for more details refer to ?on-chip debug unit? on page 969 . access this register can be read/written in 8-bit and 1-bit units. address ffff f9fc h initial value 00 h /01 h : ? after power-on clear reset, the normal operation mode is selected (ocdm.ocdm0 = 0). ? after external reset, the dedicated pins are available for on-chip debugging (ocdm.ocdm0 = 1). ? after any other reset, bit ocdm0 holds the same value as before the reset. note if the pins p05/drst , p52/ddi, p53/ddo, p54/dck, and p55/dms are used as n-wire interface pins their configuration can not be changed by the pin configuration registers. 76543210 0000000ocdm0 r/w r/w r/w r/w r/w r/w r/w r/w table 2-8 ocdm register contents bit position bit name function 0 ocdm0 enables/disables n-wire interface: 0: pins are used in normal operation mode (port mode or alternative mode). 1: pins are used in on-chip debug mode.
39 pin functions chapter 2 user?s manual u17566ee5v1um00 2.2.3 pin data input/output if a pin is in port mode, the registers for pin data input/output specify the input and output data. (1) pn - port register in port mode (pmcn.pmcnm=0), data is input from or output to an external device by writing or reading the pn register. for port groups with up to eight ports, this is an 8-bit register. for port groups with up to 16 ports, this is a 16-bit register. access this register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. address see ?port group configuration? on page 54 initial value 00 h or 0000 h . this register is cleared by any reset. note after reset, the ports are in input mode (pmn.pmnm = 1). the read input value is determined by the port pins. note the value written to register pn is retained until a new value is written to register pn. data is written to or read from the pn register as follows: 76543210 pn7 pn6 pn5 pn4 pn3 pn2 pn1 pn0 r/w r/w r/w r/w r/w r/w r/w r/w 1514131211109876543210 pn15 pn14 pn13 pn12 pn11 pn10 pn9 pn8 pn7 pn6 pn5 pn4 pn3 pn2 pn1 pn0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 2-9 pn register contents bit position bit name function 7 to 0 or 15 to 0 pn[7:0] or pn[15:0] data, see ta bl e 2 - 1 0 for details. table 2-10 writing/reading register pn function prc pm i/o write to pn and output contents of pn to pins x0o write to pn without affecting the pin status x1 i read from pn and thus read the pin status 01 i read from pn and disregard the pin status x0o 11 i
40 chapter 2 pin functions user?s manual u17566ee5v1um00 (2) prcn - port read control register in input mode (pmn.pmnm = 1), the 8-bit prcn register specifies whether the pin status or the contents of register pn are read (see also ta bl e 2 - 1 0 ). each prcn register contains only one control bit which defines the read source of all ports of the entire port group n. access this register can be read/written in 8-bit and 1-bit units. address see ?port group configuration? on page 54 initial value 00 h . this register is cleared by any reset. note if pmn.pmnm = 0, the contents of pn are read in any case - independent of prcn.prcnm. (3) pprn - port pin read register the 8-bit pprn register reflects the actual pin value, independent of the control registers set-up. access this register is read-only, in 8-bit and 1-bit units. 16-bit registers can also be read in 16-bit units. address see ?port group configuration? on page 54 initial value 00 h or 0000 h . this register is cleared by any reset. 76543210 xxxxxxxprcn0 r/w r/w r/w r/w r/w r/w r/w r/w table 2-11 prcn register contents bit position bit name function 0 prcn0 specifies which data are to be read in port group n: 0: pin status is read 1: contents of pn are read 76543210 pprn7 pprn6 pprn5 pprn4 pprn3 pprn2 pprn1 pprn0 rrrrrrrr table 2-12 pprn register contents bit position bit name function 7 to 0 pprn[7:0] actual pin value
41 pin functions chapter 2 user?s manual u17566ee5v1um00 2.2.4 configuration of electrical characteristics the registers for the configuration of electrical characteristics are briefly described in the following. for details refer to the data sheet. (1) pdscn - port drive strength control register the 8-bit pdscn register selects the output current limiting function for high- or low-drive strength. access this register can be read/written, in 8-bit and 1-bit units. address see ?port group configuration? on page 54 initial value 00 h . this register is cleared by any reset. for the detailed specification of "limit 1" and "limit 2" refer to the data sheet. (2) piccn - port input characteristic control register the 8-bit piccn register selects between schmitt trigger or non-schmitt trigger input characteristics. access this register can be read/written in 8-bit and 1-bit units. address see ?port group configuration? on page 54 initial value ff h . this register is cleared by any reset. 76543210 pdscn7 pdscn6 pdscn5 pdscn4 pdscn3 pdscn2 pdscn1 pdscn0 r/w r/w r/w r/w r/w r/w r/w r/w table 2-13 pdscn register contents bit position bit name function 7 to 0 pdscn[7:0] specifies output current limiting function: 0: limit 1. 1: limit 2. 76543210 piccn7 piccn6 piccn5 piccn4 p iccn3 piccn2 piccn1 piccn0 r/w r/w r/w r/w r/w r/w r/w r/w table 2-14 piccn register contents bit position bit name function 7 to 0 piccn[7:0] specifies trigger input characteristics: 0: non-schmitt trigger 1: schmitt trigger
42 chapter 2 pin functions user?s manual u17566ee5v1um00 (3) pilcn - port input level control register the pilcn register selects between different input characteristics for schmitt trigger (piccn.piccnm = 1) and non-schmitt trigger (piccn.piccnm = 0). for port groups with up to eight ports, this is an 8-bit register. for port groups with up to 16 ports, this is a 16-bit register. access this register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. address see ?port group configuration? on page 54 initial value 00 h this register is initialized by any reset. 76543210 pilcn7 pilcn6 pilcn5 pilcn4 pilcn3 pilcn2 pilcn1 pilcn0 r/w r/w r/w r/w r/w r/w r/w r/w 1514131211109876543210 pilcn1 5 pilcn1 4 pilcn1 3 pilcn1 2 pilcn1 1 pilcn1 0 pilcn9 pilcn8 pilcn7 pilcn6 pilcn5 pilcn4 pilcn3 pilcn2 pilcn1 pilcn0 rrrrrrrrrrrrrrrr table 2-15 pilcn register contents bit position bit name function 7 to 0 or 15 to 0 pilcn[7:0] or pilc[15:0] selects the input level: for schmitt trigger (piccn.piccnm = 1): 0: schmitt 1 1: schmitt 2 for non-schmitt trigger (piccn.piccnm = 0): 0: cmos1 1: cmos2
43 pin functions chapter 2 user?s manual u17566ee5v1um00 (4) podcn - port open drain control register the podcn register selects the output buffer function as push-pull or open- drain emulation. access this register can be read/written in 8-bit and 1-bit units. address see ?port group configuration? on page 54 initial value 00 h . this register is cleared by any reset. if open drain emulation is enabled the output function of concerned pin is automatically enabled as well, independently of the pmn.pmnm setting. caution depending on the capacitive load applied to an output pin pnm (pmnm = 0) in open-drain emulation (podcnm = 1) a change from low to high level may take a remarkable rise time. hence a read of the port pin status ? via the pprn register or ? pn register with prcn = 0 (pin status read) immediately after setting pnm to high level may still return low level at pnm. particular attention is needed when a read-modify-write instruction (set1, clr1, not1) is executed after setting pnm = 1 (with prcn0 = 0) to manipulate another port pin of the same port group n during the rise time of the pnm output. in this case the read of pnm may show 0 (though it should be 1) and the 0 is written back to pnm at the end of the read-modify-write instruction. consequently pnm may never reach high level at the output pin. 76543210 podcn7 podcn6 podcn5 podcn4 podcn3 podcn2 podcn1 podcn0 r/w r/w r/w r/w r/w r/w r/w r/w table 2-16 podcn register contents bit position bit name function 7 to 0 podcn[7:0] specifies the output buffer function: 0: push-pull 1: open drain emulation output mode
44 chapter 2 pin functions user?s manual u17566ee5v1um00 2.2.5 alternative input selection alternative input functions of csib0?csib2, uart0?uart1, i 2 c0, i 2 c1, intp6, intp7, tmp0?tmp3 and tmg0?tmg2 are provided on two pins each. thus you can select on which pin the alternative function should appear. for this purpose, four peripheral function select registers pfsrk (k = 0 to 3) are provided. note the selection of the alternative input function is done by a different circuit than the selection of the alternative output function. therefore, the registers for selecting the alternative input functions (pfsr) are not reflected in the block diagrams of the port types in chapter ?port types diagrams? on page 49 .
45 pin functions chapter 2 user?s manual u17566ee5v1um00 (1) pfsr0 - peripheral function select register the 8-bit pfsr0 register selects the alternative input paths for the peripheral functions csib0?2, i 2 c0, i 2 c1, intp6 and intp7. access this register can be read/written in 8-bit units. address ffff f720 h initial value 01 h . this register is initialized by any reset. 76543210 pfsr07 pfsr06 pfsr05 pfsr04 0 a a) this bit may be written, but write is ignored. pfsr02 pfsr01 pfsr00 r/w r/w r/w r/w r r/w r/w r/w table 2-17 pfsr0 register contents bit position bit name function 7 pfsr07 specifies the alternative input path for intp7: 0: intp7 is input from p50 (intp7_0) 1: intp7 is input from p84 (intp7_1) 6 pfsr06 specifies the alternative input path for intp6: 0: intp6 is input from p07 (intp6_0) 1: intp6 is input from p40 (intp6_1) 5 pfsr05 specifies the alternative input path for i 2 c1: 0: scl1 is input from p21 (scl1_0) sda1 is input from p20 (sda1_0) 1: scl1 is input from p31 (scl1_1) sda1 is input from p30 (sda1_1) 4 pfsr04 specifies the alternative input path for i 2 c0: 0: scl0 is input from p17 (scl0_0) sda0 is input from p16 (sda0_0) 1: scl0 is input from p64 (scl0_1) sda0 is input from p65 (sda0_1) 2 pfsr02 specifies the alternative input path for csib2: 0: sckb2 is input from p82 (sckb2_0) sib2 is input from p80 (sib2_0) 1: sckb2 is input from p96 (sckb2_1) sib2 is input from p94 (sib2_1) 1 pfsr01 specifies the alternative input path for csib1: 0: sckb1 is input from p45 (sckb1_0) sib1 is input from p43 (sib1_0) 1: sckb1 is input from p92 (sckb1_1) sib1 is input from p90 (sib1_1) 0 pfsr00 specifies the alternative input path for csib0: 0: sckb0 is input from p42 (sckb0_0) sib0 is input from p40 (sib0_0) 1: sckb0 is input from p107 (sckb0_1) sib0 is input from p105 (sib0_1)
46 chapter 2 pin functions user?s manual u17566ee5v1um00 (2) pfsr1 - peripheral function select register the 8-bit pfsr1 register selects the alternative input paths for the peripheral functions tmp0?3. access this register can be read/written in 8-bit units. address ffff f722 h initial value 01 h . this register is initialized by any reset. 76543210 pfsr17 pfsr16 pfsr15 pfsr14 pfsr13 pfsr12 pfsr11 pfsr10 r/w r/w r/w r/w r/w r/w r/w r/w table 2-18 pfsr1 register contents bit position bit name function 7 pfsr17 specifies the alternative input path for timer channel 1 of tmp3: 0: tip31 is input from p67 (tip31_0) 1: tip31 is input from p102 (tip31_1) 6 pfsr16 specifies the alternative input path for timer channel 0 of tmp3: 0: tip30 is input from p65 (tip30_0) 1: tip30 is input from p103 (tip30_1) 5 pfsr15 specifies the alternative input path for timer channel 1 of tmp2: 0: tip21 is input from p66 (tip21_0) 1: tip21 is input from p103 (tip21_1) 4 pfsr14 specifies the alternative input path for timer channel 0 of tmp2: 0: tip20 is input from p64 (tip20_0) 1: tip20 is input from p102 (tip20_1) 3 pfsr13 specifies the alternative input path for timer channel 1 of tmp1: 0: tip11 is input from p63 (tip11_0) 1: tip11 is input from p100 (tip11_1) 2 pfsr12 specifies the alternative input path for timer channel 0 of tmp1: 0: tip10 is input from p62 (tip10_0) 1: tip10 is input from p101 (tip10_1) 1 pfsr11 specifies the alternative input path for timer channel 1 of tmp0: 0: tip01 is input from p61 (tip01_0) 1: tip01 is input from p101 (tip01_1) 0 pfsr10 specifies the alternative input path for timer channel 0 of tmp0: 0: tip00 is input from p60 (tip00_0) 1: tip00 is input from p100 (tip00_1)
47 pin functions chapter 2 user?s manual u17566ee5v1um00 (3) pfsr2 - peripheral function select register the 8-bit pfsr2 register selects the alternative input paths for the peripheral functions tmg0 and tmg1. access this register can be read/written in 8-bit units. address ffff f724 h initial value 01 h . this register is initialized by any reset. 76543210 pfsr27 pfsr26 pfsr25 pfsr24 pfsr23 pfsr22 pfsr21 pfsr20 r/w r/w r/w r/w r/w r/w r/w r/w table 2-19 pfsr2 register contents bit position bit name function 7 pfsr27 specifies the alternative input path for timer channel 4 of tmg1: 0: tig14 is input from p27 (tig14_0) 1: tig14 is input from p137 (tig14_1) 6 pfsr26 specifies the alternative input path for timer channel 2 of tmg1: 0: tig13 is input from p26 (tig13_0) 1: tig13 is input from p136 (tig13_1) 5 pfsr25 specifies the alternative input path for timer channel 2 of tmg1: 0: tig12 is input from p25 (tig12_0) 1: tig12 is input from p135 (tig12_1) 4 pfsr24 specifies the alternative input path for timer channel 1 of tmg1: 0: tig11 is input from p24 (tig11_0) 1: tig11 is input from p134 (tig11_1) 3 pfsr23 specifies the alternative input path for timer channel 4 of tmg0: 0: tig04 is input from p23 (tig04_0) 1: tig04 is input from p133 (tig04_1) 2 pfsr22 specifies the alternative input path for timer channel 3 of tmg0: 0: tig03 is input from p22 (tig03_0) 1: tig03 is input from p132 (tig03_1) 1 pfsr21 specifies the alternative input path for timer channel 2 of tmg0: 0: tig02 is input from p21 (tig02_0) 1: tig02 is input from p131 (tig02_1) 0 pfsr20 specifies the alternative input path for timer channel 1 of tmg0: 0: tig01 is input from p20 (tig01_0) 1: tig01 is input from p130 (tig01_1)
48 chapter 2 pin functions user?s manual u17566ee5v1um00 (4) pfsr3 - peripheral function select register the 8-bit pfsr3 register selects the alternative input paths for the peripheral functions tmg2, uarta0 and uarta1. access this register can be read/written in 8-bit units. address ffff f726 h initial value 01 h . this register is initialized by any reset. 76543210 0 0 pfsr35 pfsr34 pfsr33 pfsr32 pfsr31 pfsr30 r a a) these bits may be written, but write is ignored. r a r/w r/w r/w r/w r/w r/w table 2-20 pfsr3 register contents bit position bit name function 5 pfsr35 specifies the alternative input path for uarta1: 0: rxda1 is input from p33 (rxda1_0) 1: rxda1 is input from p56 (rxda1_1) 4 pfsr34 specifies the alternative input path for uarta0: 0: rxda0 is input from p31 (rxda0_0) 1: rxda0 is input from p87 (rxda0_1) 3 pfsr33 specifies the alternative input path for timer channel 4 of tmg2: 0: tig24 is input from p37 (tig24_0) 1: tig24 is input from p63 (tig24_1) 2 pfsr32 specifies the alternative input path for timer channel 3 of tmg2: 0: tig23 is input from p36 (tig23_0) 1: tig23 is input from p67 (tig23_1) 1 pfsr31 specifies the alternative input path for timer channel 2 of tmg2: 0: tig22 is input from p35 (tig22_0) 1: tig22 is input from p66 (tig22_1) 0 pfsr30 specifies the alternative input path for timer channel 1 of tmg2: 0: tig21 is input from p34 (tig21_0) 1: tig21 is input from p61 (tig21_1)
49 pin functions chapter 2 user?s manual u17566ee5v1um00 2.3 port types diagrams the control circuits that evaluate the settings of the configuration registers are of different types. this chapter presents the block diagrams of all port types. (1) port type m figure 2-2 block diagram: port type m piccnm pmcnm pmnm pnm 0 1 1 0 1 0 0 1 alt1-out pfcnm alt2-out alt-in prcn0 podcnm pnm p rd pdscnm lcdbufen plcdcnm analog filter pilcnm ppr rd enable note 4 note 5 note 6 note 3 note 1 note 2 enable internal reset
50 chapter 2 pin functions user?s manual u17566ee5v1um00 note 1. the analog filter is provided only for alternative external interrupt ports p00?04, p06, p07, p40. the pd70f3424, pd70f3425, pd70f3426a, pd70f3427 provides analog filters additionally at p50 and p84. 2. bit plcdcn.plcdcnm is only provid ed with pd70f3421, pd70f3422 and pd70f3423 for pins with an alternative function as lcd controller/ driver output ports p20?27, p32?37, p43?45, p60?67, p80?83, p85?87, p90?97, p104?107. 3. the pfcn register is available only for port groups p0, p3, p5, p6, p13. 4. the pdscn register is not available for port groups 11, 12, 13 and 14. the bits pdsc3[3:2], pdsc8[7:6], pdsc10[7:4] are not available for pd70f3427. 5. the bits picc3[3:2], picc8[7:6], picc10[7:4] are not available for pd70f3427. 6. the bits pilc3[3:2], pilc8[7:6], pilc10[7:4] are not available for pd70f3427.
51 pin functions chapter 2 user?s manual u17566ee5v1um00 (2) port type q figure 2-3 block diagram: port type q note 1. the pdsc9 register is not available for pd70f3427. 2. the picc9 register is not available for pd70f3427. 3. the pilc9 register is not available for pd70f3427. piccnm pmcnm pmnm pnm 0 1 1 0 1 0 0 1 alt1-out pfcnm alt2-out internal reset prcn0 podcnm pnm p rd pdscnm pilcnm lcd bus i/f read ppr rd enable lcd bus i/f write enable note 1 note 2 note 3
52 chapter 2 pin functions user?s manual u17566ee5v1um00 (3) port type r this port type holds for pins that can be used for on-chip debugging with the n-wire interface. figure 2-4 block diagram: port type r note if ocdm.ocdm0 = 1, the corresponding pins are operating in on-chip debug mode. the pins are automatically set as input or output pins, respectively. setting of bits pmn.pmnm is not necessary. for more details refer to ?on-chip debug unit? on page 969 . piccnm pilcnm ocdm pmnm pnm 1 0 1 0 0 1 ddo ddi, dms, dck, drst prcn0 podcnm pnm p rd pdscnm pfcnm 1 0 pfc0.pdc05 internal reset enable ppr rd enable
53 pin functions chapter 2 user?s manual u17566ee5v1um00 (4) port type b this port type holds for pins that only work in input mode. pins of port type b are used for the corresponding alternative input function a/d converter input. at the same time, the pin status can also be read via the port register pn, so that the pin also works in port function. figure 2-5 block diagram: port type b a/d conversion of the level at pnm is independent of any register settings. for reading the pin status via the pn register pmcnm has to be set to 0. since the accuracy of an a/d conversion may degrade when pn is read during the sampling time of the a/d converter, it is recommended to disable the port pin read by pmcnm = 1 during a/d conversion. p rd pnm a in select adc input pmcnm pilcnm
54 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4 port group configuration this section provides an overview of the port groups ( ta bl e 2 - 2 1 , ta b l e 2 - 2 2 ) and of the pin functions ( table 2-23 on page 62 ). in table 2-73 on page 108 it is listed how the pin functions change if the microcontroller is reset or if it is in one of the standby modes. in the subsections, for every port group the settings of the configuration registers is listed. further, the addresses and initial values of the configuration registers are given. see ?port group 0? on page 69 to ?port group 13? on page 93 .
55 pin functions chapter 2 user?s manual u17566ee5v1um00 2.4.1 port group configuration lists following tables provide overviews of the functions available at each port pin: ? ta bl e 2 - 2 1 for pd70f3421, pd70f3422, pd70f3423 ? ta bl e 2 - 2 2 for pd70f3424, pd70f3425, pd70f3426a, pd70f3427 table 2-21 port group list for pd70f3421, pd70f3422, pd70f3423 (1/4) port group name port name alternative outputs alt1_out/alt2_out/ lcd_out alternative inputs port type 0 p00 ? intp0/nmi m p01 ? intp1 m p02 ? intp2 m p03 ? intp3 m p04 ? intp4 m p05 ? drst r p06 ? intp5 m p07 vcmpo0/vcmpo1 intp6 m 1 p16 sda0/ctxd2 sda0 m p17 scl0 scl0/crxd2 m 2 p20 sda1/tog01/seg0 tig01/sda1 m p21 scl1/tog02/seg1 tig02/scl1 m p22 tog03/seg2 tig03 m p23 tog04/seg3 tig04 m p24 tog11/seg4 tig11 m p25 tog12/seg5 tig12 m p26 tog13/seg6 tig13 m p27 tog14/seg7 tig14 m 3 p30 txda0/sda1 sda1 m p31 scl1 rxda0/scl1 m p32 txda1/seg31 ? m p33 seg29 rxda1 m p34 top01/tog21/seg8 tig21 m p35 top21/tog22/seg9 tig22 m p36 top31/tog23/seg10 tig23 m p37 top11/tog24/seg11 tig24 m 4 p40 ? sib0/intp6 m p41 sob0 ? m p42 sckb0 sckb0 m p43 seg22 sib1 m p44 sob1/seg21 ? m p45 sckb1/seg20 sckb1 m p46 ? crxd0 m p47 ctxd0 ? m
56 chapter 2 pin functions user?s manual u17566ee5v1um00 5 p50 fout/sgoa ? m p51 sgo ? m p52 ? ddi r p53 ddo ? r p54 ? dck r p55 ? dms r p56 ? rxda1/crxd1 m p57 txda1/ctxd1 ? m 6 p60 top00/seg12 tip00/tig20 m p61 top01/tog21/seg13 tip01/tig21 m p62 top10/seg14 tip10/tig25 m p63 top11/tog24/seg15 tip11/tig24 m p64 scl0/top20/seg16 tip20/scl0 m p65 sda0/top30/seg17 tip30/sda0 m p66 top21/tog22/seg18 tip21/tig22 m p67 top31/tog23/seg19 tip31/tig23 m 7 p70 ? ani0 b p71 ? ani1 b p72 ? ani2 b p73 ? ani3 b p74 ? ani4 b p75 ? ani5 b p76 ? ani6 b p77 ? ani7 b p78 ? ani8 b p79 ? ani9 b p710 ? ani10 b p711 ? ani11 b p712 ? ? b p713 ? ? b p714 ? ? b p715 ? ? b 8 p80 seg26 ? m p81 seg25 ? m p82 seg24 ? m p83 toy0/fout /seg23 ? m p84 toy0 ? m p85 fout/seg27 ? m p86 txda0/seg30 ? m p87 seg28 rxda0 m table 2-21 port group list for pd70f3421, pd70f3422, pd70f3423 (2/4) port group name port name alternative outputs alt1_out/alt2_out/ lcd_out alternative inputs port type
57 pin functions chapter 2 user?s manual u17566ee5v1um00 9 p90 dbd0/seg36 dbd0/sib1 q p91 dbd1/seg37/sob1 dbd1 q p92 dbd2/seg38/sckb1 dbd2/sckb1 q p93 dbd3/seg39 dbd3 q p94 dbd4/com0 dbd4 q p95 dbd5/com1 dbd5 q p96 dbd6/com2 dbd6 q p97 dbd7/com3 dbd7 q 10 p100 top00/top11 tip00/tip11 m p101 top01/top10 tip01/tip10 m p102 top20/top31 tip20/tip31 m p103 top21/top30 tip21/tip30 m p104 dbrd /seg35 ? m p105 dbwr /seg34 sib0 m p106 sob0/seg33 ? m p107 sckb0/seg32 sckb0 m 11 p110 sm11/tog21 ? m p111 sm12/tog22 ? m p112 sm13/tog23 ? m p113 sm14/tog24 ? m p114 sm21/sgo ? m p115 sm22/sgoa ? m p116 sm23 ? m p117 sm24 ? m note: port group 11 is equipped with high drive buffers for stepper motor control. 12 p120 sm51 ? m p121 sm52 ? m p122 sm53 ? m p123 sm54 ? m p124 sm61 ? m p125 sm62 ? m p126 sm63 ? m p127 sm64 ? m note: port group 12 is equipped with high drive buffers for stepper motor control. table 2-21 port group list for pd70f3421, pd70f3422, pd70f3423 (3/4) port group name port name alternative outputs alt1_out/alt2_out/ lcd_out alternative inputs port type
58 chapter 2 pin functions user?s manual u17566ee5v1um00 13 p130 sm31/tog01 tig01 m p131 sm32/tog02 tig02 m p132 sm33/tog03 tig03 m p133 sm34/tog04 tig04 m p134 sm41/tog11 tig11 m p135 sm42/tog12 tig12 m p136 sm43/tog13 tig13 m p137 sm44/tog14 tig14 m note: port group 13 is equipped with high drive buffers for stepper motor control. table 2-22 port group list for pd70f3424, pd70f3425, pd70f3426a, pd70f3427 (1/4) port group name port name alternative outputs alt1_out/alt2_out alternative inputs port type 0 p00 ? intp0/nmi m p01 ? intp1 m p02 ? intp2 m p03 ? intp3 m p04 ? intp4 m p05 ? drst r p06 ? intp5 m p07 vcmpo0/vcmpo1 intp6 m 1 p16 sda0/ctxd2 a sda0 m p17 scl0 scl0/crxd2 a m 2 p20 sda1/tog01 tig01/sda1 m p21 scl1/tog02 tig02/scl1 m p22 tog03 tig03 m p23 tog04 tig04 m p24 tog11 tig11 m p25 tog12 tig12 m p26 tog13 tig13 m p27 tog14 tig14 m 3 p30 txda0/sda1 sda1 m p31 scl1 rxda0/scl1 m p32 txda1/d18 b d18 b m p33 d19 b rxda1/d19 b m p34 top01/tog21 tig21 m p35 top21/tog22 tig22 m p36 top31/tog23 tig23 m p37 top11/tog24 tig24 m table 2-21 port group list for pd70f3421, pd70f3422, pd70f3423 (4/4) port group name port name alternative outputs alt1_out/alt2_out/ lcd_out alternative inputs port type
59 pin functions chapter 2 user?s manual u17566ee5v1um00 4 p40 ? sib0/intp6 m p41 sob0 ? m p42 sckb0 sckb0 m p43 ? sib1 m p44 sob1 ? m p45 sckb1 sckb1 m p46 ? crxd0 m p47 ctxd0 ? m 5 p50 fout/sgoa intp7 m p51 sgo ? m p52 ? ddi r p53 ddo ? r p54 ? dck r p55 ? dms r p56 ? rxda1/crxd1 m p57 txda1/ctxd1 ? m 6 p60 top00 tip00/tig20 m p61 top01/tog21 tip01/tig21 m p62 top10 tip10/tig25 m p63 top11/tog24 tip11/tig24 m p64 scl0/top20 tip20/scl0 m p65 sda0/top30 tip30/sda0 m p66 top21/tog22 tip21/tig22 m p67 top31/tog23 tip31/tig23 m 7 p70 ? ani0 b p71 ? ani1 b p72 ? ani2 b p73 ? ani3 b p74 ? ani4 b p75 ? ani5 b p76 ? ani6 b p77 ? ani7 b p78 ? ani8 b p79 ? ani9 b p710 ? ani10 b p711 ? ani11 b p712 ? ani12 b p713 ? ani13 b p714 ? ani14 b p715 ? ani15 b table 2-22 port group list for pd70f3424, pd70f3425, pd70f3426a, pd70f3427 (2/4) port group name port name alternative outputs alt1_out/alt2_out alternative inputs port type
60 chapter 2 pin functions user?s manual u17566ee5v1um00 8 p80 ? sib2 m p81 sob2 ? m p82 sckb2 sckb2 m p83 toy0/fout ?m p84 toy0 intp7 m p85 fout ? m p86 txda0/d16 b d16 b m p87 d17 b rxda0/d17 b m 9 p90 dbd0/d24 b dbd0/sib1/ d24 b q p91 dbd1/sob1/d25 b dbd1/d25 b q p92 dbd2/sckb1/d26 b dbd2/sckb1/ d26 b q p93 dbd3/d27 b dbd3/d27 b q p94 dbd4/d28 b dbd4/sib2/ d28 b q p95 dbd5/sob2/d29 b dbd5/d29 b q p96 dbd6/sckb2/d30 b dbd6/sckb2/ d30 b q p97 dbd7/d31 b dbd7/d31 b q 10 p100 top00/top11 tip00/tip11 m p101 top01/top10 tip01/tip10 m p102 top20/top31 tip20/tip31 m p103 top21/top30 tip21/tip30 m p104 dbrd /d20 b d20 b m p105 dbwr /d21 b sib0/d21 b m p106 sob0/d22 b d22 b m p107 sckb0/d23 b sckb0/d23 b m 11 p110 sm11/tog21 ? m p111 sm12/tog22 ? m p112 sm13/tog23 ? m p113 sm14/tog24 ? m p114 sm21/sgo ? m p115 sm22/sgoa ? m p116 sm23 ? m p117 sm24 ? m note: port group 11 is equipped with high drive buffers for stepper motor control. table 2-22 port group list for pd70f3424, pd70f3425, pd70f3426a, pd70f3427 (3/4) port group name port name alternative outputs alt1_out/alt2_out alternative inputs port type
61 pin functions chapter 2 user?s manual u17566ee5v1um00 12 p120 sm51 ? m p121 sm52 ? m p122 sm53 ? m p123 sm54 ? m p124 sm61 ? m p125 sm62 ? m p126 sm63 ? m p127 sm64 ? m note: port group 12 is equipped with high drive buffers for stepper motor control. 13 p130 sm31/tog01 tig01 m p131 sm32/tog02 tig02 m p132 sm33/tog03 tig03 m p133 sm34/tog04 tig04 m p134 sm41/tog11 tig11 m p135 sm42/tog12 tig12 m p136 sm43/tog13 tig13 m p137 sm44/tog14 tig14 m note: port group 13 is equipped with high drive buffers for stepper motor control. 14 b p140 bclk ? m p141 be2 ?m p142 be3 ?m mem-i/f b ?a[23:0] ? ?cs0 , cs1 , cs3 , cs4 ? ?wr ? ?rd ? ? be0 , be1 ? ?d[15:0] ? ?wait ? a) not available on pd70f3426a b) pd70f3427 only table 2-22 port group list for pd70f3424, pd70f3425, pd70f3426a, pd70f3427 (4/4) port group name port name alternative outputs alt1_out/alt2_out alternative inputs port type
62 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.2 alphabetic pin function list ta b l e 2 - 2 3 provides a list of all pin function names in alphabetic order. table 2-23 alphabetic pin functions list (1/6) pin name i/o pin function port pd70f3421, pd70f3422, pd70f3423 pd70f3424, pd70f3425 pd70f3426a pd70f3427 a0 to a23 o external memory interface address lines 0 to 23 ? no ports ani0 to ani11 i a/d converter input 0 to 11 p70 to p711 ani12 to ani15 i a/d converter input 12 to 15 ? p712 to p715 avdd ? adc supply voltage no ports avref ? adc reference voltage input no ports avss ? adc ground no ports be0 , be1 o external memory interface byte enable signals 0, 1 ? no ports be2 o external memory interface byte enable signal 2 ?p141 be3 o external memory interface byte enable signal 3 ?p142 bclk o external memory interface clock signal (pd70f3427 only) ?p140 bvdd50, bvdd51 ? i/o buffer supply voltage no ports bvss50, bvss51 ? i/o buffer supply ground no ports com0 to com3 o lcd common lines 0 to 3 p94 to p97 ? crxd0 i can0 receive data p46 crxd1 i can1 receive data p56 crxd2 i can2 receive data p17 ? p17 cs0 , cs1 , cs3 , cs4 o external memory interface chip select signals) ? no ports ctxd0 o can0 transmit data p47 ctxd1 o can1 transmit data p57 ctxd2 o can2 transmit data p16 ? p16 d0 to d15 i/o external memory interface data lines 0 to 15 ? no ports
63 pin functions chapter 2 user?s manual u17566ee5v1um00 d16 i/o external memory interface data lines 16 to 31 ?p86 d17 p87 d18 p32 d19 p33 d20 to d23 p104 to p107 d24 to d31 p90 to p97 dbd0 to dbd7 i/o lcd bus i/f data lines 0 to 7 p90 to p97 dbrd o lcd bus i/f read strobe p104 dbwr o lcd bus i/f write strobe p105 dck i n-wire interface clock p54 ddi i n-wire interface debug data input p52 ddo o n-wire interface debug data output p53 dms i n-wire interface debug mode select input p55 drst i n-wire debug interface reset p05 dvdd50 ? lcd bus i/f supply voltage no ports dvss50 ? lcd bus i/f supply ground no ports dvdd51 ? lcd bus i/f, d[31:16] ports supply voltage ? no ports dvss51 ? lcd bus i/f, d[31:16] ports supply ground ? no ports flmd0 i primary operating mode select pin no port flmd1 i secondary operating mode select pin p07 fout o frequency output p50, p85 fout o inverted frequency output p83 intp0 to intp4 i external interrupts 0 to 6 p00 to p04 intp5 i external interrupts 5 p06 intp6 i external interrupts 5 p07, p40 intp7 i external interrupt 7 ? p50, p84 mvdd50 - mvdd54 ? external memory interface supply voltage ? no ports mvss50 - mvss54 ? external memory interface supply ground ? no ports nmi i non-maskable interrupt p00 table 2-23 alphabetic pin functions list (2/6) pin name i/o pin function port pd70f3421, pd70f3422, pd70f3423 pd70f3424, pd70f3425 pd70f3426a pd70f3427
64 chapter 2 pin functions user?s manual u17566ee5v1um00 rd o external memory interface read strobe ? no ports regc0 to regc2 ? external capacitor connection no ports reset i reset input no ports rxda0 i uarta0 receive data p31, p87 rxda1 i uarta1 receive data p33, p56 sckb0 i/o clocked serial interface csib0 clock line p42, p107 sckb1 i/o clocked serial interface csib1 clock line p45, p92 sckb2 i/o clocked serial interface csib2 clock line ?p82, p96 scl0 i/o i 2 c0 clock line p17, p64 scl1 i/o i 2 c1 clock line p21, p31 sda0 i/o i 2 c0 data line p16, p65 sda1 i/o i 2 c1 data line p20, p30 seg0 to seg7 o lcd segment lines 0 to 39 p20 to p27 ? seg8 to seg11 o p34 to p37 seg12 to seg19 o p60 to p67 seg20 o p45 seg21 o p44 seg22 o p43 seg23 o p83 seg24 o p82 seg25 o p81 seg26 o p80 seg27 o p85 seg28 o p87 seg29 o p33 seg30 o p86 seg31 o p32 seg32 o p107 seg33 o p106 seg34 o p105 seg35 o p104 seg36 to seg39 o p90 to p93 sgo o sound generator output p51, p114 table 2-23 alphabetic pin functions list (3/6) pin name i/o pin function port pd70f3421, pd70f3422, pd70f3423 pd70f3424, pd70f3425 pd70f3426a pd70f3427
65 pin functions chapter 2 user?s manual u17566ee5v1um00 sgoa o sound generator amplitude pwm output p50, p115 sib0 i clocked serial interface csib0 data input p40, p105 sib1 i clocked serial interface csib1 data input p43, p90 sib2 i clocked serial interface csib2 data input ?p80, p94 sm11 o stepper motor 1 output sin + p110 sm12 o stepper motor 1 output sin ? p111 sm13 o stepper motor 1 output cos + p112 sm14 o stepper motor 1 output cos ? p113 sm21 o stepper motor 2 output sin + p114 sm22 o stepper motor 2 output sin ? p115 sm23 o stepper motor 2 output cos + p116 sm24 o stepper motor 2 output cos ? p117 sm31 o stepper motor 3 output sin + p130 sm32 o stepper motor 3 output sin ? p131 sm33 o stepper motor 3 output cos + p132 sm34 o stepper motor 3 output cos ? p133 sm41 o stepper motor 4 output sin + p134 sm42 o stepper motor 4 output sin ? p135 sm43 o stepper motor 4 output cos + p136 sm44 o stepper motor 4 output cos ? p137 sm51 o stepper motor 5 output sin + p120 sm52 o stepper motor 5 output sin ? p121 sm53 o stepper motor 5 output cos + p122 sm54 o stepper motor 5 output cos ? p123 sm61 o stepper motor 6 output sin + p124 sm62 o stepper motor 6 output sin ? p125 sm63 o stepper motor 6 output cos + p126 sm64 o stepper motor 6 output cos ? p127 smvdd50, smvdd51 ? stepper motor controller/ driver supply voltage no ports smvss50, smvss51 ? stepper motor controller/ driver ground no ports sob0 o clocked serial interface csib0 data output p41, p106 sob1 o clocked serial interface csib1 data output p44, p91 sob2 o clocked serial interface csib2 data output ?p81, p95 table 2-23 alphabetic pin functions list (4/6) pin name i/o pin function port pd70f3421, pd70f3422, pd70f3423 pd70f3424, pd70f3425 pd70f3426a pd70f3427
66 chapter 2 pin functions user?s manual u17566ee5v1um00 tig01 to tig04 i timer tmg0 channels 1 to 4 input p20 to p23, p130 to p133 tig11 to tig14 i timer tmg1 channels 1 to 4 input p24 to p27, p134 to p137 tig20 i timer tmg2 channels 0 to 5 input p60 tig21 i p34, p61 tig22 i p35, p66 tig23 i p36, p67 tig24 i p37, p63 tig25 i p62 tip00 i timer tmp0 channel 0 input p60, p100 tip01 i timer tmp0 channel 1 input p61, p101 tip10 i timer tmp1 channel 0 input p62, p101 tip11 i timer tmp1 channel 1 input p63, p100 tip20 i timer tmp2 channel 0 input p64, p102 tip21 i timer tmp2 channel 1 input p66, p103 tip30 i timer tmp3 channel 0 input p65, p103 tip31 i timer tmp3 channel 1 input p67, p102 tog01 to tog04 o timer tmg0 channels 1 to 4 output p20 to p23, p130 to p133 tog11 to tog14 o timer tmg1 channels 1 to 4 output p24 to p27, p134 to p137 tog21 o timer tmg2 channels 1 to 4 output p34, p61, p110 tog22 p35, p66, p111 tog23 p36, p67, p112 tog24 p37, p63, p113 top00 o timer tmp0 channel 0 output p60, p100 top01 o timer tmp0 channel 1 output p34, p61, p101 top10 o timer tmp1 channel 0 output p62, p101 top11 o timer tmp1 channel 1 output p37, p63, p100 top20 o timer tmp2 channel 0 output p64, p102 table 2-23 alphabetic pin functions list (5/6) pin name i/o pin function port pd70f3421, pd70f3422, pd70f3423 pd70f3424, pd70f3425 pd70f3426a pd70f3427
67 pin functions chapter 2 user?s manual u17566ee5v1um00 note alternative input functions of csib0?csib2, uart0?uart1, i 2 c0, i 2 c1, intp6, intp7, tmp0?tmp3 and tmg0?tmg2 are provided on two pins each. thus you can select on which pin the alternative function should appear. refer to ?alternative input selection? on page 44 . caution the wait pin must be connected to mv dd5n via a pull-up resistor in any case. top21 o timer tmp2 channel 1 output p35, p66, p103 top30 o timer tmp3 channel 0 output p65, p103 top31 o timer tmp3 channel 1 output p36, p67, p102 toy0 o timer tmy0 output p83, p84 txda0 o uarta0 transmit data p30, p86 txda1 o uarta1 transmit data p32, p57 vcmp0 i voltage comparator 0 input no ports vcmp1 i voltage comparator 1 input no ports vcmpo0 o output state of internal voltage comparator 0 p07 vcmpo1 o output state of internal voltage comparator 1 p07 vdd50 to vdd52 ? core supply voltage no ports vss50 to vss52 ? core supply ground no ports wait i external memory interface data wait request ? no ports wr o external memory interface write strobe ? no ports x1, x2 ? main oscillator terminals no ports xt1, xt2 ? sub-oscillator terminals no ports table 2-23 alphabetic pin functions list (6/6) pin name i/o pin function port pd70f3421, pd70f3422, pd70f3423 pd70f3424, pd70f3425 pd70f3426a pd70f3427
68 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.3 external memory interface of pd70f3427 the pd70f3427 is equipped with an external memory interface. the data bus width can be chosen between 16-bit d[15:0] and 32-bit d[31:0]. the signals of the external memory interface are partly shared with ports respectively alternative functions and are controlled by different means, as listed in ta b l e 2 - 2 4 . the upper data bus lines d[31:16] are made available by setting pmc.pmc143 = 1. thus this bit changes the interface from 16- to 32-bit mode. all other bus interface signals are available via group 14 (also usable as 3-bit i/ o port) and the permanent mem-i/f group. table 2-24 external memory interface pin control port ext. memory i/f signal mode control group name port/alternative ext. memory i/f 3 p32 d18 pmc.pmc143 = 0 pmc.pmc143 = 1 p33 d19 8p86 d16 p87 d17 9p90 d24 p91 d25 p92 d26 p93 d27 p94 d28 p95 d29 p96 d30 p97 d31 10 p104 d20 p105 d21 p106 d22 p107 d23 14 p140 bclk pmc.pmc140 = 0 pmc.pmc140 = 1 p141 be2 pmc.pmc141 = 0 pmc.pmc141 = 1 p142 be3 pmc.pmc142 = 0 pmc.pmc142 = 1 mem-i/f ? a[23:0] ? permanent d[15:0] wr cs0 , cs1 , cs3 , cs4 rd wait be0 , be1
69 pin functions chapter 2 user?s manual u17566ee5v1um00 2.4.4 port group 0 ? port group 0 is an 8-bit port group. in alternative mode, it comprises pins for the following functions: ? external interrupt (intp0 to intp6) ? non-maskable interrupt (nmi) ? n-wire debug interface reset (drst ) ? output state of internal voltage comparators 0 and 1 (vcmpo0, vcmpo1) port group 0 includes the following pins: note 1. the alternative input function of intp6 is provided on two pins. thus you can select on which pin the alternative function should appear. refer to ?alternative input selection? on page 44 . 2. the setting of bit ocdm.ocdm0 applies only to pins of port type r. 3. for configuring p00 as nmi and/or intp0 refer also to ?edge and level detection configuration? on page 257 . table 2-25 port group 0: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) on-chip debug mode (ocdm0 = 1) output mode (pmnm = 0) input mode (pmnm = 1) pfcnm = 0 alt1-out pfcnm = 1 alt2_out p00 (i/o) - intp0/nmi ? p00 (i) m p01 (i/o) - intp1 ? p01 (i) m p02 (i/o) ? intp2 ? p02 (i) m p03 (i/o) ? intp3 ? p03 (i) m p04 (i/o) ? intp4 ? p04 (i) m p05 (i/o) ? ? drst (i) p05 or drst (i) a r p06 (i/o) ? intp5 ? p06 (i) m p07 (i/o) vcmpo0 vcmpo1 intp6 ? p07 (i) m a) the pin function after reset depends on the reset source, that means on bit ocdm.ocdm0. refer to ?ocdm - on-chip debug mode register? on page 38 and to the ?on-chip debug unit? on page 969 .
70 chapter 2 pin functions user?s manual u17566ee5v1um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-26 port group 0: configuration registers register address initial value used bits pm0 ffff f420 h ff h pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pmc0 ffff f440 h 00 h pmc07 pmc06 x pmc04 pmc03 pmc02 pmc01 pmc00 pfc0 ffff f460 h 20 h pfc07 x pdc05 a a) note that pdc05 is used to connect/disconnect the internal pull-down resistor at pin p05/drst . xxxxx ocdm ffff f9fc h 00 h / 01 h b b) depends on the reset source (refer to ?ocdm - on-chip debug mode register? on page 38 and to ?on-chip debug unit? on page 969 . 0000000ocdm0 p0 ffff f400 h 00 h p07 p06 p05 p04 p03 p02 p01 p00 prc0 ffff f3e0 h 00 h xxxxxxxprc00 c c) the setting of prc00 is valid for the entire port group. ppr0 ffff f3c0 h 00 h ppr07 ppr06 ppr05 ppr04 ppr03 ppr02 ppr01 ppr00 pdsc0 ffff f300 h 00 h pdsc07 pdsc06 pdsc05 pdsc04 pdsc03 pdsc02 pdsc01 pdsc00 picc0 ffff f380 h ff h picc07 picc06 picc05 picc04 picc03 picc02 picc01 picc00 pilc0 ffff f3a0 h 00 h pilc07 pilc06 pilc05 pilc04 pilc03 pilc02 pilc01 pilc00 podc0 ffff f360 h 00 h podc07 podc06 podc05 podc04 podc03 podc02 podc01 podc00
71 pin functions chapter 2 user?s manual u17566ee5v1um00 2.4.5 port group 1 port group 1 is a 2-bit port group. in alternative mode, it comprises pins for the following functions: ?i 2 c0 data/clock line (sda0/scl0) port group 1 includes the following pins: note alternative input functions sda0 and scl0 are provided on two pins each. thus you can select on which pin the alternative function should appear. if alternative functions sda0/scl0 are used at p16/17, make sure to set also pfsr0.pfsr04 = 0. refer to ?alternative input selection? on page 44 . access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-27 port group 1: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) output mode (pmnm = 0) input mode (pmnm = 1) pfcnm = 0 alt1-out pfcnm = 1 alt2-out p16 (i/o) sda0 a ctxd2 b sda0 p16 (i) m p17 (i/o) scl0 a scl0/crxd2 b p17 (i) m a) xin i 2 c function mode open drain emulation has to be enabled (podc1.podc16 = 1 and podc1.podc17 = 1). thus output function is enabled automatically, although pmnm = 1. b) not available on pd70f3426a table 2-28 port group 1: configuration registers register address initial value used bits pm1 ffff f422 h ff h pm17pm16xxxxxx pmc1 ffff f442 h 00 h pmc17pmc16xxxxxx pfc1 a a) not available on pd70f3426a ffff f462 h 00 h x pfc16xxxxxx p1 ffff f402 h 00 h p17p16xxxxxx prc1 ffff f3e2 h 00 h x x xxxxxprc10 b b) the setting of prc10 is valid for the entire port group. ppr1 ffff f3c2 h 00 h ppr17ppr16xxxxxx pdsc1 ffff f302 h 00 h pdsc17 pdsc16 x x x x x x picc1 ffff f382 h ff h picc17 picc16 x x x x x x pilc1 ffff f3a2 h 00 h pilc17pilc16xxxxxx podc1 ffff f362 h 00 h podc17podc16xxxxxx
72 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.6 port group 2 port group 2 is an 8-bit port group. in alternative mode, it comprises pins for the following functions: ? timer tmg0 to tmg1 channels (tig01 to tig04, tog01 to tog04, tig11 to tig14, tog11 to tog14) ?i 2 c1 data/clock line (sda1, scl1) ? lcd controller segment signal output (seg0 to seg7) (pd70f3421, pd70f3422, pd70f3423 only) port group 2 includes the following pins: note 1. for pins that support only one alternative output mode, the pfcnm bit is not available. 2. alternative input functions of i 2 c1 (sda1, scl1) and of tmg0?tmg1 are provided on two pins each. thus you can select on which pin the alternative function should appear. if alternative functions sda1/scl1 are used at p20/21 make sure to set also pfsr0.pfsr05 = 0. refer to ?alternative input selection? on page 44 . table 2-29 port group 2: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) lcd mode (plcdcnm = 1) a output mode (pmnm = 0) input mode (pmnm = 1) pfcnm = 0 alt1-out pfcnm = 1 alt2-out p20 (i/o) sda1 b tog01 tig01/sda1 seg0 a p20 (i) m p21 (i/o) scl1 b tog02 tig02/scl1 seg1 a p21 (i) m p22 (i/o) tog03 tig03 seg2 a p22 (i) m p23 (i/o) tog04 tig04 seg3 a p23 (i) m p24 (i/o) tog11 tig11 seg4 a p24 (i) m p25 (i/o) tog12 tig12 seg5 a p25 (i) m p26 (i/o) tog13 tig13 seg6 a p26 (i) m p27 (i/o) tog14 tig14 seg7 a p27 (i) m a) pd70f3421, pd70f3422, pd70f3423 only b) in i 2 c function mode open drain emulation has to be enabled (podc2.podc20 = 1 and podc2.podc21 = 1). thus output function is enabled automatically, although pmnm = 1.
73 pin functions chapter 2 user?s manual u17566ee5v1um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-30 port group 2: configuration registers register address initial value used bits pm2 ffff f424 h ff h pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pmc2 ffff f444 h 00 h pmc27 pmc26 pmc25 pmc24 pmc23 pmc22 pmc21 pmc20 pfc2 ffff f464 h 00 h xxxxxxpfc21pfc20 plcdc2 a a) pd70f3421, pd70f3422, pd70f3423 only ffff f344 h 00 h plcdc27 plcdc26 plcdc25 plcdc24 plcdc23 plcdc22 plcdc21 plcdc20 p2 ffff f404 h 00 h p27 p26 p25 p24 p23 p22 p21 p20 prc2 ffff f3e4 h 00 h xxxxxxxprc20 b b) the setting of prc20 is valid for the entire port group. ppr2 ffff f3c4 h 00 h ppr27 ppr26 ppr25 ppr24 ppr23 ppr22 ppr21 ppr20 pdsc2 ffff f304 h 00 h pdsc27 pdsc26 pdsc25 pdsc24 pdsc23 pdsc22 pdsc21 pdsc20 picc2 ffff f384 h ff h picc27 picc26 picc25 picc24 p icc23 picc22 picc21 picc20 pilc2 ffff f3a4 h 00 h pilc27 pilc26 pilc25 pilc24 pilc23 pilc22 pilc21 pilc20 podc2 ffff f364 h 00 h podc27 podc26 podc25 podc24 podc23 podc22 podc21 podc20
74 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.7 port group 3 port group 3 is an 8-bit port group. in alternative mode, it comprises pins for the following functions: ? uarta0 transmit/receive data (txda0, rxda0) ? uarta1 transmit/receive data (txda1, rxda1) ?i 2 c1 data/clock line (sda1, scl1) ? lcd controller segment signal output (seg8 to seg11, seg29, seg31) (pd70f3421, pd70f3422, pd70f3423 only) ? timer tmg2 channels (tig21 to tig24, tog21 to tog24) ? timer tmp0 to tmp3 channels (top01 to top31) ? external memory interface data lines d[19:18] (pd70f3427 only) port group 3 includes the following pins x note 1. for pins that support only one alternative output mode, the pfcnm bit is not available. 2. alternative input functions of i 2 c1 (sda1, scl1), tmp0?tmp3, tmg2 and uarta0?uarta1 are provided on two pins each. thus you can select on which pin the alternative function should appear. if alternative functions sda1/scl1 are used at p30/31 make sure to set also pfsr0.pfsr05 = 1. refer to ?alternative input selection? on page 44 . table 2-31 port group 3: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm =0) alternative mode (pmcnm = 1) lcd mode (plcdcnm = 1) a external memory interface mode (pmc143 =1) b output mode (pmnm = 0) input mode (pmnm = 1) pfcnm = 0 alt1-out pfcnm = 1 alt2-out p30 (i/o) txda0 sda1 c sda1 ? port/alternative mode p30 (i) m p31 (i/o) scl1 c rxda0/scl1 ? port/alternative mode p31 (i) m p32 (i/o) txda1 ? seg31 a d18 b p32 (i) m p33 (i/o) ? rxda1 seg29 a d19 b p33 (i) m p34 (i/o) top01 tog21 tig21 seg8 a port/alternative mode p34 (i) m p35 (i/o) top21 tog22 tig22 seg9 a port/alternative mode p35 (i) m p36 (i/o) top31 tog23 tig23 seg10 a port/alternative mode p36 (i) m p37 (i/o) top11 tog24 tig24 seg11 a port/alternative mode p37 (i) m a) pd70f3421, pd70f3422, pd70f3423 only b) pd70f3427 only c) in i 2 c function mode open drain emulation has to be enabled (podc3.podc30 = 1 and podc3.podc31 = 1). thus output function is enabled automatically, although pmnm = 1.
75 pin functions chapter 2 user?s manual u17566ee5v1um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-32 port group 3: configuration registers register address initial value used bits pm3 ffff f426 h ff h pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pmc3 ffff f446 h 00 h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 pfc3 ffff f466 h 00 h pfc37 pfc36 pfc35 pfc34 x x x pfc30 plcdc3 a a) pd70f3421, pd70f3422, pd70f3423 only ffff f346 h 00 h plcdc37 plcdc36 plcdc35 plcdc34 plcdc33 plcdc32 xx p3 ffff f406 h 00 h p37p36p35p34p33p32p31p30 prc3 ffff f3e6 h 00 h xxxxxxxprc30 b b) the setting of prc30 is valid for the entire port group. ppr3 ffff f3c6 h 00 h ppr37 ppr36 ppr35 ppr34 ppr33 ppr32 ppr31 ppr30 pdsc3 ffff f306 h 00 h pdsc37 pdsc36 pdsc35 pdsc34 pdsc33 c c) not available for pd70f3427 pdsc32 c pdsc31 pdsc30 picc3 ffff f386 h ff h picc37 picc36 picc35 picc34 picc33 c picc32 c picc31 picc30 pilc3 ffff f3a6 h 00 h pilc37 pilc36 pilc35 pilc34 pilc33 c pilc32 c pilc31 pilc30 podc3 ffff f366 h 00 h podc37 podc36 podc35 podc34 podc33 podc32 podc31 podc30
76 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.8 port group 4 port group 4 is an 8-bit port group. in alternative mode, it comprises pins for the following functions: ? clocked serial interface csib0 data/clock line (sib0, sob0, sckb0) ? clocked serial interface csib1 data/clock line (sib1, sob1, sckb1) ? external interrupt (intp6) ? lcd controller segment signal output (seg20 to seg22) (pd70f3421, pd70f3422, pd70f3423 ? can0 transmit/receive data (ctxd0, crxd0) port group 4 includes the following pins: note alternative input functions of intp6, csib0, and csib1 are provided on two pins each. thus you can select on which pin the alternative function should appear. refer to ?alternative input selection? on page 44 . table 2-33 port group 4: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) lcd mode (plcdcnm = 1) a output mode (pmnm = 0) input mode (pmnm = 1) p40 (i/o) ? intp6/sib0 ? p40 (i) m p41 (i/o) sob0 ? ? p41 (i) m p42 (i/o) sckb0 sckb0 ? p42 (i) m p43 (i/o) ? sib1 seg22 a p43 (i) m p44 (i/o) sob1 ? seg21 a p44 (i) m p45 (i/o) sckb1 sckb1 seg20 a p45 (i) m p46 (i/o) ? crxd0 ? p46 (i) m p47 (i/o) ctxd0 ? ? p47 (i) m a) pd70f3421, pd70f3422, pd70f3423 only
77 pin functions chapter 2 user?s manual u17566ee5v1um00 note it is recommended to configure the ports used for can data transmit ctxdn to its highest drive strength to limit2 by pdscn.pdscnm = 1 for can baud rates above 200 kbit/sec. access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-34 port group 4: configuration registers register address initial value used bits pm4 ffff f428 h ff h pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 pmc4 ffff f448 h 00 h pmc47 pmc46 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 plcdc4 a a) pd70f3421, pd70f3422, pd70f3423 only ffff f348 h 00 h xx plcdc45 plcdc44 plcdc43 xxx p4 ffff f408 h 00 h p47 p46 p45 p44 p43 p42 p41 p40 prc4 ffff f3e8 h 00 h xxxxxxxprc40 b b) the setting of prc40 is valid for the entire port group. ppr4 ffff f3c8 h 00 h ppr47 ppr46 ppr45 ppr44 ppr43 ppr42 ppr41 ppr40 pdsc4 ffff f308 h 00 h pdsc47 pdsc46 pdsc45 pdsc44 pdsc43 pdsc42 pdsc41 pdsc40 picc4 ffff f388 h ff h picc47 picc46 picc45 picc44 picc43 picc42 picc41 picc40 pilc4 ffff f3a8 h 00 h pilc47 pilc46 pilc45 pilc44 pilc43 pilc42 pilc41 pilc40 podc4 ffff f368 h 00 h podc47 podc46 podc45 podc44 podc43 podc42 podc41 podc40
78 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.9 port group 5 port group 5 is an 8-bit port group. in alternative mode, it comprises pins for the following functions: ? external interrupt (intp7) (pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only) ? sound generator outputs (sgo, sgoa) ? frequency output (fout) ? n-wire interface signals (ddi, ddo, dck, dms) ? can1 transmit/receive data (ctxd1, crxd1) ? uarta1 transmit/receive data (txda1, rxda1) port group 5 includes the following pins: note 1. for pins that support only one alternative output mode, the pfcnm bit is not available. 2. the setting of bit ocdm.ocdm0 applies only to pins of port type r. 3. alternative input functions of uarta1 and intp7 are provided on two pins each. thus you can select on which pin the alternative function should appear. refer to ?alternative input selection? on page 44 . table 2-35 port group 5: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) on-chip debug mode (ocdm0 = 1) output mode (pmnm = 0) input mode (pmnm = 1) pfcnm = 0 alt1-out pfcnm = 1 alt2-out p50 (i/o) fout sgoa intp7 a ?p50 (i)m p51 (i/o) sgo ? ? p51 (i) m p52 (i/o) ? ? ddi (i) p52 or ddi (i) b r p53 (i/o) ? ? ddo (o) p53 (i) or ddo (o) b r p54 (i/o) ? ? dck (i) p54 or dck (i) b r p55 (i/o) ? ? dms(i) p55 or dms(i) b r p56 (i/o) ? crxd1 /rxda1 ?p56 (i) m p57 (i/o) txda1 ctxd1 ? ? p57 (i) m a) pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only b) the pin function after reset depends on the reset source, that means on bit ocdm.ocdm0. refer to ?ocdm - on-chip debug mode register? on page 38 and to the ?on-chip debug unit? on page 969 .
79 pin functions chapter 2 user?s manual u17566ee5v1um00 note it is recommended to configure the ports used for can data transmit ctxdn to its highest drive strength to limit2 by pdscn.pdscnm = 1 for can baud rates above 200 kbit/sec. access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-36 port group 5: configuration registers register address initial value used bits pm5 ffff f42a h ff h pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 pmc5 ffff f44a h 00 h pmc57pmc56xxxxpmc51pmc50 pfc5 ffff f46a h 00 h pfc57xxxxxxpfc50 ocdm ffff f9fc h 00 h /01 h 0000000ocdm0 p5 ffff f40a h 00 h p57p56p55p54p53p52p51p50 prc5 ffff f3ea h 00 h xxxxxxxprc50 a a) the setting of prc50 is valid for the entire port group. ppr5 ffff f3ca h 00 h ppr57 ppr56 ppr55 ppr54 ppr53 ppr52 ppr51 ppr50 pdsc5 ffff f30a h 00 h pdsc57 pdsc56 pdsc55 pdsc54 pdsc53 pdsc52 pdsc51 pdsc50 picc5 ffff f38a h ff h picc57 picc56 picc55 picc54 p icc53 picc52 picc51 picc50 pilc5 ffff f3aa h 00 h pilc57 pilc56 pilc55 pilc54 pilc53 pilc52 pilc51 pilc50 podc5 ffff f36a h 00 h podc57 podc56 podc55 podc54 podc53 podc52 podc51 podc50
80 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.10 port group 6 port group 6 is an 8-bit port group. in alternative mode, it comprises pins for the following functions: ? timer tmp0 to tmp3 channels (tip00 to tip31, top00 to top31) ? timer tmg2 channels (tig20 to tig25, tog21 to tog24) ? lcd controller segment signal output (seg12 to seg19) (pd70f3421, pd70f3422, pd70f3423 only) ?i 2 c0 data/clock line (sda0, scl0) port group 6 includes the following pins: note 1. for pins that support only one alternative output mode, the pfcnm bit is not available. 2. alternative input functions of i 2 c0 (sda0, scl0), tmp0?tmp3 and tmg2 are provided on two pins each. thus you can select on which pin the alternative function should appear. if alternative functions sda0/scl0 are used at p64/65 make sure to set also pfsr0.pfsr04 = 1. refer to ?alternative input selection? on page 44 . table 2-37 port group 6: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) lcd mode (plcdcnm = 1) a output mode (pmnm = 0) input mode (pmnm = 1) pfcnm = 0 alt1-out pfcnm = 1 alt2-out p60 (i/o) top00 tip00/tig20 seg12 a p60 (i) m p61 (i/o) top01 tog21 tip01/tig21 seg13 a p61 (i) m p62 (i/o) top10 tip10/tig25 seg14 a p62 (i) m p63 (i/o) top11 tog24 tip11/tig24 seg15 a p63 (i) m p64 (i/o) scl0 b top20 scl0/tip20 seg16 a p64 (i) m p65 (i/o) sda0 b top30 sda0/tip30 seg17 a p65 (i) m p66 (i/o) top21 tog22 tip21/tig22 seg18 a p66 (i) m p67 (i/o) top31 tog23 tip31/tig23 seg19 a p67 (i) m a) pd70f3421, pd70f3422, pd70f3423 only b) in i 2 c function mode open drain emulation has to be enabled (podc6.podc64 = 1 and podc6.podc65 = 1). thus output function is enabled automatically, although pmnm = 1.
81 pin functions chapter 2 user?s manual u17566ee5v1um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-38 port group 6: configuration registers register address initial value used bits pm6 ffff f42c h ff h pm67 pm66 pm65 pm64 pm63 pm62 pm61 pm60 pmc6 ffff f44c h 00 h pmc67 pmc66 pmc65 pmc64 pmc63 pmc62 pmc61 pmc60 pfc6 ffff f46c h 00 h pfc67 pfc66 pfc65 pfc64 pfc63 x pfc61 x plcdc6 a a) pd70f3421, pd70f3422, pd70f3423, only ffff f34c h 00 h plcdc67 plcdc66 plcdc65 plcdc64 plcdc63 plcdc62 plcdc61 plcdc60 p6 ffff f40c h 00 h p67 p66 p65 p64 p63 p62 p61 p60 prc6 ffff f3ec h 00 h xxxxxxxprc60 b b) the setting of prc60 is valid for the entire port group. ppr6 ffff f3cc h 00 h ppr67 ppr66 ppr65 ppr64 ppr63 ppr62 ppr61 ppr60 pdsc6 ffff f30c h 00 h pdsc67 pdsc66 pdsc65 pdsc64 pdsc63 pdsc62 pdsc61 pdsc60 picc6 ffff f38c h ff h picc67 picc66 picc65 picc64 picc63 picc62 picc61 picc60 pilc6 ffff f3ac h 00 h pilc67 pilc66 pilc65 pilc64 pilc63 pilc62 pilc61 pilc60 podc6 ffff f36c h 00 h podc67 podc66 podc65 podc64 podc63 podc62 podc61 podc60
82 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.11 port group 7 port group 7 is a 16-bit port group. it includes pins for the a/d converter input. the pins of this port group only work in input mode (port type b). they are used for their alternative input function a/d converter input. at the same time, the pin status can also be read via the port register pn, so that the pin also works in port mode. port group 7 includes the following pins: note all pins of port group 7 always function in alternative input mode, i.e. a/d conversion of the level at p7m is independent of any register settings. for reading the pin status via the p7 register pmc7m has to be set to 0. since the accuracy of an a/d conversion may degrade when p7 is read during the sampling time of the a/d converter, it is recommended to disable the port pin read by pmc7m = 1 during a/d conversion. table 2-39 port group 7: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative input mode (pmcnm = 1) p70 (i) ani0 p70 (i) b p71 (i) ani1 p71 (i) b p72 (i) ani2 p72 (i) b p73 (i) ani3 p73 (i) b p74 (i) ani4 p74 (i) b p75 (i) ani5 p75 (i) b p76 (i) ani6 p76 (i) b p77 (i) ani7 p77 (i) b p78 (i) ani8 p78 (i) b p79 (i) ani9 p79 (i) b p710 (i) ani10 p710 (i) b p711 (i) ani11 p711 (i) b p712 (i) ani12 a p712 (i) b p713 (i) ani13 a p713 (i) b p714 (i) ani14 a p714 (i) b p715 (i) ani15 a p715 (i) b a) pd70f3424 , pd70f3425, pd70f3426a, pd70f3427 only
83 pin functions chapter 2 user?s manual u17566ee5v1um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. all 16-bit registers can be accessed in 16-bit units. table 2-40 port group 7: configuration registers register address initial value used bits pmc7l ffff f44e h 00 h pmc77 pmc76 pmc75 pmc74 pmc73 pmc72 pmc71 pmc70 pmc7h ffff f44f h 00 h pmc715 a a) pmc715 to pmc712 are available for pd70f3424 , pd70f3425, pd70f3426a, pd70f3427 only. pmc714 a pmc713 a pmc712 a pmc711 pmc710 pmc79 pmc78 pmc7 (16 bit) ffff f44e h 0000 h pmc715 to pmc78 (pmc7h) a pmc77 to pmc70 (pmc7l) p7l ffff f40e h 00 h p77 p76 p75 p74 p73 p72 p71 p70 p7h ffff f40f h 00 h p715 p714 p713 p712 p711 p710 p79 p78 p7 (16 bit) ffff f04e h 0000 h p715 to pmc78 (p7h) p77 to p70 (p7l) pilc7l ffff f3ae h 00 h pilc77 pilc76 pilc75 pilc74 pilc73 pilc72 pilc71 pilc70 pilc7h ffff f3af h 00 h pilc715 pilc714 pilc713 pilc712 pilc711 pilc710 pilc79 pilc78 pilc7 (16 bit) ffff f44e h 0000 h pilc715 to pilc78 (pilc7h) pilc77 to pilc70 (pilc7l)
84 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.12 port group 8 port group 8 is an 8-bit port group. in alternative mode, it comprises pins for the following functions: ? clocked serial interface csib2 data/clock line (sib2, sob2, sckb2) (pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only) ? lcd controller segment signal output (seg23 to seg28, seg30) (pd70f3421, pd70f3422, pd70f3423 only) ? timer tmy0 output (toy0) ? frequency output (fout) ? inverted frequency output (fout ) ? external interrupt (intp7) (pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only) ? uarta0 transmit/receive data (txda0, rxda0) ? external memory interface data lines d[17:16] (pd70f3427 only) port group 8 includes the following pins: note 1. for pins that support only one alternative output mode, the pfcnm bit is not available. 2. alternative input functions of csib2, uart0, and intp7 are provided on two pins each. thus you can select on which pin the alternative function should appear. refer to ?alternative input selection? on page 44 . table 2-41 port group 8: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) lcd mode (plcdcnm = 1) a external memory interface mode (pmc143 =1) b output mode (pmnm = 0) input mode (pmnm = 1) pfcnm = 0 alt1-out pfcnm = 1 alt2-out p80 (i/o) ? sib2 c seg26 a port/alternative mode p80 (i) m p81 (i/o) sob2 c ? seg25 a port/alternative mode p81 (i) m p82 (i/o) sckb2 c sckb2 c seg24 a port/alternative mode p82 (i) m p83 (i/o) toy0 fout ? seg23 a port/alternative mode p83 (i) m p84 (i/o) toy0 intp7 c ? port/alternative mode p84 (i) m p85 (i/o) fout ? seg27 a port/alternative mode p85 (i) m p86 (i/o) txda0 ? seg30 a d16 b p86 (i) m p87 (i/o) ? rxda0 seg28 a d17 b p87 (i) m a) pd70f3421, pd70f3422, pd70f3423 only b) pd70f3427 only c) pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only
85 pin functions chapter 2 user?s manual u17566ee5v1um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-42 port group 8: configuration registers register address initial value used bits pm8 ffff f430 h ff h pm87 pm86 pm85 pm84 pm83 pm82 pm81 pm80 pmc8 ffff f450 h 00 h pmc87 pmc86 pmc85 pmc84 pmc83 pmc82 pmc81 pmc80 pfc8 ffff f470 h 00 h xxxxpfc83xxx plcdc8 a a) pd70f3421, pd70f3422, pd70f3423 only ffff f350 h 00 h plcdc87 plcdc86 plcdc85 x plcdc83 plcdc82 plcdc81 plcdc80 p8 ffff f410 h 00 h p87 p86 p85 p84 p83 p82 p81 p80 prc8 ffff f3f0 h 00 h xxxxxxxprc80 b b) the setting of prc80 is valid for the entire port group. ppr8 ffff f3d0 h 00 h ppr87 ppr86 ppr85 ppr84 ppr83 ppr82 ppr81 ppr80 pdsc8 ffff f310 h 00 h pdsc87 c c) not available for pd70f3427 pdsc86 c pdsc85 pdsc84 pdsc83 pdsc82 pdsc81 pdsc80 picc8 ffff f390 h ff h picc87 c picc86 c picc85 picc84 picc83 picc82 picc81 picc80 pilc8 ffff f3b0 h 00 h pilc87 c pilc86 c pilc85 pilc84 pilc83 pilc82 pilc81 pilc80 podc8 ffff f370 h 00 h podc87 podc86 podc85 podc84 podc83 podc82 podc81 podc80
86 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.13 port group 9 port group 9 is an 8-bit port group. in alternative mode, it comprises pins for the following functions: ? lcd bus interface data lines (dbd0 to dbd7) (pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only) ? clocked serial interface csib1 data/clock line (sckb1, sob1, sib1) ? clocked serial interface csib2 data/clock line (sckb2, sob2, sib2) (pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only) ? lcd controller segment signal output (seg36 to seg39) (pd70f3421, pd70f3422, pd70f3423 only) ? lcd controller common signal output (com0 to com4) (pd70f3421, pd70f3422, pd70f3423 only) ? external memory interface data lines d[31:24] (pd70f3427 only) port group 9 includes the following pins: note 1. for pins that support only one alternative output mode, the pfcnm bit is not available. 2. alternative input functions of csib1?csib2 are provided on two pins each. thus you can select on which pin the alternative function should appear. refer to ?alternative input selection? on page 44 . 3. though dbd0-7 is a bidirectional bus pmnm must be set to "0", i.e. to output mode, when the port is used as lcd bus i/f bus dbd0-7. the change of the direction is performed automatically, when data is read from the external bus. table 2-43 port group 9: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) lcd mode (plcdcnm = 1) a external memory interface mode (pmc143 =1) b output mode (pmnm = 0) input mode (pmnm = 1) pfcnm = 0 alt1-out pfcnm = 1 alt2-out p90 (i/o) dbd0 sib1 seg36 a d24 b p90 (i) q p91 (i/o) dbd1 sob1 ? seg37 a d25 b p91 (i) q p92 (i/o) dbd2 sckb1 sckb1 seg38 a d26 b p92 (i) q p93 (i/o) dbd3 ? seg39 a d27 b p93 (i) q p94 (i/o) dbd4 sib2 c com0 a d28 b p94 (i) q p95 (i/o) dbd5 sob2 c ?com1 a d29 b p95 (i) q p96 (i/o) dbd6 sckb2 c sckb2 c com2 a d30 b p96 (i) q p97 (i/o) dbd7 ? com3 a d31 b p97 (i) q a) pd70f3421, pd70f3422, pd70f3423 only b) pd70f3427 only c) pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only
87 pin functions chapter 2 user?s manual u17566ee5v1um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. caution though the lcd bus interface data lines dbd[7:0] are not available for pd70f3421, pd70f3422, and pd70f3423 pfc91 and pfc92 must be set to 1 for making sob1 and sckb1 externally available. thus initialize pfc9 = x6 h always when the csib1 is used on port group 9. table 2-44 port group 9: configuration registers register address initial value used bits pm9 ffff f432 h ff h pm97 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pmc9 ffff f452 h 00 h pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pfc9 ffff f472 h 00 h xpfc96 a a) pd703424, pd70f3425, pd703426a, pd70f3427 only pfc95 a xxpfc92 b b) refer to caution below. pfc91 b x plcdc9 c c) pd70f3421, pd70f3422, pd70f3422 only ffff f352 h 00 h plcdc97 plcdc96 plcdc95 plcdc94 plcdc93 plcdc92 plcdc91 plcdc90 p9 ffff f412 h 00 h p97 p96 p95 p94 p93 p92 p91 p90 prc9 ffff f320 h 00 h xxxxxxxprc90 d d) the setting of prc90 is valid for the entire port group. ppr9 ffff f3d2 h 00 h ppr97 ppr96 ppr95 ppr94 ppr93 ppr92 ppr91 ppr90 pdsc9 e e) not available for pd70f3427 ffff f312 h 00 h pdsc97 pdsc96 pdsc95 pdsc94 pdsc93 pdsc92 pdsc91 pdsc90 picc9 e ffff f392 h ff h picc97 picc96 picc95 picc94 p icc93 picc92 picc91 picc90 pilc9 e ffff f3b2 h 00 h pilc97 pilc96 pilc95 pilc94 pilc93 pilc92 pilc91 pilc90 podc9 ffff f372 h 00 h podc97 podc96 podc95 podc94 podc93 podc92 podc91 podc90
88 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.14 port group 10 port group 10 is an 8-bit port group. in alternative mode, it comprises pins for the following functions: ? timer tmp0 to tmp3 (top00 to top31, tip00 to tip31) ? lcd bus interface read/write strobe (dbrd , dbwr ) (pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only) ? lcd controller segment signal output (seg32 to seg35)(pd70f3421, pd70f3422, pd70f3423 only) ? clocked serial interface csib0 data/clock line (sib0, sob0, sckb0) ? external memory interface data lines d[23:20] (pd70f3427 only) port group 10 includes the following pins note 1. for pins that support only one alternative output mode, the pfcnm bit is not available. 2. alternative input functions of csib0 and tmp0?tmp3 are provided on two pins each. thus you can select on which pin the alternative function should appear. refer to ?alternative input selection? on page 44 . table 2-45 port group 10: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) lcd mode (plcdcnm = 1) a external memory interface mode (pmc143 =1) b output mode (pmnm = 0) input mode (pmnm = 1) pfcnm = 0 alt1-out pfcnm = 1 alt2-out p100 (i/o) top00 top11 tip00/tip11 ? port/alternative mode p100 (i) m p101 (i/o) top01 top10 tip01/tip10 ? port/alternative mode p101 (i) m p102 (i/o) top20 top31 tip20/tip31 ? port/alternative mode p102 (i) m p103 (i/o) top21 top30 tip21/tip30 ? port/alternative mode p103 (i) m p104(i/o) dbrd c ? seg35 a d20 b p104(i) m p105 (i/o) dbwr c sib0 seg34 a d21 b p105 (i) m p106 (i/o) sob0 ? seg33 a d22 b p106 (i) m p107 (i/o) sckb0 sckb0 seg32 a d23 b p107 (i) m a) pd70f3421, pd70f3422, pd70f3423 only b) pd70f3427 only c) pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only
89 pin functions chapter 2 user?s manual u17566ee5v1um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-46 port group 10: configuration registers register address initial value used bits pm10 ffff f434 h ff h pm107 pm106 pm105 pm104 pm103 pm102 pm101 pm100 pmc10 ffff f454 h 00 h pmc107 pmc106 pmc105 pmc104 pmc103 pmc102 pmc101 pmc100 pfc10 ffff f474 h 00 h x x x x pfc103 pfc102 pfc101 pfc100 plcdc10 a a) pd70f3421, pd70f3422, pd70f3423 only ffff f354 h 00 h plcdc107 plcdc106 plcdc105 plcdc104 xxxx p10 ffff f414 h 00 h p107 p106 p105 p104 p103 p102 p101 p100 prc10 ffff f3f4 h 00 h xxxxxxxprc100 b b) the setting of prc100 is valid for the entire port group. ppr10 ffff f3d4 h 00 h ppr107 ppr106 ppr105 ppr10 4 ppr103 ppr102 ppr101 ppr100 pdsc10 ffff f314 h 00 h pdsc107 c c) not available for pd70f3427 pdsc106 c pdsc105 c pdsc104 c pdsc103 pdsc102 pdsc101 pdsc100 picc10 ffff f394 h ff h picc107 c picc106 c picc105 c picc104 c picc103 picc102 picc101 picc100 pilc10 ffff f3b4 h 00 h pilc107 c pilc106 c pilc105 c pilc104 c pilc103 pilc102 pilc101 pilc100 podc10 ffff f374 h 00 h podc107 podc106 podc105 podc104 podc103 podc102 podc101 podc100
90 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.15 port group 11 port group 11 is an 8-bit port group. in alternative mode, it comprises pins for the following functions: ? stepper motor controller/driver outputs (sm11 to sm14, sm21 to sm24) ? timer tmg2 channels (tog21 to tog24) ? sound generator outputs (sgo, sgoa) port group 11 includes the following pins: note 1. for pins that support only one alternative output mode, the pfcnm bit is not available. 2. alternative input functions of tmg2 are provided on two pins each. thus you can select on which pin the alternative function should appear. refer to ?alternative input selection? on page 44 . 3. port group 11 is equipped with high driver buffers for stepper motor control. table 2-47 port group 11: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) output mode (pmnm = 0) input mode (pmnm = 1) pfcnm = 0 alt1-out pfcnm = 1 alt2-out p110 (i/o) sm11 tog21 ? p110 (i) m p111 (i/o) sm12 tog22 ? p111 (i) m p112 (i/o) sm13 tog23 ? p112 (i) m p113 (i/o) sm14 tog24 ? p113 (i) m p114 (i/o) sm21 sgo ? p114 (i) m p115 (i/o) sm22 sgoa ? p115 (i) m p116 (i/o) sm23 ? p116 (i) m p117 (i/o) sm24 ? p117 (i) m
91 pin functions chapter 2 user?s manual u17566ee5v1um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-48 port group 11: configuration registers register address initial value used bits pm11 ffff f436 h ff h pm117 pm116 pm115 pm114 pm113 pm112 pm111 pm110 pmc11 ffff f456 h 00 h pmc117 pmc116 pmc115 pmc114 pmc113 pmc112 pmc111 pmc110 pfc11 ffff f476 h 00 h x x pfc115 pfc114 pfc113 pfc112 pfc111 pfc110 p11 ffff f416 h 00 h p117 p116 p115 p114 p113 p112 p111 p110 prc11 ffff f3f6 h 00 h xxxxxxxprc110 a a) the setting of prc110 is valid for the entire port group. ppr11 ffff f3d6 h 00 h ppr117 ppr116 ppr115 ppr11 4 ppr113 ppr112 ppr111 ppr110 picc11 ffff f396 h ff h picc117 picc116 picc115 picc114 picc113 picc112 picc111 picc110 pilc11 ffff f3b6 h 00 h pilc117 pilc116 pilc115 pilc114 pilc113 pilc112 pilc111 pilc110 podc11 ffff f376 h 00 h podc117 podc116 podc115 podc114 podc113 podc112 podc111 podc110
92 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.16 port group 12 port group 12 is an 8-bit port group. in alternative mode, it comprises pins for the following functions: ? stepper motor controller/driver outputs (sm51 to sm54, sm61 to sm64) port group 12 includes the following pins: note port group 12 is equipped with high driver buffers for stepper motor control. access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-49 port group 12: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) output mode (pmnm = 0) input mode (pmnm = 1) p120 (i/o) sm51 ? p120 (i) m p121 (i/o) sm52 ? p121 (i) m p122 (i/o) sm53 ? p122 (i) m p123 (i/o) sm54 ? p123 (i) m p124 (i/o) sm61 ? p124 (i) m p125 (i/o) sm62 ? p125 (i) m p126 (i/o) sm63 ? p126 (i) m p127 (i/o) sm64 ? p127 (i) m table 2-50 port group 12: configuration registers register address initial value used bits pm12 a a) pm12 register has to be changed from its default value ff h to 00 h in order to enable the stepper motor con- troller/driver outputs. ffff f438 h ff h pm127 pm126 pm125 pm124 pm123 pm122 pm121 pm120 pmc12 ffff f458 h 00 h pmc127 pmc126 pmc125 pmc124 pmc123 pmc122 pmc121 pmc120 p12 ffff f418 h 00 h p127 p126 p125 p124 p123 p122 p121 p120 prc12 ffff f3f8 h 00 h xxxxxxxprc120 b b) the setting of prc120 is valid for the entire port group. ppr12 ffff f3d8 h 00 h ppr127 ppr126 ppr125 ppr12 4 ppr123 ppr122 ppr121 ppr120 picc12 ffff f398 h ff h picc127 picc126 picc125 picc124 picc123 picc122 picc121 picc120 pilc12 ffff f3b8 h 00 h pilc127 pilc126 pilc125 pilc124 pilc123 pilc122 pilc121 pilc120 podc12 ffff f378 h 00 h podc127 podc126 podc125 podc124 podc123 podc122 podc121 podc120
93 pin functions chapter 2 user?s manual u17566ee5v1um00 2.4.17 port group 13 port group 13 is an 8-bit port group. in alternative mode, it comprises pins for the following functions: ? stepper motor controller/driver outputs (sm31 to sm34, sm41 to sm44) ? timer tmg0 to tmg1 channels (tig01 to tig04, tog01 to tog04, tig11 to tig14, tog11 to tog14) port group 13 includes the following pins: note 1. alternative input functions of tmg0?tmg1 are provided on two pins each. thus you can select on which pin the alternative function should appear. refer to ?alternative input selection? on page 44 . 2. port group 13 is equipped with high driver buffers for stepper motor control. access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-51 port group 13: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) output mode (pmnm = 0) input mode (pmnm = 1) pfcnm = 0 alt1-out pfcnm = 1 alt2-out p130 (i/o) sm31 tog01 tig01 p130 (i) m p131 (i/o) sm32 tog02 tig02 p131 (i) m p132 (i/o) sm33 tog03 tig03 p132 (i) m p133 (i/o) sm34 tog04 tig04 p133 (i) m p134 (i/o) sm41 tog11 tig11 p134 (i) m p135 (i/o) sm42 tog12 tig12 p135 (i) m p136 (i/o) sm43 tog13 tig13 p136 (i) m p137 (i/o) sm44 tog14 tig14 p137 (i) m table 2-52 port group 13: configuration registers register address initial value used bits pm13 ffff f43a h ff h pm137 pm136 pm135 pm134 pm133 pm132 pm131 pm130 pmc13 ffff f45a h 00 h pmc137 pmc136 pmc135 pmc134 pmc133 pmc132 pmc131 pmc130 pfc13 ffff f47a h 00 h pfc137 pfc136 pfc135 pfc134 pfc133 pfc132 pfc131 pfc130 p13 ffff f41a h 00 h p137 p136 p135 p134 p133 p132 p131 p130 prc13 ffff f3fa h 00 h xxxxxxxprc130 a a) the setting of prc130 is valid for the entire port group. ppr13 ffff f3da h 00 h ppr137 ppr136 ppr135 ppr134 p pr133 ppr132 ppr131 ppr130 picc13 ffff f39a h ff h picc137 picc136 picc135 picc134 picc133 picc132 picc131 picc130 pilc13 ffff f3ba h 00 h pilc137 pilc136 pilc135 pilc134 pilc133 pilc132 pilc131 pilc130 podc13 ffff f37a h 00 h podc137 podc136 podc135 podc134 podc133 podc132 podc131 podc130
94 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.18 port group 14 (pd70f3427 only) port group 14 is a 3-bit port group. in alternative mode, it comprises pins for the following functions: ? external memory interface bus clock bclk ? external memory interface byte enable signals be2 , be3 port group 14 includes the following pins: access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-53 port group 14: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) output mode (pmnm = 0) input mode (pmnm = 1) p140 (i/o) bclk ? p140 (i) m p141 (i/o) be2 ? p141 (i) m p142 (i/o) be3 ? p142 (i) m table 2-54 port group 14: configuration registers register address initial value used bits pm14 ffff f43c h ff h xxxxxpm142pm141pm140 pmc14 ffff f45c h 10 h xxx1 a a) this bit is set to 1 after reset and cannot be changed. pmc143 b b) pmc143 specifies the data bus width of the external memory interface: - pmc143 = 0: 16-bit data bus d[15:0], d[31:16] pins of port groups 3, 8, 9, 10 operate in port/alternative mode - pmc143 = 1: 32-bit data bus d[31:0], d[31:16] pins of port groups 3, 8, 9, 10 operate as data bus pins pmc142 pmc141 pmc140 p14 ffff f41c h 00 h xxxxxp142p141p140 prc14 ffff f3fc h 00 h xxxxxxxprc140 c c) the setting of prc140 is valid for the entire port group. ppr14 ffff f3dc h 00 h x x x x x ppr142 ppr141 ppr140
95 pin functions chapter 2 user?s manual u17566ee5v1um00 2.4.19 port group al port group al is a 16-bit port group. in alternative mode, it comprises pins for the external memory interface address lines 0 to 15. this port group is externally only available for pd70f3419 devices. caution for the pd70f3418 this port group must be configured as output port mode. thus set following registers as shown below: ? port mode: pmcal = 0000 h ? output port: pmal = 0000 h port group al includes the following pins: table 2-55 port group al: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) output mode (pmnm = 0) input mode (pmnm = 1) pal0 (i/o) a0 - pal0 (i) m pal1 (i/o) a1 - pal1 (i) m pal2 (i/o) a2 - pal2 (i) m pal3 (i/o) a3 - pal3 (i) m pal4 (i/o) a4 - pal4 (i) m pal5 (i/o) a5 - pal5 (i) m pal6 (i/o) a6 - pal6 (i) m pal7 (i/o) a7 - pal7 (i) m pal8 (i/o) a8 - pal8 (i) m pal9 (i/o) a9 - pal9 (i) m pal10 (i/o) a10 - pal10 (i) m pal11 (i/o) a11 - pal11 (i) m pal12 (i/o) a12 - pal12 (i) m pal13 (i/o) a13 - pal13 (i) m pal14 (i/o) a14 - pal14 (i) m pal15 (i/o) a15 - pal15 (i) m
96 chapter 2 pin functions user?s manual u17566ee5v1um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. all 16-bit registers can be accessed in 16-bit units. table 2-56 port group al: configuration registers register address initial value used bits pmall ffff f020 h ff h pmal7 pmal6 pmal5 pmal4 pmal3 pmal2 pmal1 pmal0 pmalh ffff f021 h ff h pmal15 pmal14 pmal13 pmal12 pmal11 pmal10 pmal9 pmal8 pmal (16 bit) ffff f020 h ffff h pmal15 to pmal8 (pmalh) pmal7 to pmal0 (pmall) pmcall ffff f040 h 00 h pmcal7 pmcal6 pmcal5 pmcal4 pmcal3 pmcal2 pmcal1 pmcal0 pmcalh ffff f041 h 00 h pmcal15 pmcal14 pmcal13 pmcal12 pmcal11 pmcal10 pmcal9 pmcal8 pmcal (16 bit) ffff f040 h 0000 h pmcal15 to pmcal8 (pmcalh) pmcal7 to pmcal0 (pmcall) pall ffff f000 h 00 h pa l 7 pa l 6 pa l 5 pa l 4 pa l 3 pa l 2 pa l 1 pa l 0 palh ffff f001 h 00 h pa l 1 5 pa l 1 4 pa l 1 3 pa l 1 2 pa l 1 1 pa l 1 0 pa l 9 pa l 8 pa l (16 bit) ffff f000 h 0000 h pal15 to pal8 (palh) pal7 to pal0 (pall) prcal ffff f2e0 h 00 h xxxxxxxprcal0 a a) the setting of prcal0 is valid for the entire port group. pprall ffff f2c0 h 00 h ppral7 ppral6 ppral5 ppral4 ppral3 ppral2 ppral1 ppral0 ppralh ffff f2c1 h 00 h ppral15 ppral14 ppral13 ppral12 ppral11 ppral10 ppral9 ppral8 ppral (16 bit) ffff f2c0 h 0000 h ppral15 to ppral8 (ppralh) ppral7 to ppral0 (pprall) pdsceal ffff f260 h 00 h xxxxxxx pdsceal0 pdscal ffff f240 h 00 h xxxxxxx pdscal0 piccal ffff f280 h ff h xxxxxxxpiccal0 pilcal ffff f2a0 h 01 h xxxxxxxpilcal0
97 pin functions chapter 2 user?s manual u17566ee5v1um00 2.4.20 port group ah port group ah is a 7-bit port group. in alternative mode, it comprises pins for the external memory interface address lines 16 to 22. this port group is externally only available for pd70f3419 devices. caution for the pd70f3418 this port group must be configured as output port mode. thus set following registers as shown below: ? port mode: pmcah = 00 h ? output port: pmah = 00 h port group ah includes the following pins: access all 8-bit registers can be accessed in 8-bit or 1-bit units. all 16-bit registers can be accessed in 16-bit units. table 2-57 port group ah: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) output mode (pmnm = 0) input mode (pmnm = 1) pah0 (i/o) a16 - pah0 (i) m pah1 (i/o) a17 - pah1 (i) m pah2 (i/o) a18 - pah2 (i) m pah3 (i/o) a19 - pah3 (i) m pah4 (i/o) a20 - pah4 (i) m pah5 (i/o) a21 - pah5 (i) m pah6 (i/o) a22 - pah6 (i) m table 2-58 port group ah: configuration registers register address initial value used bits pmah ffff f022 h ff h ? pmah6 pmah5 pmah4 pmah3 pmah2 pmah1 pmah0 pmcah ffff f042 h 00 h ? pmcah6 pmcah5 pmcah4 pmcah3 pmcah2 pmcah1 pmcah0 pah ffff f002 h 00 h ? pah6 pah5 pah4 pah3 pah2 pah1 pah0 prcah ffff f2e2 h 00 h ?xxxxxxprcah0 a a) the setting of prcah0 is valid for the entire port group. pprah ffff f2c2 h 00 h ? pprah6 pprah5 pprah4 pprah3 pprah2 pprah1 pprah0 pdsceah ffff f262 h 00 h ?xxxxxx pdsceah0 pdscah ffff f242 h 00 h ?xxxxxx pdscah0 piccah ffff f282 h ff h ?xxxxxxpiccah0 pilcah ffff f2a2 h 01 h ?xxxxxxpilcah0
98 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.21 port group cs port group cs is a 3-bit port group. in alternative mode, it comprises pins for the following functions: ? external memory interface chip select signals (cs0 , cs3 , cs4 ) ? external memory interface data wait request (wait ) this port group is externally only available for pd70f3419 devices. caution for the pd70f3418 this port group must be configured as output port mode. thus set following registers as shown below: ? port mode: pmccs = 00 h ? output port: pmcs = 00 h port group cs includes the following pins: access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-59 port group cs: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) output mode (pmnm = 0) input mode (pmnm = 1) pcs0 (i/o) cs0 ?pcs0 (i)m pcs3 (i/o) cs3 ?pcs3 (i)m pcs4 (i/o) cs4 wait pcs4 (i) m table 2-60 port group cs: configuration registers register address initial value used bits pmcs ffff f028 h ff h xxxpmcs4pmcs3xxpmcs0 pmccs ffff f048 h 00 h xxxpmccs4pmccs3xxpmccs0 pcs ffff f008 h 00 h xxxpcs4pcs3xxpcs0 prccs ffff f2e8 h 00 h xxxx x xxp rccs0 a a) the setting of prccs0 is valid for the entire port group. pprcs ffff f2c8 h 00 h x x x pprcs4 pprcs3 x x pprcs0 pdscecs ffff f268 h 00 h xxxx x xxpdscecs0 pdsccs ffff f248 h 00 h xxxx x xxpdsccs0 picccs ffff f288 h ff h xxxx x xxpicccs0 pilccs ffff f2a8 h 01 h xxxx x xxpilccs0
99 pin functions chapter 2 user?s manual u17566ee5v1um00 2.4.22 port group ct port group ct is a 2-bit port group. in alternative mode, it comprises pins for the external memory interface read/write strobe. this port group is externally only available for pd70f3419 devices. caution for the pd70f3418 this port group must be configured as output port mode. thus set following registers as shown below: ? port mode: pmcct = 00 h ? output port: pmct = 00 h port group ct includes the following pins: access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-61 port group ct: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) output mode (pmnm = 0) input mode (pmnm = 1) pct0 (i/o) wr ?pct0 (i)m pct4 (i/o) rd ?pct4 (i)m table 2-62 port group ct: configuration registers register address initial value used bits pmct ffff f02a h ff h xxxpmct4xxxpmct0 pmcct ffff f04a h 00 h x x x pmcct4 x x x pmcct0 pct ffff f00a h 00 h xxxpct4xxxpct0 prcct ffff f2ea h 00 h x x x x x x x prcct0 a a) the setting of prcct0 is valid for the entire port group. pprct ffff f2ca h 00 h x x x pprct4 x x x pprct0 pdscect ffff f26a h 00 h xxxx xxxpdscect0 pdscct ffff f24a h 00 h xxxx xxxpdscct0 piccct ffff f28a h ff h x x x x x x x piccct0 pilcct ffff f2aa h 01 h xxxx xxxpilcct0
100 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.23 port group dl port group dl is a 16-bit port group. in alternative mode, it comprises pins for the external memory interface data lines 0 to 15. this port group is externally only available for pd70f3419 devices. caution for the pd70f3418 this port group must be configured as output port mode. thus set following registers as shown below: ? port mode: pmcdl = 00 h ? output port: pmdl = 00 h port group dl includes the following pins: note though d0-15 is a bidirectional bus don?t care about pmnm. the change of the input and output direction is performed automatically, when data is read from or written to the external bus. table 2-63 port group dl: pin functions and port type pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) pdl0 (i/o) d0 pdl0 (i) m pdl1 (i/o) d1 pdl1 (i) m pdl2 (i/o) d2 pdl2 (i) m pdl3 (i/o) d3 pdl3 (i) m pdl4 (i/o) d4 pdl4 (i) m pdl5 (i/o) d5 pdl5 (i) m pdl6 (i/o) d6 pdl6 (i) m pdl7 (i/o) d7 pdl7 (i) m pdl8 (i/o) d8 pdl8 (i) m pdl9 (i/o) d9 pdl9 (i) m pdl10 (i/o) d10 pdl10 (i) m pdl11 (i/o) d11 pdl11 (i) m pdl12 (i/o) d12 pdl12 (i) m pdl13 (i/o) d13 pdl13 (i) m pdl14 (i/o) d14 pdl14 (i) m pdl15 (i/o) d15 pdl15 (i) m
101 pin functions chapter 2 user?s manual u17566ee5v1um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. all 16-bit registers can be accessed in 16-bit units. table 2-64 port group dl: configuration registers register address initial value used bits pmdll ffff f024 h ff h pmdl7 pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 pmdlh ffff f025 h ff h pmdl15 pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 pmdl (16 bit) ffff f024 h ffff h pmdl15 to pmdl8 (pmdlh) pmdl7 to pmdl0 (pmdll) pmcdll ffff f044 h 00 h pmcdl7 pmcdl6 pmcdl5 pmcdl4 p mcdl3 pmcdl2 pmcdl1 pmcdl0 pmcdlh ffff f045 h 00 h pmcdl15 pmcdl14 pmcdl13 pmcdl12 pmcdl11 pmcdl10 pmcdl9 pmcdl8 pmcdl (16 bit) ffff f044 h 0000 h pmcdl15 to pmcdl8 (pmcdlh) pmcdl7 to pmcdl0 (pmcdll) pdll ffff f004 h 00 h pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 pdlh ffff f005 h 00 h pdl15 pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 pdl (16 bit) ffff f004 h 0000 h pdl15 to pdl8 (pdlh) pdl7 to pdl0 (pdll) prcdl ffff f2e4 h 00 h xxxxxxxp rcdl0 a a) the setting of prcdl0 is valid for the entire port group. pprdll ffff f2c4 h 00 h pprdl7 pprdl6 pprdl5 pprdl4 pprdl3 pprdl2 pprdl1 pprdl0 pprdlh ffff f2c5 h 00 h pprdl15 pprdl14 pprdl13 pprdl12 pprdl11 pprdl10 pprdl9 pprdl8 pprdl (16 bit) ffff f2c4 h 0000 h pprdl15 to pprdl8 (pprdlh) pprdl7 to pprdl0 (pprdll) pdscedl ffff f264 h 00 h xxxxxxx pdscedl0 pdscdl ffff f244 h 00 h xxxxxxx pdscdl0 piccdl ffff f284 h ff h xxxxxxxpiccdl0 pilcdl ffff f2a4 h 01 h xxxxxxxpilcdl0
102 chapter 2 pin functions user?s manual u17566ee5v1um00 2.4.24 port group dh port group dh is a 16-bit port group. in alternative mode, it comprises pins for the external memory interface data lines 16 to 31. this port group is externally only available for pd70f3419 devices. caution for the pd70f3418 this port group must be configured as output port mode. thus set following registers as shown below: ? port mode: pmcdh = 00 h ? output port: pmdh = 00 h port group dh includes the following pins: note though d16-31 is a bidirectional bus don?t care about pmnm. the change of the input and output direction is performed automatically, when data is read from or written to the external bus. table 2-65 port group dh: pin functions and port types pin functions in different modes pin function after reset port type port mode (pmcnm = 0) alternative mode (pmcnm = 1) pdh0 (i/o) d16 pdh0 (i) m pdh1 (i/o) d17 pdh1 (i) m pdh2 (i/o) d18 pdh2 (i) m pdh3 (i/o) d19 pdh3 (i) m pdh4 (i/o) d20 pdh4 (i) m pdh5 (i/o) d21 pdh5 (i) m pdh6 (i/o) d22 pdh6 (i) m pdh7 (i/o) d23 pdh7 (i) m pdh8 (i/o) d24 pdh8 (i) m pdh9 (i/o) d25 pdh9 (i) m pdh10 (i/o) d26 pdh10 (i) m pdh11 (i/o) d27 pdh11 (i) m pdh12 (i/o) d28 pdh12 (i) m pdh13 (i/o) d29 pdh13 (i) m pdh14 (i/o) d30 pdh14 (i) m pdh15 (i/o) d31 pdh15 (i) m
103 pin functions chapter 2 user?s manual u17566ee5v1um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. all 16-bit registers can be accessed in 16-bit units. table 2-66 port group dh: configuration registers register address initial value used bits pmdhl ffff f026 h ff h pmdh7 pmdh6 pmdh5 pmdh4 pmdh3 pmdh2 pmdh1 pmdh0 pmdhh ffff f027 h ff h pmdh15 pmdh14 pmdh13 pmdh12 pmdh11 pmdh10 pmdh9 pmdh8 pmdh (16 bit) ffff f026 h ffff h pmdhl15 to pmdh8 (pmdhh) pmdh7 to pmdh0 (pmdhl) pmcdhl ffff f046 h 00 h pmcdh7 pmcdh6 pmcdh5 pmcdh4 pmcdh3 pmcdh2 pmcdh1 pmcdh0 pmcdhh ffff f047 h 00 h pmcdh15 pmcdh14 pmcdh13 pmcdh12 pmcdh11 pmcdh10 pmcdh9 pmcdh8 pmcdh (16 bit) ffff f046 h 0000 h pmcdhl15 to pmcdh8 (pmcdhh) pmcdh7 to pmcdh0 (pmcdhl) pdhl ffff f006 h 00 h pdh7 pdh6 pdh5 pdh4 pdh3 pdh2 pdh1 pdh0 pdhh ffff f007 h 00 h pdh15 pdh14 pdh13 pdh12 pdh11 pdh10 pdh9 pdh8 pdh (16 bit) ffff f006 h 0000 h pdh15 to pdh8 (pdhh) pdh7 to pdh0 (pdhl) prcdh ffff f2e6 h 00 h xxxxxxxp rcdh0 a a) the setting of prcdh0 is valid for the entire port group. pprdhl ffff f2c6 h 00 h pprdh7 pprdh6 pprdh5 pprdh4 pprdh3 pprdh2 pprdh1 pprdh0 pprdhh ffff f2c7 h 00 h pprdh15 pprdh14 pprdh13 pprdh12 pprdh11 pprdh10 pprdh9 pprdh8 pprdh (16 bit) ffff f2c6 h 0000 h pprdh15 to pprdh8 (pprdhh) pprdh7 to pprdh0 (pprdhl) pdscedh ffff f266 h 00 h xxxxxxx pdscedh0 pdscdh ffff f246 h 00 h xxxxxxx pdscdh0 piccdh ffff f286 h ff h xxxxxxxpi ccdh0 pilcdh ffff f2a6 h 01 h xxxxxxxpil cdh0
104 chapter 2 pin functions user?s manual u17566ee5v1um00 2.5 noise elimination the input signals at some pins are passed through a filter to remove noise and glitches. the microcontroller supports both analog and digital filters. the analog filters are always applied to the input signals, whereas the digital filters can be enabled/disabled by control registers. 2.5.1 analog filtered inputs the external interrupts intp0?intp7and nmi and the external reset input are passed through an analog filter to remove noise and glitches. the analog filter suppresses input pulses that are shorter than a specified puls width (refer to the data sheet). this assures the hold time for the external interrupt signals. the analog filter operates in all modes (normal mode and standby modes). it is only effective if the corresponding pin works in alternative input mode and not as a general purpose i/o port. 2.5.2 digitally filtered inputs the inputs of the peripherals listed below are passed through a digital filter to remove noise and glitches. the digital filter operates in all modes, which have the pll enabled. thus, it does not operate in watch, sub-watch and idle mode. the digital filter is only effective if the corresponding pin works in alternative input mode and not as a general purpose i/o port. the digital input filter is available for the following external signals: note the timers g provide additional digital noise filters at their capture inputs tign1 to tign4. refer also to the data sheet for the minimum capture inputs pulse widths. table 2-67 digitally filtered external signals module signal comment csib0 sib0, sckb0 for high clock rates of the clocked serial interface, the digital filter should be disabled. otherwise, desired input pulses may be removed by the digital filter. csib1 sib1, sckb1 csib2 sib2, sckb2 tmp0 tip00, tip01 tmp1 tip10, tip11 tmp2 tip20, tip21 tmp3 tip30, tip31 tmg0 tig01 to tig04 tmg1 tig11 to tig14 tmg2 tig20 to tig25
105 pin functions chapter 2 user?s manual u17566ee5v1um00 filter operation the input terminal signal is sampled with the sampling frequency f s . spikes shorter than 2 sampling cycles are suppressed and no internal signal is generated. pulses longer than 3 sampling cycles are recognized as valid pulses and an internal signal is generated. for pulses between 2 and 3 sampling cycles, the behaviour is not defined. the filter operation is illustrated in figure 2-6 . figure 2-6 digital noise removal example the minimum input terminal pulse width to be validated is defined by the sampling frequency f s . the sampling frequency f s is pclk0. the digital filter function can be individually enabled for each of the aforementioned external input signals. the filter is enabled/disabled by the 16-bit registers dfen0 and dfen1. input terminal filter output table 2-68 digital noise removal features sampling frequency f s = pclk0 minimum pulse width to generate an internal signal 16 mhz (pll enabled) 0.125 ? 0.1875 sec 4 mhz (pll disabled) 0.5 ? 0.75 sec
106 chapter 2 pin functions user?s manual u17566ee5v1um00 (1) dfen0 - digital filter enable register the 16-bit dfen0 register enables/disables the digital filter for tmp0 to tmp3 and tmg0 input channels and for csib0 to csib2 input channels. access this register can be read/written in 16-bit, 8-bit and 1-bit units. address ffff f710 h initial value 0000 h . this register is cleared by any reset. 15 14 13 12 11 10 9 8 dfenc15 dfenc14 dfenc13 dfenc12 dfenc11 dfenc10 dfenc9 dfenc8 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 dfenc7 dfenc6 dfenc5 dfenc4 dfenc3 dfenc2 dfenc1 dfenc0 r/w r/w r/w r/w r/w r/w r/w r/w table 2-69 dfen0 register contents bit position bit name function 15 to 0 dfenc[15:0] enables/disables the digital noise elimination filter for the corresponding input signal: 0: digital filter is disabled. 1: digital filter is enabled. for an assignment of bit positions to input signals see table ta bl e 2 - 7 0 . table 2-70 assignment of input signals to bit positions for register dfen0 bit position bit name input signal description 0 dfenc0 sib0 csib0 data input a a) note that the digital filter should be disabled for high clock rates of the clocked serial interface. otherwise, desired input pulses may be suspended by the digital filter. 1 dfenc1 sib1 csib1 data input a 2 dfenc2 sib2 csib2 data input a b b) pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only 3 dfenc3 sckib0 csib0 clock input a 4 dfenc4 sckib1 csib1 clock input a - 5 dfenc5 sckib2 csib2 clock input a b 6 dfenc6 tip00 timer tmp0 channel 0 capture input 7 dfenc7 tip01 timer tmp0 channel 1 capture input 8 dfenc8 tip10 timer tmp1 channel 0 capture input 9 dfenc9 tip11 timer tmp1 channel 1 capture input 10 dfenc10 tip20 timer tmp2 channel 0 capture input 11 dfenc11 tip21 timer tmp2 channel 1 capture input 12 dfenc12 tip30 timer tmp3 channel 0 capture input 13 dfenc13 tip31 timer tmp3 channel 1 capture input 14 dfenc14 tig01 timer tmg0 channel 1 capture input 15 dfenc15 tig02 timer tmg0 channel 2 capture input
107 pin functions chapter 2 user?s manual u17566ee5v1um00 (2) dfen1 - digital filter enable register the 16-bit dfen1 register enables/disables the digital filter for tmg0 to tmg2 and tmp0 to tmp1 input channels. access this register can be read/written in 16-bit, 8-bit and 1-bit units. address ffff f712 h initial value 0000 h . this register is cleared by any reset. 15 14 13 12 11 10 9 8 x x x x dfenc27 dfenc26 dfenc25 dfenc24 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 dfenc23 dfenc22 dfenc21 dfenc20 dfenc19 dfenc18 dfenc17 dfenc16 r/w r/w r/w r/w r/w r/w r/w r/w table 2-71 dfen1 register contents bit position bit name function 11 to 0 dfenc[27:16] enables/disables the digital noise elimination filter for the corresponding input signal: 0: digital filter is disabled. 1: digital filter is enabled. for an assignment of bit positions to input signals see table ta b l e 2 - 7 2 . table 2-72 assignment of input signals to bit positions for register dfen1 bit position bit name input signal description 0 dfenc16 tig03 timer tmg0 channel 3 capture input 1 dfenc17 tig04 timer tmg0 channel 4 capture input 2 dfenc18 tig11 timer tmg1 channel 1 capture input 3 dfenc19 tig12 timer tmg1 channel 2 capture input 4 dfenc20 tig13 timer tmg1 channel 3 capture input 5 dfenc21 tig14 timer tmg1 channel 4 capture input 6 dfenc22 tip00/tig20 shared input: timer tmp0 channel 0 capture input / timer tmg2 channel 0 capture input 7 dfenc23 tig21 timer tmg2 channel 1 capture input 8 dfenc24 tig22 timer tmg2 channel 2 capture input 9 dfenc25 tig23 timer tmg2 channel 3 capture input 10 dfenc26 tig24 timer tmg2 channel 4 capture input 11 dfenc27 tip10/ttig25 shared input: timer tmp1 channel 0 capture input/ timer tmg2 channel 5 capture input
108 chapter 2 pin functions user?s manual u17566ee5v1um00 2.6 pin functions in reset and power save modes the following table summarizes the status of the pins during reset and power save modes and after release of these operating states in normal operation mode, i.e. = 0. the reset source makes a difference concerning the n-wire debugger interface pins drst , ddi, ddo, dck and dms after reset release. an external reset or an internal power-on-clear switches all pins to input port mode, while all other internal reset sources make the pins available for the debugger. in contrast to all other power save modes the halt mode suspends only the cpu operation and has no effect on any pin status. table 2-73 pin functions during and after reset / power save modes note for information about the status of the external memory i/f pins refer to chapter 7 on page 255 . if flash programming mode is enabled by flmd0 = 1, p07 is used as flmd1 pin in input port mode during and after reset. operating status pin status power-on- clear during ? p05/drst : p05 port input with internal pull-down resistor ? all other pins: hi-z (3-state) after ? all ports pnm: input port mode ? a[23:0], d[15:0], be[1:0] , rd , wr , wait : input external reset during ? p05/drst : p05 port input with internal pull-down resistor ? all other pins: hi-z (3-state) after ? p05/drst : drst input with internal pull-down resistor ? p52/ddi, p54/dck, p55/dms: ddi, dck, dms inputs ? p53/ddo: ddo output ? all ports pnm: input port mode ? a[23:0], d[15:0], be[1:0] , rd , wr , wait : input all other reset sources during ? p05/drst : p05 port input with internal pull-down resistor ? all other pins: hi-z (3-state) after ? p05/drst, p52/ddi, p54/dck, p55/dms, p53/ddo: no change. same function as before reset ? all ports pnm: input port mode ? a[23:0], d[15:0], be[1:0] , rd , wr , wait : input halt mode during same as before halt mode after idle, watch, sub-watc h, stop mode during same as before power save mode: ? output signals are valid and output levels are remained. ? input signals with wake-up capability a are valid. ? input signals without wake-up capability are ignored. a) inputs with wake-up capability: external interrupts (intp0 to intp7, nmi) and can receive data (crxd0, crxd1) after same as before power save mode
109 pin functions chapter 2 user?s manual u17566ee5v1um00 2.7 recommended connection of unused pins if a pin is not used, it is recommended to connect it as follows: ? output pins: leave open ? input pins: connect to v dd5 or v ss5 sub oscillator connection if no sub oscillator crystal is connected , connect xt1 to v ss and leave xt2 open. pd70f3427 memory interface if the external memory interface of the pd70f3427 is not used connect the pins d[15:0] via pull-up or pull-down resistors to mv dd5n respectively mv ss5n . caution note that the wait pin must be connected to mv dd5n via a pull-up resistor in any case, also if the memory interface is used. note if the overall maximum output current of a concerned pin group exceeds its maximum value the output buffer can be damaged. a placement of a series resistor to prevent damage in case of accidentally enabled outputs is recommended. refer to the absolute maximum rating parameter in the data sheet.
110 chapter 2 pin functions user?s manual u17566ee5v1um00 2.8 package pins assignment the following sections show the location of pins in top view. every pin is labelled with its pin number and all possible pin names. 2.8.1 pd70f3421, pd70f3422, pd70f3423 figure 2-7 pin overview of pd70f3421, pd70f3422, pd70f3423 v 8 50e / dj 3 pd70f 3 421 pd70f 3 422 pd70f 3 42 3 55 p40/intp6/ s ib0 6 3 p 3 0/txda0/ s da1 1 3 5 p79/ain9 8 5 p64/tip20/top20/ s cl0/ s eg16 100 p 33 /rxda1/ s eg29 54 p100/tip00/tip11/top00/top11 33 p04/intp4 1 avref 70 p21/tig02/tog02/ s cl1/ s eg1 64 vdd51 45 v ss 50 75 p26/tig1 3 /tog1 3 / s eg6 104 p106/ s ob0/ s eg 33 9 s mv ss 50 16 p122/ s m5 3 21 p127/ s m64 109 p92/ s ckb1/dbd2/ s eg 38 3 0 p1 3 6/tig1 3 / s m4 3 /tog1 3 5 3 p101/tip01/tip10/top01/top10 47 p50/fout/ s goa 115 dvdd50 114 p97/dbd7/com 3 51 p10 3 /tip21/tip 3 0/top21/top 3 0 90 bv ss 51 40 p54/dck 88 p67/tig2 3 /tip 3 1/tog2 3 /top 3 1/ s eg19 12 8 vcmp1 77 p 3 4/tig21/tog21/top01/ s eg 8 126 p07/intp6/vcmpo0/vcmpo1/flmd1 71 p22/tig0 3 /tog0 3 / s eg2 96 p 8 1/ s eg25 5 p111/ s m12/tog22 57 p42/ s ckb0 61 p47/ctxd0 12 p116/ s m2 3 19 p125/ s m62 24 p1 3 2/tig0 3 / s m 33 /tog0 3 112 p95/dbd5/com1 62 p 3 1/rxda0/ s cl1 8 4 p6 3 /tig24/tip11/tog24/top11/ s eg15 102 p 3 2/txda1/ s eg 3 1 8 0 p 3 7/tig24/tog24/top11/ s eg11 60 p46/crxd0 3 4 p0 3 /intp 3 69 p20/tig01/tog01/ s da1/ s eg0 4 3 vdd50 26 s mvdd51 74 p25/tig12/tog12/ s eg5 105 p105/ s ib0/dbwr/ s eg 3 4 41 p5 3 /ddo 124 xt1 15 p121/ s m52 20 p126/ s m6 3 10 8 p91/dbd1/ s ob1/ s eg 3 7 29 p1 3 5/tig12/ s m42/tog12 8 9 bvdd51 144 p70/ain0 50 bv ss 50 11 3 p96/dbd6/com2 52 p102/tip20/tip 3 1/top20/top 3 1 8 2 p61/tig21/tip01/tog21/top01/ s eg1 3 1 3 4 p710/ain10 125 xt2 8 7 p66/tig22/tip21/tog22/top21/ s eg1 8 127 vcmp0 3 6 p01/intp1 3 2 p06/intp5 3 av ss 59 p57/txda1/ctxd1 14 3 p71/ain1 1 33 p711/ain11 119 v ss 52 97 p 8 0/ s eg26 4 p110/ s m11/tog21 12 3 re s et 11 p115/ s m22/ s goa 1 8 p124/ s m61 2 3 p1 3 1/tig02/ s m 3 2/tog02 111 p94/dbd4/com0 142 p72/ain2 1 3 2 p712 9 8 p 8 5/fout/ s eg27 83 p62/tig25/tip10/top10/ s eg14 42 p52/ddi 99 p 8 7/rxda0/ s eg2 8 79 p 3 6/tig2 3 /tog2 3 /top 3 1/ s eg10 141 p7 3 /ain 3 3 5 p02/intp2 6 8 p17/ s cl0/crxd2 2 avdd 1 3 1 p71 3 11 8 regc2 8 s mvdd50 106 p104/dbrd/ s eg 3 5 7 3 p24/tig11/tog11/ s eg4 94 7 -p11 3 / s m14/tog24 14 p120/ s m51 140 p74/ain4 107 p90/dbd0/ s ib1/ s eg 3 6 2 8 p1 3 4/tig11/ s m41/tog11 1 3 0 p714 5 8 p56/rxda1/crxd1 121 x1 49 bvdd50 44 regc0 46 p 8 4/toy0 8 1 p60/tig20/tip00/top00/ s eg12 91 p45/ s ckb1/ s eg20 8 6 p65/tip 3 0/top 3 0/ s da0/ s eg17 3 7 p00/intp0/nmi 1 3 9 p75/ain5 129 p715 38 p05/dr s t 122 x2 117 vdd52 66 v ss 51 76 p27/tig14/tog14/ s eg7 10 3 p107/ s ckb0/ s eg 3 2 27 s mv ss 51 10 p114/ s m21/ s go 4 8 p51/ s go 17 p12 3 / s m54 1 38 p76/ain6 92 p44/ s ob1/ s eg21 22 p1 3 0/tig01/ s m 3 1/tog01 110 p9 3 /dbd 3 / s eg 3 9 3 1 p1 3 7/tig14/ s m44/tog14 116 dv ss 50 56 p41/ s ob0 101 p 8 6/txda0/ s eg 3 0 1 3 7 p77/ain7 120 flmd0 7 8 p 3 5/tig22/tog22/top21/ s eg9 67 p16/ s da0/ctxd2 65 regc1 9 3 p4 3 / s ib1/ s eg22 3 9 p55/dm s 72 p2 3 /tig04/tog04/ s eg 3 95 p 8 2/ s eg24 6 p112/ s m1 3 /tog2 3 1 3 6 p7 8 /ain 8 1 3 p117/ s m24 25 p1 33 /tig04/ s m 3 4/tog04 p 83 /toy0/fout/ s eg2 3
111 pin functions chapter 2 user?s manual u17566ee5v1um00 2.8.2 pd70f3424, pd70f3425, pd70f3426a figure 2-8 pin overview of pd70f3424, pd70f3425, pd70f3426a note crxd2, ctxd2 not available on pd70f3426a v 8 50e / dj 3 pd70f 3 424 pd70f 3 425 pd70f 3 426a 55 p40/intp6/ s ib0 6 3 p 3 0/txda0/ s da1 1 3 5 p79/ain9 8 5 p64/tip20/top20/ s cl0 100 p 33 /rxda1 54 p100/tip00/tip11/top00/top11 33 p04/intp4 1 avref 70 p21/tig02/tog02/ s cl1 64 vdd51 45 v ss 50 75 p26/tig1 3 /tog1 3 104 p106/ s ob0 9 s mv ss 50 16 p122/ s m5 3 21 p127/ s m64 109 p92/ s ckb1/dbd2 3 0 p1 3 6/tig1 3 / s m4 3 /tog1 3 5 3 p101/tip01/tip10/top01/top10 47 p50/intp7/fout/ s goa 115 dvdd50 114 p97/dbd7 51 p10 3 /tip21/tip 3 0/top21/top 3 0 90 bv ss 51 40 p54/dck 88 p67/tig2 3 /tip 3 1/tog2 3 /top 3 1 12 8 vcmp1 77 p 3 4/tig21/tog21/top01 126 p07/intp6/vcmpo0/vcmpo1/flmd1 71 p22/tig0 3 /tog0 3 96 p 8 1/ s ob2 5 p111/ s m12/tog22 57 p42/ s ckb0 61 p47/ctxd0 12 p116/ s m2 3 19 p125/ s m62 24 p1 3 2/tig0 3 / s m 33 /tog0 3 112 p95/ s ob2/dbd5 62 p 3 1/rxda0/ s cl1 8 4 p6 3 /tig24/tip11/tog24/top11 102 p 3 2/txda1 8 0 60 p46/crxd0 3 4 p0 3 /intp 3 69 p20/tig01/tog01/ s da1 4 3 vdd50 26 s mvdd51 74 p25/tig12/tog12 105 p105/ s ib0/dbwr 41 p5 3 /ddo 124 xt1 15 p121/ s m52 20 p126/ s m6 3 10 8 p91/ s ob1/dbd1 29 p1 3 5/tig12/ s m42/tog12 8 9 bvdd51 144 p70/ain0 50 bv ss 50 11 3 p96/ s ck2/dbd6 52 p102/tip20/tip 3 1/top20/top 3 1 8 2 p61/tig21/tip01/tog21/top01 1 3 4 p710/ain10 125 xt2 8 7 p66/tig22/tip21/tog22/top21 127 vcmp0 3 6 p01/intp1 3 2 p06/intp5 3 av ss 59 p57/txda1/ctxd1 14 3 p71/ain1 1 33 p711/ain11 119 v ss 52 97 p 8 0/ s ib2 4 p110/ s m11/tog21 12 3 re s et 11 p115/ s m22/ s goa 1 8 p124/ s m61 2 3 p1 3 1/tig02/ s m 3 2/tog02 111 p94/ s ib2/dbd4 142 p72/ain2 1 3 2 p712/ain12 9 8 p 8 5/fout 83 p62/tig25/tip10/top10 42 p52/ddi 99 p 8 7/rxda0 79 141 p7 3 /ain 3 3 5 p02/intp2 6 8 p17/ s cl0/crxd2 2 avdd 1 3 1 p71 3 /ain1 3 11 8 regc2 8 s mvdd50 106 p104/dbrd 7 3 p24/tig11/tog11 94 7 p11 3 / s m14/tog24 14 p120/ s m51 140 p74/ain4 107 p90/ s ib1/dbd0 2 8 p1 3 4/tig11/ s m41/tog11 1 3 0 p714/ain14 5 8 p56/rxda1/crxd1 121 x1 49 bvdd50 44 regc0 46 p 8 4/intp7/toy0 8 1 p60/tig20/tip00/top00 91 p45/ s ckb1 8 6 p65/tip 3 0/top 3 0/ s da0 3 7 p00/intp0/nmi 1 3 9 p75/ain5 129 p715/ain15 38 p05/dr s t 122 x2 117 vdd52 66 v ss 51 76 p27/tig14/tog14 10 3 p107/ s ckb0 27 s mv ss 51 10 p114/ s m21/ s go 4 8 p51/ s go 17 p12 3 / s m54 1 38 p76/ain6 92 p44/ s ob1 22 p1 3 0/tig01/ s m 3 1/tog01 110 p9 3 /dbd 3 3 1 p1 3 7/tig14/ s m44/tog14 116 dv ss 50 56 p41/ s ob0 101 p 8 6/txda0 1 3 7 p77/ain7 120 flmd0 7 8 67 p16/ s da0/ctxd2 65 regc1 9 3 p4 3 / s ib1 3 9 p55/dm s 72 p2 3 /tig04/tog04 95 p 8 2/ s ckb2 6 p112/ s m1 3 /tog2 3 1 3 6 p7 8 /ain 8 1 3 p117/ s m24 25 p1 33 /tig04/ s m 3 4/tog04 p 83 /toy0/fout p 3 7/tig24/tog24/top11 p 3 6/tig2 3 /tog2 3 /top 3 1 p 3 5/tig22/tog22/top21 note note
112 chapter 2 pin functions user?s manual u17566ee5v1um00 2.8.3 pd70f3427 figure 2-9 pin overview of pd70f3427 v 8 50e/dl 3 pd70f 3 427 2 8 p1 3 4/tig11/ s m41/tog11 9 3 a4 19 3 p715/ain15 3 9 p92/ s ckb1/dbd2/d26 101 mvdd5 3 51 p 8 6/txda0/d16 74 mvdd51 3 6 dvdd50 1 8 9 xt2 165 bvdd51 11 p115/ s m22/ s goa 12 3 p02/intp2 159 p 3 4/tig21/tog21/top01 62 regc0 4 8 dv ss 51 11 8 a22 110 a16 14 p120/ s m51 27 s mv ss 51 1 38 p101/tip01/tip10/top01/top10 65 67 8 4 d1 3 55 be0 9 8 vdd51 156 p25/tig12/tog12 10 3 a9 41 p90/ s ib1/dbd0/d24 169 p64/tip20/top20/ s cl0 144 p57/ctxd1/txda1 8 2 d11 75 mv ss 51 5 p111/ s m12/tog22 167 p62/tig25/tip10/top10 46 p 33 /rxda1/d19 111 a17 33 p96/ s ckb2/dbd6/d 3 0 1 3 6 p10 3 /tip21/tip 3 0/top21/top 3 0 3 1 p1 3 7/tig14/ s m44/tog14 6 8 20 3 p75/ain5 3 7 dv ss 50 3 4 p95/ s ob2/dbd5/d29 200 p7 8 /ain 8 145 p46/crxd0 7 8 d7 16 p122/ s m5 3 8 0 d9 204 p74/ain4 8 s mvdd50 15 p121/ s m52 94 a5 177 p 8 2/ s ckb2 1 8 6 x2 199 p79/ain9 40 p91/ s ob1/dbd1/d25 26 s mvdd51 191 vcmp0 196 p712/ain12 54 172 p67/tig2 3 /tip 3 1/tog2 3 /top 3 1 206 p72/ain2 3 0 p1 3 6/tig1 3 / s m4 3 /tog1 3 14 8 p 3 0/txda0/ s da1 76 d5 1 8 2 regc2 5 8 p140/bclk 141 p41/ s ob0 154 p2 3 /tig04/tog04 164 p61/tig21/tip01/tog21/top01 97 a 8 117 a21 171 p66/tig22/tip21/tog22/top21 91 a2 202 p76/ain6 61 vdd50 1 3 1 p 8 4/intp7/toy0 121 p04/intp4 192 vcmp1 100 v ss 51 122 p0 3 /intp 3 64 195 p71 3 /ain1 3 1 avref 1 3 p117/ s m24 90 a1 166 bv ss 51 152 p21/tig02/tog02/ s cl1 162 p 3 7/tig24/tog24/top11 1 8 p124/ s m61 106 a12 1 8 0 p 8 5/fout 4 p110/ s m11/tog21 161 p 3 6/tig2 3 /tog2 3 /top 3 1 20 p126/ s m6 3 114 mv ss 54 16 3 p60/tig20/tip00/top00 6 3 v ss 50 25 p1 33 /tig04/ s m 3 4/tog04 50 p 8 7/rxda0/d17 8 9 a0 7 p11 3 / s m14/tog24 70 d1 10 p114/ s m21/ s go 8 1 d10 115 a19 6 p112/ s m1 3 /tog2 3 92 a 3 88 d15 8 6 mvdd52 1 3 0 p52/ddi 126 49 p 3 2/txda1/d1 8 1 33 p51/ s go 140 p40/intp6/ s ib0 119 a2 3 125 p00/intp0/nmi 57 1 8 1 vdd52 201 p77/ain7 104 a10 1 3 4 bvdd50 29 p1 3 5/tig12/ s m42/tog12 7 3 d4 1 3 2 p50/intp7/fout/ s goa 10 8 a14 170 p65/tip 3 0/top 3 0/ s da0 83 d12 197 p711/ain11 179 p 8 0/ s ib2 71 d2 4 3 p106/ s ob0/d22 8 5 d14 19 8 p710/ain10 3 5 p94/ s ib2/dbd4/d2 8 17 3 p45/ s ckb1 9 s mv ss 50 102 mv ss 5 3 150 p17/ s cl0/crxd2 176 21 p127/ s m64 1 3 9 p100/tip00/tip11/top00/top11 1 8 7 11 3 mvdd54 16 8 p6 3 /tig24/tip11/tog24/top11 112 a1 8 194 p714/ain14 175 p4 3 / s ib1 14 3 p56/crxd1/rxda1 109 a15 59 mvdd50 99 regc1 3 2 p97/dbd7/d 3 1 19 p125/ s m62 5 3 69 d0 116 a20 142 p42/ s ckb0 95 a6 1 88 xt1 105 a11 79 d 8 24 p1 3 2/tig0 3 / s m 33 /tog0 3 190 p07/intp6/vcmpo0/vcmpo1/flmd1 44 149 p16/ s da0/ctxd2 127 p55/dm s 1 3 7 p102/tip21/tip 3 1/top20/top 3 1 47 dvdd51 107 a1 3 42 p107/ s ckb0/d2 3 120 p06/intp5 155 p24/tig11/tog11 1 83 v ss 52 12 p116/ s m2 3 15 8 p27/tig14/tog14 157 p26/tig1 3 /tog1 3 2 3 p1 3 1/tig02/ s m 3 2/tog02 207 p71/ain1 72 d 3 151 p20/tig01/tog01/ s da1 96 a7 160 p 3 5/tig22/tog22/top21 174 p44/ s ob1 60 mv ss 50 124 p01/intp1 8 7 mv ss 52 45 56 17 8 p 8 1/ s ob2 12 8 p54/dck 1 3 5 bv ss 50 205 p7 3 /ain 3 17 p12 3 / s m54 147 p 3 1/rxda0/ s cl1 1 8 5 x1 66 77 d6 52 22 p1 3 0/tig01/ s m 3 1/tog01 129 p5 3 /ddo 3 av ss 38 p9 3 /dbd 3 /d27 1 8 4 flmd0 2 avdd 15 3 p22/tig0 3 /tog0 3 146 p47/ctxd0 20 8 p70/ain0 re s et p104/dbrd/d20 p105/ s ib0/dbwr/d21 rd wr be1 p141/be2 p142/be 3 c s 0 p05/dr s t wait c s 1 c s 4 c s3 p 83 /toy0/fout
113 user?s manual u17566ee5v1um00 chapter 3 cpu system functions this chapter describes the registers of the cpu, the operation modes, the address space and the memory areas. 3.1 overview the cpu is founded on harvard architecture and it supports a risc instruction set. basic instructions can be executed in one clock period. optimized five- stage pipelining is supported. this improves instruction execution speed. in order to make the microcontroller ideal for use in digital control applications, a 32-bit hardware multiplier enables this cpu to support multiply instructions, saturated multiply instructions, bit operation instructions, etc. features summary the cpu has the following special features: ? memory space: ? 64 mb linear program space ? 4 gb linear data space ? 32 general purpose registers ? internal 32-bit architecture ? five-stage pipeline ? efficient multiplication and division instructions ? saturation logic (saturated operation instructions) ? barrel shifter (32-bit shift in one clock cycle) ? instruction formats: long and short ? four types of bit manipulation instructions: set, clear, not, test
114 chapter 3 cpu system functions user?s manual u17566ee5v1um00 3.1.1 description the figure below shows a block diagram of the microcontroller, focusing on the cpu and modules that interact with the cpu directly. ta bl e 3 - 1 lists the bus types. figure 3-1 cpu system the shaded busses are used for accessing the configuration registers of the concerned modules. progr a m co u nter gener a l-p u rpo s e regi s ter s m u ltiplier ( 3 2 3 2  64) alu b a rrel s hifter cpu v s b dma control u nit (dmac) s y s tem controller b us b ridge (bbr) in s tr u ction qu e u e b us control u nit (bcu) npb v d b v f b s y s tem regi s ter s rcu interf a ce s t a nd b y control u nit ( s tbc) interr u pt control u nit (intc) table 3-1 bus types bus type function npb ? nec peripheral bus bus interface to the peripherals (internal bus).
115 cpu system functions chapter 3 user?s manual u17566ee5v1um00 3.2 cpu register set there are two categories of registers: ? general purpose registers ? system registers all registers are 32-bit registers. an overview is given in the figure below. for details, refer to v850e1 user?s manual architecture. figure 3-2 cpu register set vsb ? v850 system bus bus interface to the memory controller for access to external memory, additional internal memory and to the npb bus bridge bbr. vfb ? v850 fetch bus interface to the internal flash. vdb ? v850 data bus interface to the internal ram. table 3-1 bus types bus type function r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r1 0 r1 1 r1 2 r1 3 r1 4 r1 5 r1 6 r1 7 r1 8 r1 9 r2 0 r2 1 r2 2 r2 3 r2 4 r2 5 r2 6 r2 7 r2 8 r2 9 r3 0 r3 1 31 0 31 0 (zero register) (reserved for assembler) (interrupt stack pointer) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) (program counter) pc (callt base pointer) ctbp (status saving register during exception/debug trap) dbpsw (status saving register during exception/debug trap) dbpc (status saving register during callt execution) ctpsw (status saving register during callt execution) ctpc (program status word) psw (interrupt/execution source register) ecr (status saving register during nmi) fepsw (status saving register during nmi) fepc (status saving register during interrupt) eipsw (status saving register during interrupt) eipc
116 chapter 3 cpu system functions user?s manual u17566ee5v1um00 some registers are write protected. that means, writing to those registers is protected by a special sequence of instructions. refer to ?write protected registers? on page 135 for more details.
117 cpu system functions chapter 3 user?s manual u17566ee5v1um00 3.2.1 general purpose registers (r0 to r31) each of the 32 general purpose registers can be used as a data variable or address variable. however, the registers r0, r1, r3 to r5, r30, and r31 may implicitly be used by the assembler/compiler (see table ta b l e 3 - 2 ). for details refer to the documentation of your assembler/compiler. caution before using registers r1, r3 to r5, r30, and r31, their contents must be saved so that they are not lost. the contents must be restored to the registers after the registers have been used. table 3-2 general purpose registers register name usage operation r0 zero register always holds 0. it is used for operations using 0 and offset 0 addressing. a a) registers r0 and r30 are used by dedicated instructions. r1 assembler-reserved register used for 32-bit direct addressing. b b) registers r1, r3, r4, r5, and r31 may be used by the assembler/compiler. r2 user address/data variable register r3 stack pointer (sp) used to generate stack frame when function is called. b r4 global pointer (gp) used to access global variable in data area. b r5 text pointer (tp) used to indicate the start of the text area (where program code is located). b r6 to r29 user address/data variable registers r30 element pointer (ep) base pointer when memory is accessed by means of instructions sld (short format load) and sst (short format store). a r31 link pointer (lp) used when calling a function. b
118 chapter 3 cpu system functions user?s manual u17566ee5v1um00 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. additionally, the program counter holds the instruction address during program execution. to read/write the system registers, use instructions ldsr (load to system register) or stsr (store contents of system register), respectively, with a specific system register number (regid) indicated below. the program counter states an exception. it cannot be accessed via ldsr or stsr instructions. no regid is allocated to the program counter. example stsr 0, r2 stores the contents of system register 0 (eipc) in general purpose register r2. system register numbers the table below gives an overview of all system registers and their system register number (regid). it shows whether a load/store instruction is allowed ( ) for the register or not ( ? ). table 3-3 system register numbers regid system register name shortcut operand specification ldsr stsr 0 status saving register during interrupt (stores contents of pc) eipc 1 status saving register during interrupt (stores contents of psw) eipsw 2 status saving register during non-maskable interrupts (stores contents of pc) fepc 3 status saving register during non-maskable interrupts (stores contents of psw) fepsw 4 interrupt source register ecr ? 5 program status word psw 6 to 15 reserved (operations that access these register numbers cannot be guaranteed). ?? 16 status saving register during callt execution (stores contents of pc) ctpc 17 status saving register during callt execution (stores contents of psw) ctpsw 18 status saving register during exception/debug trap (stores contents of pc) dbpc a a) reading from this register is only enabled between a dbtrap exception (exception handler address 0000 0060 h ) and the exception handler terminating dbret instruction. dbtrap exceptions are generated upon ilgop and rom correction detections (refer to ?interrupt controller (intc)? on page 201 and ?rom correction function (romc)? on page 375 ). 19 status saving register during exception/debug trap (stores contents of psw) dbpsw a 20 callt base pointer ctbp 21 to 31 reserved (operations that access these register numbers cannot be guaranteed). ??
119 cpu system functions chapter 3 user?s manual u17566ee5v1um00 (1) pc - program counter the program counter holds the instruction address during program execution. the lower 26 bits are valid, and bits 31 to 26 are fixed to 0. if a carry occurs from bit 25 to 26, it is ignored. branching to an odd address cannot be performed. bit 0 is fixed to 0. access this register can not be accessed by any instruction. initial value 0000 0000 h . the program counter is cleared by any reset. (2) eipc, fepc, dbpc, ctpc - pc saving registers the pc saving registers save the contents of the program counter for different occasions, see ta b l e 3 - 4 . when one of the occasions listed in ta bl e 3 - 4 occurs, except for some instructions, the address of the instruction following the one being executed is saved to the saving registers. for more details refer to table 3-9 on page 123 and to the ?interrupt controller (intc)? on page 201 . all pc saving registers are built up as the pc, with the initial value 0xxx xxxx h (x = undefined). note when multiple interrupt servicing is enabled, the contents of eipc or fepc must be saved by program?because only one pc saving register for maskable interrupts and non-maskable interrupts is provided, respectively. caution when setting the value of any of the pc saving registers, use even values (bit 0 = 0). if bit 0 is set to 1, the setting of this bit is ignored. this is because bit 0 of the program counter is fixed to 0. 31 26 25 1 0 fixed to 0 instruction address during execution 0 table 3-4 pc saving registers register shortcut saves contents of pc in case of status saving register during interrupt eipc ? software exception ? maskable interrupt status saving register during non-maskable interrupts fepc ? non-maskable interrupt status saving register during exception/debug trap dbpc a a) reading from this register is only enabled between a dbtrap exception (excep- tion handler address 0000 0060 h ) and the exception handler terminating dbret instruction. dbtrap exceptions are generated upon ilgop and rom correction detections (refer to ?interrupt controller (intc)? on page 201 and ?rom correction function (romc)? on page 375 ). ? exception trap ? debug trap ? debug break ? during a single-step operation status saving register during callt execution ctpc ? execution of callt instruction
120 chapter 3 cpu system functions user?s manual u17566ee5v1um00 (3) psw - program status word the 32-bit program status word is a collection of flags that indicates the status of the program (result of instruction execution) and the status of the cpu. if the bits in the register are modified by the ldsr instruction, the psw will take on the new value immediately after the ldsr instruction has been executed. initial value 0000 0020 h . the program status is initialized by any reset. 31 876543210 fixed to 0 np ep id sat cy ov s z r r r/w r/w r/w r/w r/w r/w r/w r/w table 3-5 psw register contents bit position flag function 7 np indicates that non-maskable interrupt (nmi) servicing is in progress. this flag is set when nmi request is acknowledged, and multiple interrupt servicing is disabled. 0: nmi servicing is not in progress. 1: nmi servicing is in progress. 6 ep indicates that exception processing is in progress. this flag is set when an exception occurs. even when this bit is set, interrupt requests can be acknowledged. 0: exception processing is not in progress. 1: exception processing is in progress. 5 id indicates whether a maskable interrupt request can be acknowledged. 0: interrupts enabled. 1: interrupts disabled. note: setting this flag will disable interrupt requests even while the ldsr instruction is being executed. 4sat a for saturated operation processing instructions only: indicates that the operation result is saturated due to overflow. 0: not saturated. 1: saturated. note: 1. this is a cumulative flag: the bit is not automatically cleared if subsequent instructions lead to not saturated results. to clear this bit, use the ldsr instruction to set psw.sat = 0. 2. in a general arithmetic operation this bit is neglected. it is neither set nor cleared. 3 cy carry/borrow flag. indicates whether a carry or borrow occurred as a result of the operation. 0: carry or borrow did not occur 1: carry or borrow occurred. 2ov a overflow flag. indicates whether an overflow occurred as a result of the operation. 0: overflow did not occur. 1: overflow occurred. 1s a sign flag. indicates whether the result of the operation is negative. 0: result is positive or zero. 1: result is negative. 0 z zero flag. indicates whether the result of the operation is zero. 0: result is not zero. 1: result is zero.
121 cpu system functions chapter 3 user?s manual u17566ee5v1um00 saturated operation instructions the following table shows the setting of flags pws.sat, pws.ov, and pws.s, depending on the status of the operation result. a) in the case of saturate instructions, the sat, s, and ov flags will be set according to the result of the operation as shown in the table below. note that the sat flag is set only when the ov flag has been set during a satu- rated operation. table 3-6 saturation-processed operation result status of operation result flag status saturation-processed operation result sat ov s maximum positive value exceeded 1 1 0 7fff ffff h maximum negative value exceeded 1 1 1 8000 0000 h positive (maximum not exceeded) x a a) retains the value before operation. 0 0 operation result itself negative (maximum not exceeded) 1
122 chapter 3 cpu system functions user?s manual u17566ee5v1um00 (4) eipsw, fepsw, dbpsw, ctpswpsw saving registers the psw saving registers save the contents of the program status word for different occasions, see ta bl e 3 - 4 . when one of the occasions listed in ta bl e 3 - 4 occurs, the current value of the psw is saved to the saving registers. all psw saving registers are built up as the psw, with the initial value 0000 0xxx h (x = undefined). note when multiple interrupt servicing is enabled, the contents of eipsw or fepsw must be saved by program?because only one psw saving register for maskable interrupts and non-maskable interrupts is provided, respectively. caution bits 31 to 26 of eipc and bits 31 to 12 and 10 to 8 of eipsw are reserved for future function expansion (fixed to 0).when setting the value of eipc, fepc, or ctpc, use even values (bit 0 = 0). if bit 0 is set to 1, the setting of this bit is ignored. this is because bit 0 of the program counter is fixed to 0. table 3-7 psw saving registers register shortcut saves contents of psw in case of status saving register during interrupt eipsw ? software exception ? maskable interrupt status saving register during non-maskable interrupts fepsw ? non-maskable interrupt status saving register during exception/debug trap dbpsw a a) reading from this register is only enabled between a dbtrap exception (excep- tion handler address 0000 0060 h ) and the exception handler terminating dbret instruction. dbtrap exceptions are generated upon ilgop and rom correction detections (refer to ?interrupt controller (intc)? on page 201 and ?rom correction function (romc)? on page 375 ). ? exception trap ? debug trap ? debug break ? during a single-step operation status saving register during callt execution ctpsw ? execution of callt instruction
123 cpu system functions chapter 3 user?s manual u17566ee5v1um00 (5) ecr - interrupt/exception source register the 32-bit ecr register displays the exception codes if an exception or an interrupt has occurred. with the exception code, the interrupt/exception source can be identified. for a list of interrupts/exceptions and corresponding exception codes, see table 3-9 on page 123 . initial value 0000 0000 h . this register is cleared by any reset. the following table lists the exception codes. if an interrupt (maskable or non-maskable) is acknowledged during instruction execution, generally, the address of the instruction following the one being executed is saved to the saving registers, except when an interrupt is acknowledged during execution of one of the following instructions: ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? divide instructions (div, divh, divu, divhu) 31 26 25 0 fecc eicc table 3-8 ecr register contents bit position bit name function 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupts table 3-9 interrupt/execution codes interrupt/exception source classification exception code handler address value restored to eipc/fepc name trigg er non-maskable interrupts (nmi) nmi0 input interrupt 0010 h 0000 0010 h next pc (see note) nmi1 input interrupt 0020 h 0000 0020 h next pc (see note) nmi2 input interrupt 0030 h 0000 0030 h next pc (see note) maskable interrupt refer to ?interrupt controller (intc)? on page 201 interrupt refer to ?interrupt controller (intc)? on page 201 ? higher 16 bits: 0000 h ? lower 16 bits: exception code next pc (see note) software exception trap0n (n = 0 to f h ) trap instruction exception 004n h 0000 0040 h next pc trap1n (n = 0 to f h ) trap instruction exception 005n h 0000 0050 h next pc exception trap (ilgop) illegal instruction code exception 0060 h 0000 0060 h next pc debug trap dbtrap instruction exception 0060 h 0000 0060 h next pc
124 chapter 3 cpu system functions user?s manual u17566ee5v1um00 ? prepare, dispose instruction (only if an interrupt is generated before the stack pointer is updated) in this case, the address of the interrupted instruction is restored to the eipc or fepc, respectively. execution is stopped, and after the completion of interrupt servicing the execution is resumed. (6) ctbp - callt base pointer the 32-bit callt base pointer is used with the callt instruction. the register content is used as a base address to generate both a 32-bit table entry address and a 32-bit target address. initial value undefined 31 30 29 28 27 26 25 1 0 0 0 0 0 0 0 base address 0 r a r a r a r a r a r a r/w r a) these bits may be written, but write is ignored.
125 cpu system functions chapter 3 user?s manual u17566ee5v1um00 3.3 operation modes this section describes the operation modes of the cpu and how the modes are specified. the following operation modes are available: ? normal operation mode ? flash programming mode after reset release, the microcontroller starts to fetch instructions from an internal boot rom which contains the internal firmware. the firmware checks the flmd0 pin, and optionally also the flmd1 pin, to set the operation mode after reset release according to ta b l e 3 - 1 0 . note the flmd1 pin function is shared with the p07 pin. 3.3.1 normal operation mode in normal operation mode, the internal flash memory is not re-programmed. after reset release, the firmware acquires the user's reset vector from the flash memory. the reset vector contains the start address of the user?s program code. the firmware branches to that address. program execution is started. table 3-10 selection of operation modes pins operation mode flmd0 flmd1 (p07) 0 x normal operation mode (fetch from flash) 1 0 flash programming mode 1 setting prohibited
126 chapter 3 cpu system functions user?s manual u17566ee5v1um00 3.3.2 flash programming mode in flash programming mode, the internal flash memory is erased and re-programmed. after reset release, the firmware initiates loading of the user's program code from the external flash programmer and programs the flash memory. after detaching the external flash programmer, the microcontroller can be started up with the new user's program in normal operation mode. for more information see section ?flash memory? on page 269 . 3.4 address space in the following sections, the address space of the cpu is explained. size and addresses of cpu address space and physical address space are explained. the address range of data space and program space together with their wrap- around properties are presented. 3.4.1 cpu address space and physical address space the cpu supports the following address space: ? 4 gb cpu address space with the 32-bit general purpose registers, addresses for a 4 gb memory can be generated. this is the maximum address space supported by the cpu. ? 64 mb physical address space the cpu provides 64 mb physical address space. that means that a maximum of 64 mb internal or external memory can be accessed. any 32-bit address is translated to its corresponding physical address by ignoring bits 31 to 26 of the address. thus, 64 addresses point to the same physical memory address. in other words, data at the physical address 0000 0000 h can additionally be accessed by addresses 0400 0000 h , 0800 0000 h , ?, f800 0000 h , or fc00 0000 h . the 64 mb physical address space is seen as 64 images in the 4 gb cpu address space:
127 cpu system functions chapter 3 user?s manual u17566ee5v1um00 figure 3-3 images in the cpu address space ffff ffffh fc00 0000h fbff ffffh 0000 0000h im a ge im a ge im a ge peripher a l i/o phy s ic a l a ddre ss s p a ce x3ff ffffh x000 0000h im a ge im a ge f800 0000h f7ff ffffh 0800 0000h 07ff ffffh 0400 0000h 03ff ffffh cpu a ddre ss s p a ce x3ff f000h x3ff 0000h vfb fl as h/rom v s b a re a (fl as h, ram extern a l memory) vdb ram
128 chapter 3 cpu system functions user?s manual u17566ee5v1um00 3.4.2 program and data space the cpu allows the following assignment of data and instructions to the cpu address space: ? 4 gb as data space the entire cpu address space can be used for operand addresses. ? 64 mb as program space only the lower 64 mb of the cpu address space can be used for instruction addresses. when an instruction address for a branch instruction is calculated and moved to the program counter (pc), then bits 31 to 26 are set to zero. figure 3-4 shows the assignment of the cpu address space to data and program space. figure 3-4 cpu address space ffff ffffh 0400 0000h 03ff ffffh 0000 0000h d a t a a re a (4 gb line a r) progr a m a re a (64 mb line a r) cpu a ddre ss s p a ce
129 cpu system functions chapter 3 user?s manual u17566ee5v1um00 (1) wrap-around of data space if an operand address calculation exceeds 32 bits, only the lower 32 bits of the result are considered. therefore, the addresses 0000 0000 h and ffff ffff h are contiguous addresses. this results in a wrap-around of the data space: figure 3-5 wrap-around of data space (2) wrap-around of program space if an instruction address calculation exceeds 26 bits, only the lower 26 bits of the result are considered. therefore, the addresses 0000 0000 h and 03ff ffff h are contiguous addresses. this results in a wrap-around of the program space: figure 3-6 wrap-around of program space caution no instruction can be fetched from the 4 kb area of 03ff f000 h to 03ff ffff h because this area is defined as peripheral i/o area. therefore, do not execute any branch to this area. ffff fffeh ffff ffffh 0000 0000h 0000 0001h d a t a s p a ce d a t a s p a ce (-) direction (+) direction 03ff fffeh 03ff ffffh 0000 0000h 0000 0001h progr a m s p a ce progr a m s p a ce (-) direction (+) direction
130 chapter 3 cpu system functions user?s manual u17566ee5v1um00 3.5 memory in the following sections, the memory of the cpu is introduced. specific memory areas are described and a recommendation for the usage of the address space is given. 3.5.1 memory areas the internal memory of the cpu provides several areas: ? internal vfb flash area ? internal vdb ram area ? internal vsb flash area ? internal vsb ram area ? external memory area ? internal fixed peripheral i/o area ? programmable peripheral i/o area the areas are briefly described below. (1) internal vfb flash areas ta b l e 3 - 1 1 summarizes the size and addresses of the flash memories, which are accessible via the vfb (v850 fetch bus). (2) internal vdb ram area after reset the internal vdb ram consists of several separated ram blocks. if a reset occurs while writing to one ram block, only the contents of that ram block may be corrupted. the contents of the other ram blocks remain unaffected. ta b l e 3 - 1 2 summarizes the vdb (v850 data bus) ram blocks compilation and their address assignment. table 3-11 vfb flash memory device flash address range pd70f3421 256 kb 0000 0000 h to 0003 ffff h pd70f3422 384 kb 0000 0000 h to 0005 ffff h pd70f3423 512 kb 0000 0000 h to 0007 ffff h pd70f3424 512 kb 0000 0000 h to 0007 ffff h pd70f3425 1 mb 0000 0000 h to 000f ffff h pd70f3426a 1 mb 0000 0000 h to 000f ffff h pd70f3427 1 mb 0000 0000 h to 000f ffff h table 3-12 internal vdb ram areas (1/2) device ram size block number size address pd70f3421 12 kb 0 4 kb 03ff 0000 h ? 03ff 0fff h 1 8 kb 03ff 1000 h ? 03ff 2fff h
131 cpu system functions chapter 3 user?s manual u17566ee5v1um00 note that the internal firmware, which is processed after reset, uses some ram (refer to ?general reset performance? on page 954 ). (3) internal vsb flash area (pd70f3426a only) the pd70f3426a provides additional flash memory, accessible via the vsb (v850 system bus). (4) internal vsb ram area (pd70f3426a only) the pd70f3426a provides additional ram, accessible via the vsb (v850 system bus). (5) external memory area (pd70f3427 only) all address areas that do not address any internal memory or peripheral i/o registers can be used as external memory area. pd70f3422 16 kb 0 8 kb 03ff 0000 h ? 03ff 1fff h 1 8 kb 03ff 2000 h ? 03ff 3fff h pd70f3423 20 kb 0 8 kb 03ff 0000 h ? 03ff 1fff h 1 8 kb 03ff 2000 h ? 03ff 3fff h 2 4 kb 03ff 4000 h ? 03ff 4fff h pd70f3424 24 kb 0 8 kb 03ff 0000 h ? 03ff 1fff h 1 8 kb 03ff 2000 h ? 03ff 3fff h 2 8 kb 03ff 4000 h ? 03ff 5fff h pd70f3425 a 32 kb 0 16 kb 03ff 0000 h ? 03ff 3fff h 1 16 kb 03ff 4000 h ? 03ff 7fff h pd70f3426a pd70f3427 60 kb 0 16 kb 03ff 0000 h ? 03ff 3fff h 1 16 kb 03ff 4000 h ? 03ff 7fff h 2 16 kb 03ff 8000 h ? 03ff bfff h 3 12 kb 03ff c000 h ? 03ff efff h a) the pd70f3425?s 32 kb ram area 03ff 0000 h to 03ff 7fff h is mirrored to the subsequent area 03ff 8000 h to 03ff ffff h . since the upper 4 kb 03ff f000 h to 03ff ffff h is used to access the fixed peripheral i/o area, the ram mirror must not be used to access the ram. table 3-12 internal vdb ram areas (2/2) device ram size block number size address table 3-13 internal vsb flash memory device flash size address range pd70f3426a 1 mb 0010 0000 h to 001f ffff h table 3-14 internal vsb ram device ram size block number size address pd70f3426a 24 kb 0 12 kb 0060 0000 h ?00602fff h 1 12 kb 0060 3000 h ?00605fff h
132 chapter 3 cpu system functions user?s manual u17566ee5v1um00 access to the external memory area uses the chip select (cs) signals assigned to each memory area. for access to external memory, see ?bus and memory control (bcu, memc)? on page 289 . 3.5.2 fixed peripheral i/o area the 4 kb area between addresses 03ff f000 h and 03ff ffff h is provided as the fixed peripheral i/o area. accesses to these addresses are passed over to the npb bus (internal bus). the following registers are memory-mapped to the peripheral i/o area: ? all registers of peripheral functions ? registers of timers ? configuration registers of interrupt, dma, bus and memory controllers ? configuration registers of the clock controller for a list of all peripheral i/o registers, see ?special function registers? on page 997 . note 1. because the physical address space covers 64 mb, the address bits a[31:26] are not considered. thus, this address space can also be addressed via the area ffff 0000 h to ffff ffff h . this has the advantage that the area can be indirectly addressed by an offset and the zero base r0. therefore, in this manual, all addresses of peripheral i/o registers in the 4 kb peripheral i/o area are given in the range ffff f000 h to ffff ffff h instead of 03ff f000 h to 03ff ffff h . 2. the fixed peripheral i/o area is mirrored to the upper 4 kb of the programmable peripheral i/o area ppa - regardless of the base address of the ppa. if data is written to one area, it appears also in the other area. 3. program fetches cannot be executed from any peripheral i/o area. 4. word registers, that means 32-bit registers, are accessed in two half word accesses. the lower two address bits are ignored. 5. for registers in which byte access is possible, if half word access is executed: ? during read operation: the higher 8 bits become undefined. ? during write operation: the lower 8 bits of data are written to the register. caution 1. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. 2. for dma transfer, the fixed peripheral i/o area 03ff f000 h to 03ff ffff h cannot be specified as the source/destination address. be sure to use the ram area 0fff f000 h to 0fff ffff h for source/destination address of dma transfer.
133 cpu system functions chapter 3 user?s manual u17566ee5v1um00 (1) programmable peripheral i/o area a 16 kb area is provided as a programmable peripheral i/o area (ppa). the ppa can be freely located. the base address of the programmable peripheral i/o area is specified by the initialization of the peripheral area selection control register (bpc). see ?bus and memory control (bcu, memc)? on page 289 for details.
134 chapter 3 cpu system functions user?s manual u17566ee5v1um00 3.5.3 recommended use of data address space when accessing operand data in the data space, one register has to be used for address generation. this register is called pointer register. with relative addressing, an instruction can access operand data at all addresses that lie in the range of 32 kb relative to the address in the pointer register. by this offset addressing method load/store instructions can be accommodated in a single 32-bit instruction word, resulting in faster program execution and smaller code size. to enhance the efficiency of using the pointer in consideration of the memory map, the following is recommended: for efficient use of the relative addressing feature, the data segments should be located in the address range ffff f800 h to 0000 0000 h and 0000 0000 h to 0000 7fff h . the peripheral i/o registers and the internal ram is aligned to the upper bound, thus the registers and a part of the ram can be addressed via relative addressing, with base address 0 (r0). it is recommended to locate flash memory data segments in the area up to 0000 7fff h , so access to these constant data can utilize also relative addressing. use the r0 register as pointer register for operand addressing. since the r0 register is fixed to zero by hardware, it can be used as a pointer register and, at the same time, for any other purposes, where a zero register is required. thus, no other general purpose register has to be reserved as pointer register. figure 3-7 example application of wrap-around 0000 7fffh (r0=)0000 0000h intern a l fl as h a re a fixed peripher a l i/o a re a ffff f000h ffff efffh ffff 8000h intern a l ram a re a (4 kb) (2 8 kb) (1 mb) intern a l ram a re a ( 3 2 kb) ffff 0000h ffff 7fffh - 3 2 kb + 3 2 kb
135 cpu system functions chapter 3 user?s manual u17566ee5v1um00 3.6 write protected registers write protected registers are protected from inadvertent write access due to erroneous program execution, etc. write access to a write protected register is only given immediately after writing to a corresponding write enable register. for a write access to the write protected registers you have to use the following instructions: 1. store instruction (st/sst instruction) 2. bit operation instruction (set1/clr1/not1 instruction) when reading write protected registers, no special sequence is required. the following table gives an overview of the write protected registers and their corresponding write enable registers. for some registers, incorrect store operations can be checked by a flag of the corresponding status register. this is also marked in the table below. example start the watchdog timer the following example shows how to write to the write protected register wdtm. the example starts the watchdog timer. do { _wpr e rr = 0; di(); wcmd = 0 x 5a; wdtm = 0 x 80; e i(); } while (_wpr e rr != 0) note 1. make sure that the compiler generates two consecutive assembler ?store? instructions to wcmd and wdtm from the associated c statements. 2. special care must be taken when writing to registers pcs and prcmd. please refer to ?clock generator? on page 139 for details. since any action between writing to a write enable register and writing to a protected register destroys this sequence, the effects of interrupts and dma transfers have to be considered: interrupts in order to prevent any maskable interrupt to be acknowledged between the two write instructions in question, shield this sequence by di - ei (disable interrupt - enable interrupt). however, any non-maskable interrupt can still be acknowledged. dma in the above example, dma transfers can still take place. they may destroy the sequence. if appropriate, you may disable dma transfers in advance. otherwise you must check whether writing to the protected register was successful. to do so, check the status via the status register, if available, or by reading back the protected register. the above examples checks wphs.wprerr for that purposes and repeats the sequence until the write to wdtm was successful.
136 chapter 3 cpu system functions user?s manual u17566ee5v1um00 3.7 instructions and data access times the below table 3-15 and ta bl e 3 - 1 6 list the instruction execution and data access cycles, required when accessing instructions or data in vfb flash, vdb ram and vsb flash/ram. the access time depends on the ? memory type (flash, ram) and access bus (vfb, vdb, vsb) ? number of latency cycles for the memory type ? type of data (instructions/data) ? type of access (consecutive/random addresses) ? device, i.e. maximum clock frequency in general the cpu is able to execute most instructions in one clock cycle (single-cycle instructions), provided no additional clock cycles are required to access the memory. note that for some instructions the cpu requires more clock cycles to execute anyway (multi-cycle instructions), regardless of the memory access time. the memory access time in a real application is deterministic, but can hardly be predicted, as this heavily depends on the status of the microcontroller and its components, the program flow and concurrent processes, like dma transfers, interrupts, accesses to peripheral registers via the npb, etc. thus the figures in the below tables assume ? all busses (vfb, vdb, vsb, npb) are not occupied, i.e. collision with other bus traffic is excluded ? 32-bit instruction/data accesses to word-aligned - that means 32-bit aligned - addresses ? data is not accessed via the same bus as the instruction is fetched from ? no wait states for the external memory interface timing consequently ?1 clock cycle? means: the instruction/data access takes one cpu clock cycle and the cpu is supplied with an instruction/data in each clock: the memory access time is invisible and has no effect. instruction execution the given numbers of cycles in table 3-15 describe the time required to execute a single-cycle instruction, fetched from the respective memory: ? consecutive access describes the number of cycles required to fetch instructions from the memory on consecutive addresses. ? random access describes the number of cycles required to access the memory in case instructions are accessed on random, i.e. non-consecutive, addresses. in case of instruction flow branches a cpu?s pipeline break occurs and an additional cycle is required to refill the pipeline. the table figures include this cycle. in case instructions and data are accessed via the same bus, all accesses - instruction fetch and data access - are regarded as random accesses. pd70f3426a vsb flash if an instruction is to be fetched from the vsb flash while an access to the npb is ongoing, the instruction fetch is stopped and completely restarted. this
137 cpu system functions chapter 3 user?s manual u17566ee5v1um00 means 3 additional cycles are necessary for each unsuccessful vsb flash instruction fetch. data access the given numbers of cycles in ta b l e 3 - 1 6 describe the time additionally required when an instruction accesses data in the respective memory. note that data accesses are always random accesses. table 3-15 single-cycle instructions execution times in cpu clock cycles memory access type pd70f3427 pd70f3426a pd70f3424 pd70f3425 pd70f3421 pd70f3422 pd70f3423 vfb flash consecutive 1 1 1 1 random 4 a a) these values include the additional clock cycle, caused by the cpu?s pipeline break 4 a 4 a 2 a vdb ram consecutive 1 1 1 1 random 2 a 2 a 2 a 2 a vsb flash consecutive ? ? 2 (32-bit instructions) ? 1 (16-bit instructions) ?? random ? 5 a ?? vsb ram consecutive ? 2 ? ? random ? 3 a ?? table 3-16 additional time for data accesses in cpu clock cycles data access memory instruction code fetch bus pd70f3427 pd70f3426a pd70f3424 pd70f3425 pd70f3421 pd70f3422 pd70f3423 vfb flash vfb 4 4 4 1 vdb ram vfb/vsb 0 0 0 0 vsb flash vfb ? 4 ? ? vsb ram vfb ? ? 1 (single access) ? 3 (multiple access) ??
138 chapter 3 cpu system functions user?s manual u17566ee5v1um00
139 user?s manual u17566ee5v1um00 chapter 4 clock generator the clock generator provides the clock signals needed by the cpu and the on-chip peripherals. 4.1 overview the clock generator can generate the required clock signals from the following sources: ? main oscillator - a built-in oscillator with external crystal and a nominal frequency of 4 mhz ? sub oscillator - a built-in oscillator with external crystal and a nominal frequency of 32 khz ? internal oscillator - an internal oscillator without external components and a nominal frequency of 240 khz features summary special features of the clock generator are: ? choice of oscillators to reduce power consumption in stand-by mode ? frequency multiplication by two pll synthesizers: ? fixed frequency pll for accurate timings ? spread spectrum pll (sscg) for reduced electromagnetic interference ? individual clock source selection for cpu and groups of peripherals ? five specific power save modes: ?halt mode ? idle mode ? watch mode ? sub-watch mode ?stop mode ? vital system registers are write-protected by a special write sequence ? direct main oscillator clock feed-through for watch clock correction support ? separate clock monitors for main and sub oscillator to detect oscillator malfunction
140 chapter 4 clock generator user?s manual u17566ee5v1um00 4.1.1 description the clock generator is built up as illustrated in the following figure. figure 4-1 block diagram of the clock generator the left-hand side of the figure shows how the three oscillators can be connected to the cpu, the two plls, and to certain peripheral modules. software-controlled selectors allow you to specify the signal paths. pll the integrated pll synthesizer multiplies the frequency of the main oscillator by eight. this yields a frequency of 32 mhz. the cpu can use the pll output directly. the output frequency of the pll divided by two can supply the peripherals of the microcontroller and also the cpu. sscg the spread spectrum clock generator (sscg) can generate a frequency- modulated clock (modulation frequency and width can be chosen) that helps to eliminate electromagnetic interference (emi). the sscg includes a programmable frequency multiplier/divider that can multiply the frequency of the main oscillator by up to 16. the sscg can supply the cpu system and some of the peripherals. standby prs0 afcan uarta csib tmz tmp wct sg standby pclk2 pclk3 ....... pclk15 standby standby standby stepper c/d tmg tmy csib lcd i/f lcd c/d adc standby standby standby foutclk fcc.foen n=1,2,4,8,16, 32,64,128 n=1,2,4,8,16,32, 64,128 n=1,2,4,8,16,32,64,128 1 0 tcc.wtsel1 fcc.focs[2:0] fcc.focks[1:0] pcc.soscp psm.cmode icc.iicps[2:0] icc.iicsel1 ckc.peric 1 0 0 1 wcc.wdtsel0 wcc.wdtsel1 wcc.soscw fcc.fosos 1 0 1 0 1 0 0 1 0 1 tcc.wtps[2:0] watch timer standby /2 pclk0 /2 / ....... / 0 2 2 1 13 spclk0 spclk1 standby prs1 standby spclk2 spclk3 ....... spclk15 /2 / ....... / 0 2 2 1 13 n=1,2,3,4,6,8 iic watch calibration timer iiclk wtclk lcdclk wdtclk pclk1 wctclk 1/2 n=1/ 3.5/ 4.5 pclk1 1/2 1/2 lcd c/d f sscgps 0 1 0 1 icc.iicsel0 1/4 1/2 1/n 1/n 1/n 1/n wcc.wps[2:0] scc.spsel1 scc.spsel0 scps.spsps[2:0] scps.vbsps[2:0] pcc.cks[1:0] pcc.cls standby vbclk cpu system ckc.den ckc.pllen scfc0,scfc1,scfmc ckc.scen pcc.frc pcc.mfrc x1 x2 xt1 xt2 tcc.wtsos tcc.wtsel0 pll x8 sscg 0 1 n=1,2,3,4,6,8 0 1 0 1 0 1 0 1 moclk soclk roclk sbclk sscclk pllclk watchdog timer port 0 1 mainosc 4 mhz int.osc ~200 khz subosc 32 khz
141 clock generator chapter 4 user?s manual u17566ee5v1um00 (1) cpu clocks the cpu can be clocked directly by any of the oscillators, or by the output of one of the plls. the following table gives an overview of the available cpu clocks. (2) peripheral clocks the right-hand side of figure 4-1 on page 140 shows how the clocks for the peripheral modules are generated and distributed. pclk clocks peripherals that require precise timings are connected to pclkn signals. such peripherals are the can controllers, the uarts, the timers z and p, and the clocked serial interfaces csib. the watch calibration timer wct can be connected to pclk1 or directly to the main oscillator. the clocks pclk0?1 can be derived from the main oscillator or the pll output. the pclk2?15 clocks are always derived from the main oscillator. spclk clocks peripherals that tolerate or demand a spread spectrum clock (like pwm output timers) are connected to spclkn signals. such peripherals are the stepper motor controller/driver, the timers g and y, the sound generator, the clocked serial interfaces csib (csib can also be connected to a pclk), the lcd bus i/f and controller/driver, and the a/d converter. the clocks spclk0?1 can be derived from the main oscillator, the sscg, or the pll. the spclk2?15 clocks can be derived from the main oscillator or the sscg. table 4-1 clock sources and frequencies for the cpu clock source frequency device description internal osc ~240 khz all default clock source after reset release. selectable as clock source for sub-watch mode release. sub osc 32 khz all selectable as clock source for sub-watch mode release. main osc 4 mhz all always selected after power save mode release except on sub-watch mode release or default clock setting. a on sub-watch mode release or default clock setting, main or sub oscillator can be selected. a) see also ?cpu operation after power save mode release? on page 193 pll 16 mhz all f main 8/2 b can be selected for cpu clock supply. b) multiplication is performed by the pll, the division by the pll post scaler. 32 mhz f main 8/1 b can be selected for cpu clock supply. sscg 8 mhz c c) center output frequency of the sscg, can be modulated up to +/- 5%. all f main 12/6 d can be selected for cpu clock supply. d) multiplication is performed by the sscg, the division by the sscg post scaler. 16 mhz c f main 16/4 d can be selected for cpu clock supply. 24 mhz c f main 12/2 d can be selected for cpu clock supply. 32 mhz c f main 16/2 d can be selected for cpu clock supply. 48 mhz c pd70f3424, pd70f3425, pd70f3426a, pd70f3427 f main 12/1 d can be selected for cpu clock supply. 64 mhz c f main 16/1 d can be selected for cpu clock supply.
142 chapter 4 clock generator user?s manual u17566ee5v1um00 iiclk clock the clock iiclk for the i 2 c interface has it?s own programmable frequency divider. the clock source can be chosen from the pll, sscg or main oscillator. (3) special clocks the figure shows also some special clock signals. these are dedicated clocks for the lcd controller/driver, watch timer, watchdog timer, and watch calibration timer. these clocks are directly derived from the oscillators and bypass the plls. lcdclk the lcd controller/driver can be clocked by spclk7, spclk9, or lcdclk. wtclk this is the clock for the watch timer. it forms the time base for updating the internal bookkeeping of daytime and calendar. note that lcdclk and wtclk have a common source and a fixed frequency ratio (1/1 or 1/2). wctclk this is the clock for the watch calibration timer wct. the wct is used in conjunction with the watch timer for calibrating the time base during power save modes by utilizing the main oscillator as the stable clock source. wctclk can also be derived from pclk1. foutclk foutclk is a clock signal that can be used for external devices. it is connected to the pin fout and can provide almost any of the internal clock frequencies (not phase-synchronized). foutclk must be enabled before it can be used. wdtclk this is the clock for the watchdog timer that is used for recovering from a system deadlock. wdtclk is available (and hence the watchdog timer running) as long as the chosen clock source is active. optionally wdtclk can be stopped during a power save mode. (4) stand-by control in the block diagram, you find also boxes labelled ?standby?. these boxes symbolize the switches that are used to disable circuits when the microcontroller enters one of the various power save modes. the following clocks are subject to automatic stand-by control: cpu system clock, pclk, spclk, iiclk optionally wdtclk. the following clocks can be operating during power save modes (stand-by) as long as their clock oscillator source is available: foutclk, lcdclk, wtclk, wctclk, optionally wdtclk. 4.1.2 clock monitors the microcontroller contains clock monitors to monitor the operation of the 4 mhz main oscillator and the 32 khz sub oscillator. in case of malfunction, these monitors can generate a system reset. the monitors require that the built-in internal oscillator is active. for details see ?operation of the clock monitors? on page 198 .
143 clock generator chapter 4 user?s manual u17566ee5v1um00 4.1.3 power save modes overview the microcontroller provides the following stand-by modes: halt, idle, watch, sub-watch, and stop. application systems which are designed in a way that they switch between these modes according to operation purposes, reduce power consumption efficiently. the following explanations provide a general overview and refer to the default settings. some settings can be changed, for example the activity of the watch and watchdog clocks and hence the connected timers. for details, please refer to ?power save modes description? on page 179 and the register descriptions. halt mode in this mode, the clock supply to the cpu is suspended while other on-chip peripherals continue to operate. combining this mode with the normal operating mode results in intermittent operation and reduces the overall system power consumption. this mode is entered by executing the halt instruction. all other power save modes are entered by setting the registers psm and psc. idle mode in this mode, the clock distribution is stopped and hence the whole system. the oscillators, clock generator (pll, sscg, frequency multipliers, dividers), watch timer, and watchdog timer remain operating. this mode allows quick return to the normal operating mode in response to a release signal, because it is not necessary to wait for oscillators or plls to settle. this mode provides low power consumption. power is only consumed by the oscillators (main oscillator, sub oscillator), clock generator (pll and sscg), and watch timer / watchdog timer. watch mode in this mode, the clock generator (pll and sscg) stops operation. therefore, the entire system except watch timer / watchdog timer stops. this mode provides low power consumption. power is only consumed by the oscillators (main oscillator, sub oscillator), and the watch timer / watchdog timer circuits. sub-watch mode in this mode, not only the clock generator is stopped but also the main oscillator . watch timer / watchdog timer are switched to the sub or internal oscillator. therefore, the entire system except watch timer / watchdog timer stops. this mode provides very low power consumption. power is only consumed by the sub oscillator and watch timer / watchdog timer circuits. stop mode in this mode, the entire system stops. this mode provides ultra-low power consumption. power is only consumed by leakage current and the sub oscillator (if a crystal is connected).
144 chapter 4 clock generator user?s manual u17566ee5v1um00 4.1.4 start conditions after any reset release, the internal oscillator is always selected as the clock source. the oscillation stabilization time for the internal oscillator is ensured by hardware. the cpu clock vbclk is derived from the internal oscillator. several clocks are operating based on the internal oscillator clock after reset. as soon as the main oscillator, which is started by the internal firmware, is stable the source of these clocks is automatically changed to the main oscillator. therefore depending on the firmware operation and the main oscillator stabilization time these clocks may already be operating with the main oscillator, when the user?s program is started. internal firmware starts the main oscillator. pll and sscg remain stopped. when the firmware passes control to the application software, software has to ensure that the main oscillator has stabilized and to start the pll and sscg. note clock supply for most peripherals is not available unless the main oscillator operates. cpu access to peripherals that have no clock supply may cause system deadlock. table 4-2 clock generator status after reset release item status remarks main oscillator stopped started by internal firmware sub oscillator operates internal oscillator operates sscg stopped pll stopped vbclk (cpu system) operates based on internal oscillator clock iiclk operates based on internal/main oscillator clock a a) starts with internal oscillator, automatically changed to main oscillator, when main oscillator stable. pclk0, pclk1 operates based on internal/main oscillator clock a pclk2?pclk15 operates based on internal/main oscillator clock a spclk0, spclk1 operates based on internal/main oscillator clock a spclk2?spclk15 operates based on internal/main oscillator clock a foutclk operates based on internal/main oscillator clock a lcdclk / wtclk operates b b) if the reset was caused by power-on clear (poc) or external reset , the clock source for lcdclk and wtclk is set to internal oscillator. if the re- set was caused by a different source, the clock selection for lcdclk / wt- clk remains unchanged. based on internal/main oscillator clock a wdtclk operates based on internal/main oscillator clock a wctclk operates based on internal/main oscillator clock a
145 clock generator chapter 4 user?s manual u17566ee5v1um00 4.1.5 start-up guideline after reset release, the internal firmware starts the main oscillator, but hands over control to the user?s software without ensuring that the main oscillator has stabilized. after that, the user?s software will typically: 1. ensure that the main oscillator has stabilized (check cgstat.oscstat). 2. switch the source of lcdclk/wtclk and wdtclk to main oscillator (if desired). 3. start the pll (set ckc.pllen) and wait until the pll has stabilized (refer to the data sheet). 4. if the sscg is going to be used: write sscg registers to set up the sscg. this is only possible when the sscg is switched off. start the sscg (set ckc.scen) and wait until the sscg has stabilized (refer to the data sheet). 5. write the pcc register to specify the sscg as the clock source for the cpu. 6. set up the clock sources for the peripherals according to application requirements. 7. the default value of following registers must be changed after reset: ? ada0m1.bit7 = 1 (refer to ?adc registers? on page 861 )
146 chapter 4 clock generator user?s manual u17566ee5v1um00 4.2 clock generator registers the clock generator is controlled and operated by means of the following registers (the list is sorted according to memory allocation): note some registers are write-protected to avoid inadvertent changes. data can be written to these registers only in a special sequence of instructions, so that the register contents is not easily rewritten in case of a program hang-up. writing to a protected register is only possible immediately after writing to the associated write protection register. table 4-3 clock generator register overview register name shortcut address write-protected by register psc write protection register prcmd ffff f1fc h power save control register psc ffff f1fe h prcmd stand-by control register stbctl ffff fca2 h stbctlp stand-by control protection register stbctlp ffff fcaa h sub oscillator clock monitor control register clmcs ffff f71a h command protection register phcmd ffff f800 h peripheral status register phs ffff f802 h power save mode register psm ffff f820 h clock generator control register ckc ffff f822 h phcmd clock generator status register cgstat ffff f824 h watchdog timer clock control register wcc ffff f826 h phcmd processor clock control register pcc ffff f828 h phcmd sscg frequency modulation control register scfmc ffff f82a h sscg frequency control 0 register scfc0 ffff f82c h sscg frequency control 1 register scfc1 ffff f82e h sscg post scaler control register scps ffff f830 h spclk control register scc ffff f832 h phcmd foutclk control register fcc ffff f834 h phcmd watch timer clock control register tcc ffff f836 h phcmd iic clock control register icc ffff f838 h phcmd set default clock register sdc ffff f83c h phcmd main oscillator clock monitor mode register clmm ffff f870 h prcmdcmm sub oscillator clock monitor mode register clms ffff f878 h prcmdcms clmm write protection register prcmdcmm ffff fcb0 h clms write protection register prcmdcms ffff fcb2 h
147 clock generator chapter 4 user?s manual u17566ee5v1um00 the subsequent register descriptions are grouped as follows: ? general clock generator registers: ? ?ckc - clock generator control register? on page 148 ? ?cgstat - clock generator status register? on page 149 ? ?phcmd - command protection register? on page 150 ? ?phs - peripheral status register? on page 151 ? ?pcc - processor clock control register? on page 152 ? ?sdc - set default clock register? on page 154 ? sscg control registers: ? ?scfc0 - sscg frequency control register 0? on page 156 ? ?scfc1 - sscg frequency control register 1? on page 157 ? ?scfmc - sscg frequency modulation control register? on page 158 ? ?scps - sscg post scaler control register? on page 160 ? control registers for peripheral clocks: ? ?wcc - watchdog timer clock control register? on page 161 ? ?tcc - watch timer clock control register? on page 163 ? ?scc - spclk control register? on page 165 ? ?fcc - foutclk control register? on page 166 ? ?icc - iic clock control register? on page 168 ? control registers for power save modes: ? ?psm - power save mode register? on page 169 ? ?psc - power save control register? on page 172 ? ?prcmd - psc write protection register? on page 173 ? ?stbctl- stand-by control register? on page 174 ? ?stbctlp - stand-by control protection register? on page 174 ? clock monitor registers: ? ?clmm - main oscillator clock monitor mode register? on page 175 ? ?prcmdcmm - clmm write protection register? on page 176 ? ?clms - sub oscillator clock monitor register? on page 177 ? ?prcmdcms - clms write protection register? on page 177 ? ?clmcs - sub oscillator clock monitor control register? on page 178
148 chapter 4 clock generator user?s manual u17566ee5v1um00 4.2.1 general clock generator registers the general clock generator registers control and reflect the operation of the clock generator. (1) ckc - clock generator control register the 8-bit ckc register controls the clock management. access this register can be read/written in 8-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?phcmd - command protection register? on page 150 for details. address ffff f822 h . initial value 00 h . the register is initialized by any reset. 76543 2 1 0 pllen scen den 0 peric 0 0 0 r/w r/w r/w r a a) these bits may be written, but write is ignored. r/w r a r a r a table 4-4 ckc register contents bit position bit name function 7pllen a a) before enabling pllen or scen, make sure that the main oscillator is running and has settled (see also cg- stat register). the cpu must operate on the sub, internal or main oscillator clock when setting pllen or scen to 1. before selecting the sscg / pll outputs as clock sources for peripherals, ensure by software that the sscg / pll stabilization time has elapsed.the stabilization times are defined in the data sheet. pll enable: 0: pll disabled. 1: pll on. it is not possible to clear this bit by writing to the register. the bit is automatically cleared in watch, sub-watch, or stop mode, or if bit sdc.sdcr is set to 1. 6scen a sscg enable: 0: sscg disabled. 1: sscg on. it is not possible to clear this bit by writing to the register. the bit is automatically cleared in watch, sub-watch, or stop mode, or if bit sdc.sdcr is set to 1. 5 den sscg dithering mode enable: 0: sscg uses fixed multiplication factor determined by scfc0, scfc1 1: sscg is in dithering mode. the base frequency, determined by the registers scfc0, scfc1, is modulated according to the setup of register scfmc. den must not be toggled while scen is 1. 3 peric clock source selection for pclk0/1: 0: main oscillator is clock source for peripheral clocks pclk0, pclk1. 1: pll (x4) is clock source for peripheral clocks pclk0, pclk1. this bit is automatically cleared in watch, sub-watch, or stop mode, or if bit sdc.sdcr is set to 1.
149 clock generator chapter 4 user?s manual u17566ee5v1um00 (2) cgstat - clock generator status register the 8-bit cgstat register is read-only. it indicates the status of the main oscillator and the status of the clock generator after wake-up from power save mode. access this register can be read in 8-bit units. address ffff f824 h . initial value 0000 1101 b . the register is initialized by any reset. 76543 2 1 0 cmplpsm 0001 1 oscstat 1 rrrrr r r r table 4-5 cgstat register contents bit position bit name function 7 cmplpsm completed power save mode entry: 0: power save mode configuration not completed. 1: power save mode configuration completed. this bit is cleared when the clock generator has accepted a power save mode request. however if cgstat.cmlpsm was already 0 before a power save mode request it can not be used as an indicator that the clock generator has accepted this power save mode request. this bit is set when the clock generator has completely set up it's power save mode configuration, i.e. all registers are set up, pll and sscg are switched off. however if cgstat.cmlpsm was already 1 before a power save mode request it can not be used as the only indicator that the clock generator has completed power save mode configuration. if the clock generator has not accepted a power save mode request this bit remains unchanged. refer also to ? ?cpu operation after power save mode release? on page 193 ?. 1 oscstat main oscillator status indicator (determined by counter): 0: main oscillator has not settled. 1: main oscillator has stabilized. the oscstat flag is cleared whenever the main oscillator is switched to stand-by mode due to entering the sub-watch or stop mode. after the main oscillator is restarted, the oscillation stabilization counter will count up from 0 to 40.960 (approx. 10ms @ 4 mhz) to assure stable oscillator operation. when the oscillation stabilization counter reaches 40.960, the counter is stopped, and the oscstat flag is set.
150 chapter 4 clock generator user?s manual u17566ee5v1um00 (3) phcmd - command protection register the 8-bit phcmd register is write-only. it is used to protect other registers from unintended writing. access this register must be written in 8-bit units. address ffff f800 h . initial value the contents of this register is undefined. phcmd protects the registers that may have a significant influence on the application system from inadvertent write access, so that the system does not stop in case of a program hang-up. any data written to this register is ignored. only the write action is monitored. after writing to the phcmd register, you are permitted to write once to one of the protected registers. this must be done immediately after writing to the phcmd register. after the second write action, or if the second write action does not follow immediately, all protected registers are write-locked again. caution in case a high level programming language is used, make sure that the compiler translates the two write instructions to phcmd and the protected register into two consecutive assembler ?store? instructions. with this method, the protected registers can only be rewritten in a specific sequence. illegal write access to a protected register is inhibited. the following registers are protected by phcmd: an invalid write attempt to one of the above registers sets the error flag phs.prerr. phs.prerr is also set, if a write access to phcmd is not immediately followed by an access to one of the protected registers. 76543 2 1 0 xxxxx x x x wwwww w w w ? ckc: clock control register ? fcc: foutclk control register ? icc: i 2 c clock control register ? pcc: processor clock control register ? scc: spclk control register ? tcc: watch timer clock control register ? wcc: watchdog timer clock control register ? sdc: set default clock register
151 clock generator chapter 4 user?s manual u17566ee5v1um00 (4) phs - peripheral status register the 8-bit phs register indicates the status of a write attempt to a register protected by phcmd (see also ?phcmd - command protection register? on page 150 ). access this register can be read/written in 8-bit units. address ffff f802 h . initial value 00 h . the register is cleared by any reset. note phs.prerr is set, if a write access to register phcmd is not directly followed by a write access to one of the write-protected registers. 76543210 0000000prerr r a a) these bits may be written, but write is ignored. r a r a r a r a r a r a r/w table 4-6 phs register contents bit position bit name function 0 prerr write error status: 0: write access was successful. 1: write access failed. you can clear this register by writing 0 to it. setting this register to 1 by software is not possible.
152 chapter 4 clock generator user?s manual u17566ee5v1um00 (5) pcc - processor clock control register the 8-bit pcc register controls the cpu clock. this register can be changed only once after reset or power save mode release. access this register can be read/written in 8-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?phcmd - command protection register? on page 150 for details. address ffff f828 h . initial value 10 h . the register is initialized by any reset. 76543 2 1 0 frc 0 mfrc cls 0 soscp cks1 cks0 r/w r a a) these bits may be written, but write is ignored. r/w r a r a r/w r/w r/w table 4-7 pcc register contents (1/2) bit position bit name function 7 frc sub oscillator circuit: control of internal return resistance 0: resistor connected. 1: resistor disconnected. set frc only to 1, if the sub oscillator is not used. 5 mfrc main oscillator circuit: control of internal return resistance 0: resistor connected. 1: resistor disconnected. do not change the initial setting. to ensure correct operation of the main oscillator, the internal feed-back resistor must remain connected. 4 cls processor clock source monitor flag: 0: main oscillator operation?source can be the output of main oscillator, pll, or sscg (selection through cks[1:0]). the main oscillator is enabled by the internal firmware. 1: sub clock operation: 32 khz sub or 240khz internal oscillator (selection through bit soscp). this is the default after reset. it is not possible to set this bit to 1 by writing to the register. on sub-watch release, the cls bit is set to the state of psm.oscdis. this is the only way to set cls to 1, which means, the main oscillator remains stopped and the cpu is supplied with the sub clock chosen by soscp. cls is automatically cleared when the processor clock source is changed by writing to pcc.cks[1:0]. if cls is 1, the bits cks[1:0] have no meaning. 2 soscp sub clock selection: 0: internal oscillator is used for sub clock operation. 1: sub oscillator is used for sub clock operation. this setting takes effect when bit cls is 1. caution: do not specify the sub oscillator, if the sub oscillator is not enabled or not connected.
153 clock generator chapter 4 user?s manual u17566ee5v1um00 note 1. switching to an unstable or not available clock is not protected by hardware. you must monitor the cgstat register or count the required stabilization time by software before switching to make sure not to select an unstable clock source. ensure also that the stabilization times of the pll and sscg (refer to the data sheet) have elapsed before using any pll or sscg output clock. 2. switching to sub clock after sub-watch and watch mode release or writing 1 to sdc.sdcr is monitored in the cls flag. the cls flag can not be changed to 1 by software. 3. frc, mfrc and soscp are not changed when power save modes are entered or released. write protection write protection of this register is achieved in two ways: ? the register can be written only once after any reset. ? the register is protected by a special sequence via the phcmd register. a fail of a write by the special sequence is reflected by phs.prerr = 1. if a write is correctly performed by the special sequence after the register has already once been written successfully phs.prerr remains 0, though the write has been ignored. phs.prerr shows violations of the special sequence only. it does not reflect attempts to write the register more than once after reset or power save mode wake-up. 1 to 0 cks[1:0] processor clock connection: cks1 cks0 selected clock connection 00 main oscillator 01 sscg 10 pll (main oscillator frequency x4) 11 pll (main oscillator frequency x8) as long as pcc.cls = 1 these bits are ignored. for changing the processor clock source these bits must be written. by this cls is set to 0 automatically. table 4-7 pcc register contents (2/2) bit position bit name function
154 chapter 4 clock generator user?s manual u17566ee5v1um00 (6) sdc - set default clock register the 8-bit sdc register can be used to reset the clock generator to default state. this is the state that is set after power save mode release. depending on the flags psm.oscdis and pcc.soscp, the main, sub, or internal oscillator becomes the cpu clock source. both pll and sscg are disabled, and all cpu and peripheral clock selections as well as the sscg setup can be rewritten. access this register can be read/written in 8-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?phcmd - command protection register? on page 150 for details. address ffff f83c h . initial value 00 h . the register is cleared by any reset. setting sdc.sdcr has the following effects: ? sdc.sdcr remains set until the default clock setting procedure has finished. after that, it is automatically cleared. ? depending on the bits psm.oscdis and pcc.soscp, either main, sub, or internal oscillator is chosen as the clock source of the cpu. ? ckc.peric is cleared?the main oscillator is the clock source for pclk0/1. ? scc.spsel[1:0] is cleared?the main oscillator is the clock source for all spclk clocks. ? icc.iicsel[1:0] is cleared?the main oscillator is the clock source for iiclk. ? ckc.pllen and ckc.scen are cleared?but pll and sscg are not stopped. note 1. for further information concerning default clock setting refer to ?power save mode activation? on page 191 . 2. as long as sdc.sdcr is set, do not access any clock generator register except sdc. 76543210 0000000sdcr r a a) these bits may be written, but write is ignored. r a r a r a r a r a r a r/w table 4-8 sdc register contents bit position bit name function 0 sdcr set default clock generator configuration: 0: normal operation. 1: establish default clock settings. the bit sdc.sdcr can be set by writing 1. clearing sdc.sdcr by writing 0 is not possible, but is done automatically after default clock settings are completed.
155 clock generator chapter 4 user?s manual u17566ee5v1um00 4.2.2 sscg control registers this section describes the registers used for controlling the spread spectrum clock generator sscg. for modulating the sscg output clock it?s dithering mode must be enabled by ckc.den = 1. reconfiguration of sscg registers the sscg control registers scfc0, scfc1 and scfmc can only be rewritten with new settings if the sscg is switched off, i.e. if ? the sscg is disabled by ckc.scen = 0 ? the sscg is safely switched off after a power save mode wake-up. refer to ?cpu operation after power save mode release? on page 193 for a procedure to ensure that the sscg is switched off after wake-up. during operation of the sscg the registers may only be rewritten with the values, they already have.
156 chapter 4 clock generator user?s manual u17566ee5v1um00 (1) scfc0 - sscg frequency control register 0 the 8-bit scfc0 register controls the frequency modulation of the sscg. it determines the sscg output frequency and is used in conjunction with register scfc1. the center sscg output frequency is f sscgc =(4 mhz n/m) / 2. this register defines the divisor ?m? and thus m = m + 1. access this register can be read/written in 8-bit or 1-bit units. address ffff f82c h . initial value 52 h . the register is initialized by any reset. note 1. this register can only be rewritten with a new value if the sscg is switched off. refer to the explanation at the beginning of this section. 2. the initial value of this register must be changed after reset. frequency calculation if dithering mode is disabled (ckc.den = 0) the sscg outputs its center frequency f sscgc : f sscgc = (4 mhz x n/m) / 2 where: ? m = m + 1 = scfc0.scfc0[2:0] + 1 ? n = n + 1 = scfc1.scfc1[6:0] + 1 the values to be written into scfc0 and scfc1 are restricted. possible combinations are: 76543210 0 a a) the default value ?0? of this bit must not be altered. scfc06 scfc05 scfc04 scfc03 scfc02 scfc01 scfc00 r/w r/w r/w r/w r/w r/w r/w r/w table 4-9 scfc0 register contents bit position bit name function 6 to 5 scfc0[6:5] must be set to 01 b 4 to 3 scfc0[4:3] must be set according to ta bl e 4 - 1 0 2 to 0 scfc0[2:0] determines the divisor m table 4-10 supported settings of n (n) and m (m) f sscgmax m (m) n (n) scfc0 scfc1 48 mhz 4 (3) 96 (95) 2b h df h 64 mhz 3 (2) 96 (95) 32 h df h
157 clock generator chapter 4 user?s manual u17566ee5v1um00 (2) scfc1 - sscg frequency control register 1 the 8-bit scfc1 register controls the frequency multiplication of the sscg. it determines the sscg output frequency and is used in conjunction with register scfc0. the center sscg output frequency is f sscgc =(4 mhz n/m) / 2. this register defines the factor ?n? and thus n = n + 1. access this register can be read/written in 8-bit or 1-bit units. address ffff f82e h . initial value eb h . the register is initialized by any reset. note 1. bits 7 is set to 1 and must not be changed. 2. this register can only be rewritten with a new value if the sscg is switched off. refer to the explanation at the beginning of this section. 76543210 1 scfc16 scfc15 scfc14 scfc13 scfc12 scfc11 scfc10 r/w r/w r/w r/w r/w r/w r/w r/w table 4-11 scfc1 register contents bit position bit name function 6 to 0 scfc1[6:0] determines the factor n
158 chapter 4 clock generator user?s manual u17566ee5v1um00 (3) scfmc - sscg frequency modulation control register the 8-bit scfmc register controls the frequency modulation of the sscg in dithering mode (when ckc.den = 1). access this register can be read/written in 8-bit or 1-bit units. address ffff f82a h . initial value 00 h . the register is initialized by any reset. note 1. this register can only be rewritten with a new value if the sscg is switched off. refer to the explanation at the beginning of this section. 2. the given modulation ranges and frequencies are typical values. refer also to the data sheet. in dithering mode, the sscg output frequency f sscg varies according to the fm range, specified by scfmc[4:2], around it?s center value: f sscg =f sscgc (fm range) the time of one full cycle is given by the period of the modulation frequency specified in scfmc[1:0]. 76543 2 1 0 0 0 0 scfmc4 scfmc3 scfmc2 scfmc1 scfmc0 r r r r/w r/w r/w r/w r/w table 4-12 scfmc register contents bit position bit name function 4 to 2 scfmc[4:2] frequency modulation range control: scfmc4 scfmc3 scfmc2 fm range 000 0.5 % (typical value) 001 1.0 % (typical value) 010 2.0 % (typical value) 011 3.0 % (typical value) 100 4.0 % (typical value) 101 5.0 % (typical value) other settings prohibited 1 to 0 scfmc[1:0] frequency modulation frequency control: scfmc1 scfmc0 modulation frequency 00 40 khz (typical value) 01 50 khz (typical value) 10 60 khz (typical value) 11 prohibited
159 clock generator chapter 4 user?s manual u17566ee5v1um00 example if: ? scfc0 = 2b h , scfc1 = df h : center frequency f sscgc =48mhz ? [scfmc[4:2]] = 101 b : fm range = 5 % ? [scfmc[1:0]] = 01 b : modulation frequency = 50 khz then: ? the sscg frequency is swept between about 45.6 mhz and 50.4 mhz. ? one sweep cycle takes typically 20 s.
160 chapter 4 clock generator user?s manual u17566ee5v1um00 (4) scps - sscg post scaler control register the 8-bit scps register controls the two independent sscg post scalers (frequency dividers) for the cpu system clock vbclkand for the modulated peripheral clocks spclk. access this register can be read/written in 8-bit or 1-bit units. address ffff f830 h . initial value 21 h . the register is initialized by any reset. note this register can only be written when the sscg enable bit ckc.scen is cleared (sscg switched off). 76543210 0 spsps2 spsps1 spsps0 0 vbsps2 vbsps1 vbsps0 r/w r/w r/w r/w r/w r/w r/w r/w table 4-13 scps register contents bit position bit name function 6 to 4 spsps[2:0] sscg clock divider selection for generating spclk0: spsps2 spsps1 spsps0 clock divider setting 000 spclk0 = sscg out frequency / 1 001 spclk0 = sscg out frequency / 2 010 spclk0 = sscg out frequency / 3 011 spclk0 = sscg out frequency / 4 100 not supported 101 spclk0 = sscg out frequency / 6 110 not supported 111 spclk0 = sscg out frequency / 8 2 to 0 vbsps[2:0] sscg clock divider selection for generating vbclk: vbsps2 vbsps1 vbsps0 clock divider setting 000 vbclk = sscg out frequency / 1 001 vbclk = sscg out frequency / 2 010 vbclk = sscg out frequency / 3 011 vbclk = sscg out frequency / 4 100 not supported 101 vbclk = sscg out frequency / 6 110 not supported 111 vbclk = sscg out frequency / 8
161 clock generator chapter 4 user?s manual u17566ee5v1um00 4.2.3 control registers for peripheral clocks this section describes the registers used for specifying the sources and operation modes for the clocks provided for the on-chip peripherals. these clocks are the clocks for the watchdog and watch timers, the spclkn clocks, foutclk, and iiclk. note be aware that the wcc register controls not only the generation of the watchdog timer clock. it defines also the run/stop mode of the sub and internal oscillators when certain power save modes are entered. (1) wcc - watchdog timer clock control register the 8-bit wcc register controls the watchdog timer clock. this register can be changed only once after any reset. writing to this register is protected by a special sequence of instructions. please refer to ?phcmd - command protection register? on page 150 for details. access this register can be read/written in 8-bit units. address ffff f826 h . initial value 00 h . the register is initialized by any reset. 76543 2 1 0 sostp wps2 wps1 wps0 rostp soscw wdtsel1 wdtsel0 r/w r/w r/w r/w r/w r/w r/w r/w table 4-14 wcc register contents (1/2) bit position bit name function 7 sostp sub oscillator stop mode control 1: sub oscillator will stop when stop mode is entered. 0: sub oscillator will not stop when stop mode is entered. 6 to 4 wps[2:0] wdt clock divider selection: wps2 wps1 wps0 clock divider setting 000 1 001 1 / 2 010 1 / 4 011 1 / 8 100 1 / 16 101 1 / 32 110 1 / 64 111 1 / 128 3 rostp internal oscillator stop control: 1: internal oscillator stops if watch, sub-watch or stop mode is entered 0: internal oscillator always operates
162 chapter 4 clock generator user?s manual u17566ee5v1um00 note 1. for security reasons, the wcc register should always be programmed after reset, even if the default settings are used. 2. watch and watchdog timer clocks are not gated during the sub oscillator stabilization period after stop-mode release. this may generate spikes on the clock supply of the watch and watchdog timers. write protection write protection of this register is achieved in two ways: ? the register can be written only once after power-on-clear reset or external reset. ? the register is protected by a special sequence via the phcmd register. a fail of a write by the special sequence is reflected by phs.prerr = 1. if a write is correctly performed by the special sequence after the register has already once been written successfully phs.prerr remains 0, though the write has been ignored. phs.prerr shows violations of the special sequence only. it does not reflect attempts to write the register more than once after reset. 2, 0 soscw, wdtsel0 watchdog timer clock source selection: soscw wdtsel0 wdt clock source 00 internal oscillator 10 sub oscillator 01 main oscillator 11 setting prohibited by default, the sub oscillator is disabled in stop mode (see bit sostp). if sostp is 1, choose main or internal oscillator before entering stop mode. caution: do not specify the sub oscillator, if the sub oscillator is not enabled or not connected. 1 wdtsel1 watchdog timer clock stand-by control 0: wdtclk stops in idle, watch, sub-watch and stop modes. 1: wdtclk operates as long as the selected clock source operates. table 4-14 wcc register contents (2/2) bit position bit name function
163 clock generator chapter 4 user?s manual u17566ee5v1um00 (2) tcc - watch timer clock control register the 8-bit tcc register determines the watch timer and lcd controller clock source and the setting of the associated clock dividers. this register can be changed only once after power-on-clear reset or external reset . access this register can be read/written in 8-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?phcmd - command protection register? on page 150 for details. address ffff f836 h . initial value 00 h . the register is initialized at power-on and by external reset . 76543210 0 wtps2 wtps1 wtps0 0 wtsos wtsel1 wtsel0 r a a) these bits may be written, but write is ignored. r/w r/w r/w r a r/w r/w r/w table 4-15 tcc register contents (1/2) bit position bit name function 6 to 4 wtps[2:0] lcdclk clock divider selection: wtps2 wtps1 wtps0 clock divider setting 000 1 001 1 / 2 010 1 / 4 011 1 / 8 100 1 / 16 101 1 / 32 110 1 / 64 111 1 / 128 1 wtsel1 wtclk (watch timer clock) divider setting: 0: wtclk = lcdclk. 1: wtclk = lcdclk / 2.
164 chapter 4 clock generator user?s manual u17566ee5v1um00 note only poc and external reset can clear the tcc register. only one write access to tcc is allowed after reset release. once the tcc has been written, it ignores new write accesses until the next poc or external reset is issued. write protection write protection of this register is achieved in two ways: ? the register can be written only once after power-on-clear reset or external reset. ? the register is protected by a special sequence via the phcmd register. a fail of a write by the special sequence is reflected by phs.prerr = 1. if a write is correctly performed by the special sequence after the register has already once been written successfully phs.prerr remains 0, though the write has been ignored. phs.prerr shows violations of the special sequence only. it does not reflect attempts to write the register more than once after reset. 2, 0 wtsos, wtsel0 clock source for watch timer and lcd controller: wtsos wtsel0 clock source 00 internal oscillator 10 sub oscillator 01 main oscillator 11 setting prohibited by default, the sub oscillator is disabled in stop mode (see bit wcc.sostp). if wcc.sostp is 1, choose main or internal oscillator before entering stop mode. caution: do not specify the sub oscillator, if the sub oscillator is not enabled or not connected. table 4-15 tcc register contents (2/2) bit position bit name function
165 clock generator chapter 4 user?s manual u17566ee5v1um00 (3) scc - spclk control register the 8-bit scc register selects the spclk sources. access this register can be read/written in 8-bit or 1-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?phcmd - command protection register? on page 150 for details. address ffff f832 h . initial value 00 h . the register is initialized by entering watch, sub-watch, or stop mode, or if control bit sdc.sdcr is set. note 1. ?main osc? is the clock moclk provided by the main oscillator. 2. ?pll? is the clock pllclk provided by the pll. ?sscg ps ? is the clock provided by the sscg post scaler for spclk (see also ?scps - sscg post scaler control register? on page 160 76543210 0 0 0 0 0 0 spsel1 spsel0 rrrrrrr/wr/w bit position bit name function 1 to 0 spsel[1:0] source selection for generating the spclk clocks: spsel1 spsel0 clock sources spclk0 spclk1 spclk2 0 0 main osc main osc main osc 0 1 pll / 2 pll / 4 main osc 1 0 not supported 1 1 sscg ps sscg ps / 2 sscg ps / 4
166 chapter 4 clock generator user?s manual u17566ee5v1um00 (4) fcc - foutclk control register the 8-bit fcc register configures the output clock foutclk that can be used for external devices. access this register can be read/written in 8-bit or 1-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?phcmd - command protection register? on page 150 for details. address ffff f834 h . initial value 00 h . the register is initialized by any reset. 76543210 foen focs2 focs1 focs0 0 fosos focks1 focks0 r/w r/w r/w r/w r r/w r/w r/w table 4-16 fcc register contents bit position bit name function 7 foen output clock foutclk enable: 0: foutclk is disabled. 1: foutclk is enabled. 6 to 4 focs[2:0] output clock divider setting for foutclk: focs2 focs1 focs0 clock divider setting 000 foutclk = selected clock source / 1 001 foutclk = selected clock source / 2 010 foutclk = selected clock source / 4 011 foutclk = selected clock source / 8 100 foutclk = selected clock source / 16 101 foutclk = selected clock source / 32 110 foutclk = selected clock source / 64 111 foutclk = selected clock source / 128 2 to 0 fosos, focks[1:0] clock source selection for foutclk: fosos focks1 focks0 clock source x00 main oscillator x01 sscg x10 pll 011 internal oscillator 111 sub oscillator caution: do not specify the sub oscillator, if the sub oscillator is not enabled or not connected.
167 clock generator chapter 4 user?s manual u17566ee5v1um00 note 1. foutclk is not influenced by stand-by modes of the microcontroller. it runs as long as it is enabled and the selected clock source operates. application software must stop foutclk by clearing the foen bit to minimize power consumption in stand-by modes. 2. there is an upper frequency limit for the output buffer of the foutclk function. do not select a frequency higher than the maximum output buffer frequency. please refer to the data sheet for the frequency limit.
168 chapter 4 clock generator user?s manual u17566ee5v1um00 (5) icc - iic clock control register the 8-bit icc register determines the i 2 c clock source and the clock divider setting for iiclk. access this register can be read/written in 8-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?phcmd - command protection register? on page 150 for details. address ffff f838 h . initial value 00 h . the register is cleared by any reset. note 1. on release of watch, sub-watch and stop mode or when the sdc.sdcr bit is set, iicsel[1:0] is cleared?the main oscillator is selected as the iic clock source. pay attention if psm.oscdis = 1 before entering any of the above power save modes, because the main oscillator will be disabled. therefore the i 2 c interface will have no clock supply after power save mode release. 2. the connected i 2 c interfaces must be disabled before switching iicps[2:0]. to switch the iicps bits, first disable the i 2 c interface by clearing the enable bit in the iic control register, then switch iicps[2:0] and finally re-enable the iic interface. 76543210 0 iicps2 iicps1 iicps0 0 0 iicsel1 iicsel0 r a a) these bits may be written, but write is ignored. r/w r/w r/w r a r a r/w r/w table 4-17 icc register contents bit position bit name function 6 to 4 iicps[2:0] divider setting for iiclk: iicps2 iicps1 iicps0 clock divider setting 000 1 101 1 / 3.5 111 1 / 4.5 other settings not supported 1 to 0 iicsel[1:0] clock source for iiclk: iicsel1 iicsel0 clock source 00 main oscillator 01 sscg / 2 1x pll
169 clock generator chapter 4 user?s manual u17566ee5v1um00 4.2.4 control registers for power save modes the registers described in this section control the begin and end of the power save modes idle, watch, sub-watch, and stop. please refer to ?power save mode activation? on page 191 for instructions and an example on how to enter a power save mode. (1) psm - power save mode register the 8-bit psm register specifies the power save mode and controls the clock generation after reset and sub-watch mode release. in addition, it specifies the source of the watch calibration timer clock wctclk. access this register can be read/written in 8-bit or 1-bit units. address ffff f820 h . initial value 08 h . the register is initialized by any reset. since the main oscillator is started by the internal firmware are reset, psm enters the user?s program with the setting 00 h . 76543 2 1 0 0 cmode 0 0 oscdis 0 psm1 psm0 r r/w r r r/w r r/w r/w table 4-18 psm register contents (1/3) bit position bit name function 6 cmode watch calibration timer clock selection: 0: pclk1. 1: main oscillator.
170 chapter 4 clock generator user?s manual u17566ee5v1um00 3 oscdis main oscillator disable/enable control during and after power save mode: 0: main oscillator enabled. 1: main oscillator disabled. caution: if oscdis is set to 1, the main oscillator clock supply for the watch timer and the lcd controller/driver are stopped immediately. thus these function stop their operation immediately as well, when the main oscillator is used as the clock source. oscdis determines also the behaviour of the main oscillator during and after power save mode. the effect of this bit differs, depending on the power save mode. ? sub-watch mode during sub-watch mode the main oscillator is always stopped. oscdis determines whether the main oscillator shall be started and chosen as cpu clock source or should remain stopped after sub-watch mode release. 0: main oscillator enable. the main oscillator is started after sub-watch mode release and the cpu is supplied with the main oscillator clock, after the oscillation stabilization time has elapsed. 1: main oscillator disable. the main oscillator remains stopped after sub-watch release. the cpu is supplied with the selected sub clock?either sub oscillator or internal oscillator (see bit pcc.soscp). since the reset value of oscdis is 1 and pcc.soscp is 0 the cpu starts always with the internal oscillator clock after reset release. in both cases, the application software must start the main oscillator by clearing the oscdis bit. after the oscillator stabilization time has elapsed (see bit cgstat.oscstat), the main oscillator can be used as system clock source by setting the pcc register accordingly. ? watch mode this bit determines whether the main oscillator shall be stopped or remain in operation during watch mode. in either case after watch mode release the cpu is operating on the main oscillator. 0: main oscillator enable. the main oscillator is operating during watch mode. after watch mode release the cpu is supplied with the main oscillator clock. 1: main oscillator disable. the main oscillator is stopped during watch mode. after watch mode release the main oscillator is started and the cpu is supplied with the main oscillator clock, after the oscillation stabilization time has elapsed. note: in case the main oscillator is chosen as the cpu clock after power save mode release (i.e. after sub-watch mode release with oscdis = 0 or after watch mode release) the start-up phase of the cpu differs depending on the history of the main oscillator status indicator cgstat.oscstat. ? main oscillator never used before if the main oscillator has never been stable before entering and releasing power save mode (cgstat.oscstat has never been set to 1), the cpu starts operation on the internal oscillator. after the main oscillator has become stable, it is used as the cpu clock. ? main oscillator already used before if the main oscillator has already been stable before entering and releasing power save mode (cgstat.oscstat has already been set to 1), the cpu starts operation on main oscillator, after the main oscillator has become stable. table 4-18 psm register contents (2/3) bit position bit name function
171 clock generator chapter 4 user?s manual u17566ee5v1um00 1 to 0 psm[1:0] power save mode selection: psm1 psm0 power save mode 00 idle 01 stop 10 watch 11 sub-watch mode (main oscillator shut down) it is not possible to switch to idle or watch mode when the cpu is operated by a sub clock. if idle or watch mode is selected during sub clock operation, the sub- watch mode will be entered. table 4-18 psm register contents (3/3) bit position bit name function
172 chapter 4 clock generator user?s manual u17566ee5v1um00 (2) psc - power save control register the 8-bit psc register is used to enter or leave the power save mode specified in register psm. access this register can be read/written in 8-bit or 1-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?prcmd - psc write protection register? on page 173 for details. address ffff f1fe h . initial value 00 h . the register is cleared by any reset. note 1. if bits 7, 3, 2, and 0 are not set to 0, proper operation of the controller can not be guaranteed. 2. psc.stp is automatically cleared when the controller is awakened from power save mode. 3. entering a power save mode requires some attention, refer to ?power save mode activation? on page 191 . 76543210 0 nmiwdtm nmi0m intm 0 0 stp 0 r r/w r/w r/w r r r/w r table 4-19 psc register contents bit position bit name function 6 nmiwdtm mask for non-maskable interrupt request from wdt: 0: permit nmiwdt request during power save mode. 1: prohibit nmiwdt request during power save mode. 5 nmi0m mask for non-maskable interrupt request 0: 0: permit external nmi0 request during power save mode 1: prohibit external nmi0 request during power save mode. 4 intm mask for maskable interrupt request: 0: permit maskable interrupt requests during power save mode. a 1: prohibit maskable interrupt requests during power save mode. a) only dedicated maskable interrupts have wake-up capability, refer to ?power save modes description? on page 179 . 1 stp enter/release power save mode: 0: power save mode is released. 1: power save mode is entered.
173 clock generator chapter 4 user?s manual u17566ee5v1um00 (3) prcmd - psc write protection register the 8-bit prcmd register protects the register psc from inadvertent write access, so that the system does not stop in case of a program hang-up. after data has been written to the prcmd register, the first write access to register psc is valid. all subsequent write accesses are ignored. thus, the value of psc can only be rewritten in a specified sequence, and illegal write access is inhibited. access this register can only be written in 8-bit units. address ffff f1fc h initial value the contents of this register is undefined. caution before writing to prcmd, make sure that all dma channels are disabled. otherwise, a direct memory access could occur between the write access to prcmd and the write access to psc. if that happens, the power save mode may not be entered. caution in case a high level programming language is used, make sure that the compiler translates the two write instructions to prcmd and psc into two consecutive assembler ?store? instructions. 76543210 xxxxxxxx wwwwwwww
174 chapter 4 clock generator user?s manual u17566ee5v1um00 (4) stbctl- stand-by control register the 8-bit stbctl register is used to control the stand-by function of the voltage regulators. access this register can be read/written in 8-bit or 1-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?stbctlp - stand-by control protection register? on page 174 for details. address ffff fca2 h . initial value 00 h . the register is cleared by any reset. in order to reduce the power consumption during power save modes the stand- by function of the voltage regulators should be enabled during the initialization. if a dedicated microcontroller does not include any of the voltage regulators dedicated to the controls bit stbctl.stbycd andstbctl.stbymd, the status of the control bit has no function. thus the initialization for enabling the stand-by functions by stbctl = 03 h can be retained. for further details concerning voltage regulators refer to ?power supply scheme? on page 1 . (5) stbctlp - stand-by control protection register the 8-bit stbctlp register protects the register stbctl from inadvertent write access. after data has been written to the stbctlp register, the first write access to register stbctl is valid. all subsequent write accesses are ignored. thus, the value of stbctl can only be rewritten in a specified sequence, and illegal write access is inhibited. access this register can only be written in 8-bit units. address ffff fcaa h initial value the contents of this register is undefined. 76543210 000000stycdstbymd rrrrrrr/wr/w table 4-20 stbctl register contents bit position bit name function 1 stbycd enable stand-by function of vdd50 and vdd51 voltage regulators: 0: stand-by function disabled 1: stand-by function enabled 2 stbymd enable stand-by function of vdd52 voltage regulator: 0: stand-by function disabled 1: stand-by function enabled 76543210 xxxxxxxx wwwwwwww
175 clock generator chapter 4 user?s manual u17566ee5v1um00 4.2.5 clock monitor registers the following registers are used to control the monitor circuits of the main oscillator clock and the sub oscillator clock. please refer to ?operation of the clock monitors? on page 198 for supplementary information. (1) clmm - main oscillator clock monitor mode register the 8-bit clmm register is used to enable the monitor for the main oscillator clock. access this register can be read/written in 8-bit or 1-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?prcmdcmm - clmm write protection register? on page 176 for details. address ffff f870 h . initial value 00 h . this register is cleared by any reset. note clmm.clmem can be set at any time. however, the clock monitor is only activated after the main oscillator has stabilized, indicated by cgstat.oscstat = 1. 76543 2 1 0 00000 0 0clmem rrrrr r r r/w table 4-21 clmm register contents bit position bit name function 0 clmem clock monitor enable: 0: clock monitor for main oscillator disabled. 1: clock monitor for main oscillator enabled. this bit can only be cleared by reset.
176 chapter 4 clock generator user?s manual u17566ee5v1um00 (2) prcmdcmm - clmm write protection register the 8-bit prcmdcmm register protects the register clmm from inadvertent write access, so that the system does not stop in case of a program hang-up. after data has been written to the prcmdcmm register, the first write access to register clmm is valid. all subsequent write accesses are ignored. thus, the value of clmm can only be rewritten in a specified sequence, and illegal write access is inhibited. access this register can only be written in 8-bit units. address ffff fcb0 h initial value the contents of this register is undefined. after writing to the prcmdcmm register, you are permitted to write once to clmm. the write access to clmm must happen with the immediately following instruction. caution in case a high level programming language is used, make sure that the compiler translates the two write instructions to prcmdcmm and clmm into two consecutive assembler ?store? instructions. 76543210 xxxxxxxx wwwwwwww
177 clock generator chapter 4 user?s manual u17566ee5v1um00 (3) clms - sub oscillator clock monitor register the 8-bit clms register is used to enable the monitor for the sub oscillator clock. access this register can be read/written in 8-bit or 1-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?prcmdcms - clms write protection register? on page 177 for details. address ffff f878 h . initial value 00 h . the register is initialized by any reset. note setting clms.clmes to 1 does not start the sub oscillator clock monitor. to start the clock monitor clmcs.cmrt has to be set to 1 afterwards. clmcs.cmrt must not be set before the sub oscillator has stabilized. (4) prcmdcms - clms write protection register the 8-bit prcmdcms register protects the register clms from inadvertent write access, so that the system does not stop in case of a program hang-up. after data has been written to the prcmdcms register, the first write access to register clms is valid. all subsequent write accesses are ignored. thus, the value of clms can only be rewritten in a specified sequence, and illegal write access is inhibited. access this register can only be written in 8-bit units. address ffff fcb2 h initial value the contents of this register is undefined. after writing to the prcmdcms register, you are permitted to write once to clms. the write access to clms must happen with the immediately following instruction. caution in case a high level programming language is used, make sure that the compiler translates the two write instructions to prcmdcms and clms into two consecutive assembler ?store? instructions. 76543 2 1 0 00000 0 0clmes rrrrr r r r/w table 4-22 clms register contents bit position bit name function 0 clmes clock monitor enable: 0: clock monitor for sub oscillator disabled. 1: clock monitor for sub oscillator enabled. this bit can only be cleared by reset. 76543210 xxxxxxxx wwwwwwww
178 chapter 4 clock generator user?s manual u17566ee5v1um00 (5) clmcs - sub oscillator clock monitor control register the 8-bit clmcs register is used to start the monitor of the sub oscillator clock. access this register can be read/written in 8-bit or 1-bit units. address ffff f71a h . initial value 00 h . the register is initialized by any reset. setting clmcs.cmrt to 1 generates a trigger to activate the sub oscillator clock monitor. note 1. the sub oscillator clock monitor can only be started, if it has been enabled by setting clms.clmes to 1. 2. make sure that the sub oscillator stabilization time has elapsed before starting the clock monitor. caution starting the sub oscillator clock monitor requires a special procedure. refer to ?operation of the clock monitors? on page 198 . 76543 2 1 0 00000 0 0cmrt rrrrr r r r/w table 4-23 clmcs register contents bit position bit name function 0 cmrt sub oscillator clock monitor start: 0: clock monitor for sub oscillator off. 1: clock monitor for sub oscillator on.
179 clock generator chapter 4 user?s manual u17566ee5v1um00 4.3 power save modes this chapter describes the various power save modes and how they are operated. for details see: ? ?power save modes description? on page 179 ? ?power save mode activation? on page 191 ? ?cpu operation after power save mode release? on page 193 4.3.1 power save modes description this section explains the various power save modes in detail. during power save mode during all power save modes, the pins behave as follows: ? all output pins retain their function. that means all outputs are active, provided the required clock source is available. ? all input pins remain as input pins. ? all input pins with stand-by wake-up capability remain active, the function of all others is disabled. during all power save modes, the main and sub oscillator clock monitors remain active, provided that the monitored oscillator is operating. if the oscillator is switched off during stand-by, the associated clock monitor enters stand-by as well. wake-up signals the following signals can awake the controller from power save modes idle, watch, sub-watch, stop: ? reset signals ? external reset ? power-on-clear reset respoc ? watchdog timer reset reswdt the watchdog timer must be configured to generate the reset wdtres in case of overflow (wdtm.wdtmode = 1) and it?s input clock wdtclk must be active during stand-by. ? clock monitors resets rescmm, rescms the main oscillator respectively sub oscillator must be active during stand-by. ? non maskable interrupts ?nmi0 the appropriate port must be configured correctly. ?nmiwdt the watchdog timer must be configured to generate the in case of overflow (wdtm.wdtmode = 0) and it?s input clock wdtclk must be active during stand-by. ? maskable interrupts ? external interrupts intpn the appropriate port must be configured correctly. ? can wake up interrupts intcnwup the appropriate port and the can (cnctrl.psmode[1:0] = 01 b ) must be configured correctly.
180 chapter 4 clock generator user?s manual u17566ee5v1um00 ? watch timer interrupts intwtnuv the watch timer clock wtclk must be active and the watch timer must be enabled. ? watch calibration timer interrupt inttm01 the watch calibration timer clock wctclk must be active and the watch calibration timer must be enabled. ? voltage comparators interrupts intvcn the voltage comparators must be enabled. ? csib receive interrupts intcbnr the csib must be operated in slave reception mode and the appropriate ports must be configured correctly. note that not all these signals are available in all power save modes. the following signals can awake the controller from the power save mode halt, provided the appropriate ports and modules are correctly configured and the required clocks are active: ? all reset signals ? the non-maskable interrupts nmi0, nmiwdt ? all maskable interrupts to grant wake-up capability to maskable interrupts these interrupts have to be unmasked by setting the dedicated mask flags xxmk to 0 (refer to ?interrupt controller (intc)? on page 201 ). a general disable of maskable interrupts acknowledgement (?di?, i.e. psw.id = 1) does not affect their wake-up capability. after power save mode after power save mode release, the clock source for cpu operation should be checked. if the user application issues a wake-up request immediately after power save mode request, the power save mode may not be entered and the clock sources remain as programmed before the stand-by request. after power save mode release, the same procedure as for system reset is required to set up the clock supply for the application. note in the following tables the clock status "operates" does not necessarily mean that the functions that use this clock source are operating as well.
181 clock generator chapter 4 user?s manual u17566ee5v1um00 (1) halt mode the halt mode can be entered from normal run mode. in halt mode, all clock settings remain unchanged. only the cpu clock is suspended and hence program execution. the halt mode can be released by any unmasked maskable interrupt, nmi or system reset. on halt mode release, all clock settings remain unchanged. the cpu clock resumes operation. table 4-24 clock generator status in halt mode item status remarks main oscillator unchanged sub oscillator operates internal oscillator operates sscg unchanged pll unchanged vbclk (cpu system) suspended clock setup is unchanged iiclk unchanged pclk0, pclk1 unchanged pclk2?pclk15 unchanged spclk0, spclk1 unchanged spclk2?spclk15 unchanged foutclk unchanged wtclk / lcdclk unchanged wdtclk unchanged wctclk unchanged
182 chapter 4 clock generator user?s manual u17566ee5v1um00 (2) idle mode the idle mode can be entered from any run mode. the main oscillator must be operating. idle mode can not be entered if the cpu is clocked by the sub or internal oscillator. in idle mode, the clock distribution is stopped (refer to the ?standby? switches in figure 4-1, ?block diagram of the clock generator,? on page 140 ). the states of all clock sources, that means, sub and internal oscillator as well as sscg and pll, remain unchanged. if a clock source was operating before entering idle mode, it continues operating. the idle mode can be released by ? the unmasked maskable interrupts intpn, intcnwup, intwtnuv, inttm01, intvcn, intcbnr ? nmi0, nmiwdt ?reset , respoc, reswdt, rescmm, rescms on idle mode release, the cpu clock and peripheral clocks are supplied by the main oscillator. table 4-25 clock generator status in idle mode item status remarks main oscillator unchanged sub oscillator operates internal oscillator operates sscg unchanged pll unchanged vbclk (cpu system) stopped iiclk stopped pclk0, pclk1 stopped pclk2?pclk15 stopped spclk0, spclk1 stopped spclk2?spclk15 stopped foutclk unchanged wtclk / lcdclk unchanged wdtclk unchanged wctclk unchanged/stopped depends on clock selector psm.cmode
183 clock generator chapter 4 user?s manual u17566ee5v1um00 (3) watch mode in watch mode, the clock supply for the cpu system and the majority of peripherals is stopped. the main oscillator continues operation. pll and sscg are stopped. by default, internal oscillator and sub oscillator operation is not affected. for exceptions see ?internal and sub oscillator operation? on page 196 . the watch mode can be released by ? the unmasked maskable interrupts intpn, intcnwup, intwtnuv, inttm01, intvcn, intcbnr ? nmi0, nmiwdt ?reset , respoc, reswdt, rescmm, rescms on watch mode release, the cpu starts operation using the following clocks: ? if psm.oscdis = 1: sub clock source selected before watch mode was entered, that means, either internal oscillator or sub oscillator (defined by pcc.soscp) ? if psm.oscdis = 0: main oscillator if the internal oscillator was stopped before entering the watch mode, the oscillation stabilization time for the internal oscillator is ensured by hardware after watch mode release. pll and sscg remain stopped after watch release. peripheral clock supply is switched to main oscillator supply, if psm.oscdis = 0, otherwise the internal oscillator is used for peripheral clocks. table 4-26 clock generator status in watch mode item status remarks main oscillator unchanged/stopped stopped if psm.oscdis = 1 sub oscillator operates internal oscillator operates/stopped stopped if wcc.rostp = 1 sscg stopped pll stopped vbclk (cpu system) stopped iiclk stopped pclk0, pclk1 stopped pclk2?pclk15 stopped spclk0, spclk1 stopped spclk2?spclk15 stopped foutclk unchanged/stopped stopped, if the selected clock source stops wtclk / lcdclk unchanged/stopped stopped, if the selected clock source stops wdtclk unchanged/stopped stopped, if the selected clock source stops wctclk unchanged/stopped depends on clock selector psm.cmode
184 chapter 4 clock generator user?s manual u17566ee5v1um00 (4) sub-watch mode in sub-watch mode, the clock supply for the cpu and the majority of peripherals is stopped. main oscillator, pll, and sscg are stopped. by default, internal oscillator and sub oscillator operation is not influenced. for exceptions see ?internal and sub oscillator operation? on page 196 . the sub-watch mode can be released by ? the unmasked maskable interrupts intpn, intcnwup, intwtnuv, intvcn, intcbnr ? nmi0, nmiwdt ?reset , respoc, reswdt, rescmm, rescms on sub-watch mode release, the cpu starts operation using the following clocks: ? if psm.oscdis = 1: sub clock source selected before sub-watch mode was entered, that means, either internal oscillator or sub oscillator (defined by pcc.soscp) ? if psm.oscdis = 0: main oscillator if the internal oscillator was stopped before entering the sub-watch mode, the oscillation stabilization time for the internal oscillator is ensured by hardware after sub-watch release. pll and sscg remain stopped after sub-watch release. peripheral clock supply is switched to main oscillator supply, if psm.oscdis = 0, otherwise the internal oscillator is used for peripheral clocks. table 4-27 clock generator status in sub-watch mode item status remarks main oscillator stopped sub oscillator operates internal oscillator operates/stopped stopped if wcc.rostp = 1 sscg stopped pll stopped vbclk (cpu system) stopped iiclk stopped pclk0, pclk1 stopped pclk2?pclk15 stopped spclk0, spclk1 stopped spclk2?spclk15 stopped foutclk unchanged stopped, if the selected clock source stops wtclk / lcdclk unchanged stopped, if the selected clock source stops wdtclk unchanged/stopped stopped, if the selected clock source stops wctclk stopped
185 clock generator chapter 4 user?s manual u17566ee5v1um00 (5) stop mode in stop mode, all clock sources are stopped, except sub and internal oscillator. these can be configured in register wcc to stop as well. no clock is available, and no internal self-timed processes operates. the stop mode can be released by ? the unmasked maskable interrupts intpn, intcnwup, intvcn, intcbnr ? nmi0, nmiwdt ?reset , respoc, reswdt, rescmm, rescms on stop mode release, the cpu clock and peripheral clocks are supplied by the main oscillator. (6) clock status summary table 4-29 on page 186 summarizes the status of all clocks delivered by the clock generator in the different states. ?normal? describes all status except reset and power save modes. the halt mode is not listed in the table. it does not change any of the table items, but stops only the cpu core operation. below the table you find the explanation of the terms used in the table. table 4-28 clock generator status in stop mode item status remark main oscillator stopped sub oscillator operates/stopped stopped if wcc.sostp = 1 internal oscillator operates/stopped stopped if wcc.rostp = 1 sscg stopped pll stopped vbclk (cpu system) stopped iiclk stopped pclk0, pclk1 stopped pclk2?pclk15 stopped spclk0, spclk1 stopped spclk2?spclk15 stopped foutclk stopped wtclk / lcdclk stopped wdtclk unchanged/stopped stopped, if the selected clock source stops wctclk stopped
186 chapter 4 clock generator user?s manual u17566ee5v1um00 table 4-29 status of oscillators and clock generator output clocks (1/2) macro clock signal condition reset reset release normal idle idle release stop stop release watch watch release sub- watch sub- watch oscillators main-osc ? oscdis=0 n.a. on on stop on on on stop on oscdis=1 stop stop n.a. stop n.a. stop sub-osc ? sostp=1 n.a. on on stop on on on sostp=0 on on internal-osc ? rostp=1 n.a. on on stop on stop on stop on rostp=0 on on on on sscg/pll sscg ? ? stby scen scen stby stby stby pll ? ? pllen pllen clock generator output clocks cpu system clock vbclk cls/cks = 000 b n.a. moclk off moclk off moclk off moclk off moclk cls/cks = 001 b sscclk n.a. n.a. n.a. n.a. cls/cks = 01x b pllclk n.a. n.a. n.a. n.a. cls/cks = 1xx b off roclk sbclk n.a. n.a. n.a. sbclk peripheral clocks pclk0 pclk1 peric=0 off moclk a moclk off moclk off moclk off moclk off moclk peric=1 n.a. pllclk pllclk n.a. n.a. n.a. pclk2 - pclk15 ? off moclk a moclk off moclk off moclk off moclk off moclk spclk0 spclk1 spsel[1:0]=00 b off moclk a moclk off moclk off moclk off moclk off moclk spsel[1:0]=01 b n.a. pllclk pllclk n.a. n.a. n.a. spsel[1:0]=11 b sscclk sscclk n.a. n.a. n.a. spclk2 - spclk15 spsel1=0 off moclk a moclk off moclk off moclk off moclk off moclk spsel1=1 n.a. pllclk pllclk n.a. n.a. n.a.
187 clock generator chapter 4 user?s manual u17566ee5v1um00 watch calibration timer wctclk cmode=0 off moclk a pclk1 off pclk1 off pclk1 off pclk1 off pclk1 cmode=1 n.a. moclk moclk moclk moclk moclk moclk moclk watchdog timer wdtclk sosc=0 wdtsel0=0 wdtsel1=0 off rosck rosck off rosck off rosck off rosck off rosck wdtsel1=1 n.a. rosck rosck (off b ) rosck (off b ) rosck (off b ) sosc=1 wdtsel0=0 wdtsel1=0 n.a. soclk off soclk off soclk off soclk off soclk wdtsel1=1 soclk soclk (off b ) soclk soclk sosc=x wdtsel0=1 wdtsel1=0 n.a. moclk off moclk off moclk off moclk off moclk wdtsel1=1 moclk moclk i 2 c iiclk iicsel[1:0]=00 b off moclk a moclk off moclk off moclk off moclk off moclk iicsel[1:0]=01 b n.a. sscsck sscsck n.a. n.a. n.a. iicsel[1:0]=1x b pllsck pllsck n.a. n.a. n.a. watch timer lcd-c/d wtclk lcdclk wtsos/wtsel0=00 b rosck rosck rosck rosck (off b ) rosck rosck (off b ) rosck rosck (off b ) rosck wtsos/wtsel0=10 b n.a. soclk soclk soclk (off b ) soclk soclk soclk soclk soclk wtsos/wtsel0=x1 b moclk moclk off moclk moclk (off c ) moclk moclk (off c ) moclk port foutclk fosos/focks1/0=x00 b off moclk moclk moclklcd-c/d moclk moclk fosos/focks1/0=x01 b n.a. sscclk sscclk sscclk sscclk sscclk fosos/focks1/0=x10 b pllclk pllclk pllclk pllclk pllclk fosos/focks1/0=011 b roclk roclk roclk roclk roclk fosos/focks1/0=111 b soclk soclk soclk soclk soclk a) after reset release these clocks are supplied with the internal roclk. when the main oscillator is stable, these clocks are aut omatically changed to moclk. b) roclk (soclk) remains clock source, but internal oscillator (sub oscillator) may be stopped in the respective power save mode b y wcc.rostp = 1 (wcc.sostp = 1). c) mosclk remains clock source, but main oscillator may be stopped in the respective power save mode by psm.oscdis = 1. table 4-29 status of oscillators and clock generator output clocks (2/2) macro clock signal condition reset reset release normal idle idle release stop stop release watch watch release sub- watch sub- watch
188 chapter 4 clock generator user?s manual u17566ee5v1um00 in the table following terms are used: stop: oscillator stopped moclk: main oscillator clock on: oscillator operating roclk: internal oscillator clock stby: pll/sscg in standby, no clock output soclk: sub oscillator clock pllen/scen: pll/sscg generates clock output sbclk: sub clock ? pcc.soscp = 0: roclk ? pcc.soscp = 1: soclk off: clock inactive pllclk: pll output clock n.a. not applicable (control bits are deter- mined by hardware) sscgclk: sscg output clock
189 clock generator chapter 4 user?s manual u17566ee5v1um00 4.3.2 clock generator state transitions (1) vbclk state transitions psm states sscg vbclk = sscclk watch mode mainosc = unchanged/off subosc = on intosc = on/off psm[1:0] = 00 b psm[1:0] = 10 b psm entry psm entry pll vbclk = pllclk (x4 or x8) sub-clock vbclk = sbclk pcc.soscp = 0: sbclk = roclk 1: sbclk = soclk mainosc pcc write prohibited vbclk = moclk mainosc pcc write permitted vbclk = moclk idle mode mainosc = unchanged/off subosc = on intosc = on/off sub-watch mode mainosc = on/off subosc = on intosc = on/off stop mode mainosc = off subosc = on intosc = on/off psm[1:0] = 01 b psm entry psm entry psm entry wake-up oscdis = 1 reset cls = 1 soscp = 0 sdc.sdcr = 1 oscdis = 1 oscdis = 0 oscdis = 0 wake-up psm[1:0] = 11 b vbclk states cls = 0, cks[1:0] = 1x b cls = 0, cks[1:0] = 01 b cls = 0, cks[1:0] = 00 b oscdis = 1
190 chapter 4 clock generator user?s manual u17566ee5v1um00 (2) main oscillator state transitions (3) internal oscillator states (4) sub oscillator states mainosc stabilization reset mainosc operating mainosc started by f/w stabilization counter expired mainosc stopped psm release from - stop (psm[1:0] = 01 b ) - sdc.sdcr = 1 and oscdis = 0 psm release from - sub-watch (psm[1:0] = 11 b ) and oscdis = 0 - watch (psm[1:0] = 10 b ) - sdc.sdcr = 1 and oscdis = 0 psm entry with - psm[1:0] = 01 b (stop) - psm[1:0] = 11 b (sub-watch) - psm[1:0] = 10 b (watch) and oscdis = 1 - sdc.sdcr = 1 psm release from - sub-watch (psm[1:0] = 11 b ) and oscdis = 1 - sdc.sdcr = 1 and oscdis = 1 intosc operating reset intosc stopped psm release psm entry with - psm[1:0] = 01 b (stop) and rostp = 1 - psm[1:0] = 11 b (sub-watch) and rostp = 1 - psm[1:0] = 10 b (watch) and rostp = 1 subosc operating reset subosc stopped psm release psm entry with -psm[1:0] = 01 b (stop) and scstp = 1
191 clock generator chapter 4 user?s manual u17566ee5v1um00 4.3.3 power save mode activation in the following procedures for securely entering a power save mode are described. stepper-c/d shut down in order to minimize power consumption during power save modes the stepper motor controller/driver needs to be shut down in a special sequence. refer to ?mcntcn0, mcntcn1 - timer mode control registers? on page 887 . (1) halt mode for entering the halt mode proceed as follows: 1. mask all interrupts which shall not have wake-up capability by xxic.xxmk = 1 and discard all possibly pending interrupts by xxic.xxif = 0. 2. unmask all interrupts which shall have wake-up capability by xxic.xxmk = 0. 3. execute the ?halt? instruction. 4. insert at least five ?nop? instruction after the ?halt? instruction. (2) watch, sub-watch, stop and idle mode for entering these power save mode proceed as follows: 1. in case maskable interrupts shall be used for wake-up unmask these interrupts by imrm.xxmk = 0 (refer to ?imr0 to imr6 - interrupt mask registers? on page 252 ). 2. mask all other interrupts, i.e. ? none wake-up capable interrupts ? wake-up capable interrupts which shall not be used for wake-up by imrm.xxmk = 1. this prevents the power save mode entry procedure from being interrupted by these interrupts. 3. it is recommended to disable interrupt acknowledgement by the ?di? instruction. 4. specify the desired power save mode in psm.psm[1:0]. 5. enable writing to the write-protected register psc by writing to prcmd. 6. write to psc for specifying permitted wake-up events and activate the power save mode by setting psc.stp to 1. example the following example shows how to initialize and enter a watch, sub- watch, stop or idle power save mode. first the desired power save mode is specified (watch mode in this example, that means psm.psm[1:0] = 10 b ). the psc register is a write-protected register, and the prcmd register is the corresponding write-enable register. prcmd has to be written immediately before writing to psc.
192 chapter 4 clock generator user?s manual u17566ee5v1um00 in this example, maskable interrupts are permitted to leave the power save mode. be aware of the following notes when entering power save mode using the above sequence: note 1. it is recommended to disable maskable interrupt acknowledgement in general by the ?di? instruction (step 3.) to prevent any pending interrupt from being served during the power save mode set-up procedure. this makes it also possible to completely control the process after wake-up, since no pending interrupt will be unintentional acknowledged. before enabling interrupt acknowledgement by the ?ei? instruction (step 16.) after wake-up, all unwanted interrupts can be discarded by setting xxic.xxif = 0 (step 15.). since the wake-up capability of the unmasked wake-up interrupts is not affected by ?di?, such interrupts shall be masked (step 1.) by imrm.xxmk = 1. 2. the store instruction to prcmd will not allow to acknowledge any interrupt until processing of the subsequent instruction is complete. that means, an interrupt will not be acknowledged before the store to psc. this presupposes that both store instructions are performed consecutively, as shown in the above example. if another instruction is placed between steps 7 and 8, an interrupt request may be acknowledged in between, and the power save mode may not be entered. however if the ?di? instruction was executed before (step 3.) none interrupt will be acknowledged anyway. 3. at least 5 ?nop? instructions must follow the power down mode setting, that means after the write to psc. the microcontroller requires this time to enter power down mode. 4. the data written to the prcmd register must be the same data that shall be written to the write-protected register afterwards. the above example ensures this method, since the contents of r10 is first written to prcmd and then immediately to psc. 1. // xxic.xxmk = 0 // mask all none wake-up interrupts 2. // xxic.xxmk = 1 // unmask all wake-up interrupts 3. di 4. mov 0x02,r10 5. st.b r10,psm[r0] // psm.psm[1:0] = 10b: watch mode 6. mov 0x62,r10 7. st.b r10,prcmd[r0] // enable write to psc 8. st.b r10,psc[r0] // wake up by maskable interrupts // and enter power save mode 9. nop 10. nop 11. nop 12. nop 13. nop 14. // after wake-up 15. // xxic.xxif = 0 // discard all unwanted pending interrupts 16. ei
193 clock generator chapter 4 user?s manual u17566ee5v1um00 5. make sure that all dma channels are disabled. otherwise a dma could happen between steps 7 and 8, and the power down mode may not be entered at all. further on do not perform write operations to prcmd and write-protected registers by dma transfers. 6. no special sequence is required for reading the psc register. caution if a wake-up event occurs within the 5 ?nop? instructions after a power save mode request (psc.stp = 1) the microcontroller is immediately returning from power save mode, but may have not at all or only partly entered the power save mode. following three situations can occur: 1. power save mode request not accepted wake-up configuration not established, pll/sscg are operating 2. power save mode request accepted, but not completed wake-up configuration established, but pll/sscg operating 3. power save mode request accepted and completed wake-up configuration established, pll/sscg stopped 4.3.4 cpu operation after po wer save mode release clock generator re- configuration the clock for the cpu system can be switched only once after reset, power save mode release, or the default clock setup request (sdc.sdcr = 1). the clocks for the watchdog timer, watch timer, and lcd controller/driver can be switched only once after system reset. access to peripherals that have no clock supply in sub-watch mode may cause system deadlock. this can happen if the main oscillator remains disabled. wake-up configuration wake-up configuration established means that all registers and clock paths are set to their wake-up state. the software should check after wake-up whether the expected wake-up configuration has been completely established. this can be achieved by observing ? following clock generator registers, which are modified by power save mode entry and wake-up ? after watch, sub-watch, stop wake-up following bits are cleared: ckc.pllen, ckc.scen, ckc.peric, scc.sel, icc.sel ? after idle or stop wake-up following bits are cleared: pcc.cls, pcc.cks ? after sub-watch or watch wake-up pcc.cls/pcc.cks = 000 b , if psm.oscdis = 0 pcc.cls/pcc.cks = 100 b , if psm.oscdis = 1 ? the ?completed power save mode? bit cgstat.cmplpsm ? cgstat.cmplpsm = 0 if a power save mode request has been accepted but not completed, wake-up configuration established, but pll/
194 chapter 4 clock generator user?s manual u17566ee5v1um00 sscg operating (provided that cgstat.cmplpsm = 1 before power save mode request) ? cgstat.cmplpsm = 1 if a power save mode has been completely entered, wake-up configuration established, pll/sscg stopped (provided that a power save mode request has been accepted before, i.e. cgstat.cmplpsm = 1  0) note that cgstat.cmplpsm is set to 0 if a power save mode request is accepted. if it was 0 before it does not change it?s state. ta b l e 4 - 3 0 summarizes the different configurations. table 4-30 power save mode wake-up configurations if the power save mode request was accepted the entire clock generator can be reconfigured after wake-up. afterwards set ckc.pllen = 1 and ckc.scen = 1 and wait the stabilization times before using the pll and sscg as clock sources. set default clock if the power save mode wake-up configuration is entered by setting sdc.sdcr = 1 all registers and clock paths settings are performed, but the pll and sscg are still operating, that means cgstat.psm remains unchanged. the entire clock generator can be reconfigured, i.e. all registers can be written. if the sscg configuration shall not be changed, set ckc.pllen = 1 and ckc.scen = 1. the sscg respectively pll can be used immediately as clock sources without waiting the stabilization times. if the sscg configuration shall be changed, rewrite the sscg configuration registers, set ckc.pllen = 1 and ckc.scen = 1. in this case make sure the stabilization times has elapsed before using the pll or sscg as clock sources. cgstat.cmplpsm registers and clock paths a a) a change of a register?s contents can only be taken as an indicator if it is before power save mode request different to the wake-up configuration. configuration after wake-up before psm-rq b b) psm-rq: power save mode request (psc.stp = 1) after wake-up 0 0 not changed psm-rq not accepted changed psm-rq accepted configuration done, but pll/ sscg operating 1 not changed not possible changed psm-rq accepted configuration done, pll/sscg off 1 0 not changed not possible changed psm-rq accepted configuration done, but pll/ sscg operating 1 not changed psm-rq not accepted changed psm-rq accepted configuration done, pll/sscg off
195 clock generator chapter 4 user?s manual u17566ee5v1um00 after idle and stop on return from idle or stop mode, the bits pcc.cls, pcc.cks1, and pcc.cks2 are cleared. after idle mode, the main oscillator is still running; on return from stop mode, it is automatically started. as a result, the main oscillator is chosen and enabled as the source for the cpu system clock vbclk. after watch in watch mode the main oscillator operation depends on psm.oscdis: ? if psm.oscdis was 0 before entering watch mode the main oscillator remains active. after watch mode release the main oscillator is chosen as the cpu system clock. ? if psm.oscdis was 1 before entering watch mode the main oscillator is stopped during watch mode. after watch mode release the main oscillator is automatically started, the oscillator stabilization time is waited and the main oscillator is chosen as the cpu system clock. after sub-watch in sub-watch mode the main oscillator is stopped. on return from sub- watch, pcc.cls is set to the status of psm.oscdis. ? if psm.oscdis was 0 before entering sub-watch, the main oscillator is started and chosen as the source for the cpu system clock (pcc.cls = 0, pcc.cks[1:0] = 00 b ). ? if psm.oscdis was 1 before entering sub-watch, the main oscillator remains stopped, and the cpu is clocked by a sub clock (pcc.cls = 1, pcc.cks[1:0] = xx b ). ?sub clock? means the clocks supplied by either the 32 khz sub oscillator or the 200 khz internal oscillator. the selection must be made in the pcc register before entering the sub-watch or watch mode: ? pcc.soscp = 0: internal oscillator ? pcc.soscp = 1: sub oscillator software can switch from sub clock cpu operation to normal run mode (by enabling the main oscillator by psm.oscdis = 0) or re-enter sub-watch respectively watch mode. after halt on return from halt mode the cpu resumes operation with the same clock settings as before halt was entered.
196 chapter 4 clock generator user?s manual u17566ee5v1um00 4.4 clock generator operation 4.4.1 internal and sub oscillator operation by default, sub and internal oscillator operate during all power save modes. however, it can be specified in the wcc register that the sub oscillator stops in stop mode (wcc.sostp). it can also be specified that the internal oscillator stops in watch, sub- watch, and stop mode (wcc.rostp). these bits can be written once after system reset, independent of the reset source. 4.4.2 watch timer and watc h calibration timer clocks the watch timer input clock wtclk can be derived directly from the main, sub, or internal oscillator. therefore, the wt can be operating in all power save modes. because pclk1 is stopped during power save modes, the watch calibration timer input clock wctclk can be directly connected to the main oscillator output. note wctclk is not available in sub-watch and stop mode where the main oscillator is stopped. these modes must be released before the wct can operate. 4.4.3 clock output foutclk the clock generator output signal foutclk supplies a clock for external components. it can be derived from any internal clock source, that means internal oscillator, sub oscillator, main oscillator, pll, or sscg.a dedicated frequency divider is available to scale the output clock down. foutclk must be enabled by register setting (fcc.foen = 1). it is not influenced by the power save modes. but foutclk stops, if the selected clock source stops. after reset release, foutclk is disabled (register fcc is cleared), and the pin fout put in input mode. note 1. if you change the configuration of foutclk or enable/disable the selected clock source while foutclk is active, glitches or irregular clock periods may appear at the output pin. 2. the clock signal foutclk cannot be used to synchronize external circuitry to other output signals of the microcontroller?it has no specified phase relation to other output signals. 3. there is an upper frequency limit for the output buffer of the foutclk function. do not select a frequency higher than the maximum output buffer frequency. please refer to the data sheet for the frequency limit.
197 clock generator chapter 4 user?s manual u17566ee5v1um00 4.4.4 default clock generator setup the clock generator can be reset to the clock settings that are used by default after power save mode release. this is done by setting bit sdc.sdcr. for this kind of reset, it is not necessary to enter a power save mode, and no wake-up signal is required. if reset to defaults is requested, ckc.pllen and ckc.scen are cleared. however the pll and sscg remain active. the cpu clock source is switched to sub, internal, or main oscillator (depending on the bits psm.oscdis and pcc.soscp). peripheral clock sources are switched to main oscillator. for details see ?sdc - set default clock register? on page 154 . this feature reduces the total power consumption of peripherals and cpu. it provides also a way to stop the pll and sscg. these plls must be stopped if the clock sources for the cpu or peripherals shall be changed. note while the clock sources are switched, the peripheral clocks are suspended. therefore, the timing of peripheral modules may be inaccurate until the reset has finished.
198 chapter 4 clock generator user?s manual u17566ee5v1um00 4.4.5 operation of the clock monitors the microcontroller provides two separate clock monitors to watch the activity of the main oscillator and the sub oscillator. (1) description the functional block diagram is shown below. figure 4-2 clock monitors block diagram the clock monitors use the internal oscillator (f r ) for monitoring the main and sub oscillators (f m ). if the main oscillator clock monitor detects a malfunction of the main oscillator (no pulse), it generates the reset request rescmm. if the sub oscillator clock monitor detects a malfunction of the sub oscillator, it generates the reset request rescms. (2) start and stop before the clock monitors can be started, they have to be enabled by setting clmm.clmem and clms.clmes to 1. main oscillator monitor start after enabling clmm.clmem = 1 the main oscillator monitor is automatically started as soon as the main oscillator is stable, indicated by cgstat.oscstat = 1. sub oscillator monitor start after enabling clmm.clmes = 1 the sub oscillator monitor must be started by software by setting clmcs.cmrt to 1. after starting the sub oscillator clock monitor by clmcs.cmrt = 1 clear clmcs.cmrt by software. main osc cgstat.oscstat start f m f r en clkm_main output clmm.clmem rescmm sub osc clmcs.cmrt start f m f r en clkm_sub output clms.clmes rescms internal osc
199 clock generator chapter 4 user?s manual u17566ee5v1um00 since clmcs.cmrt = 1 is synchronized with the internal oscillator any change of this bit has to be maintained for at least 65 internal oscillator periods t rosc =1/f rosc to become effective. therefore a wait period has to be assured before this bit is changed again. proceed as follows to start the sub oscillator clock monitor: 1. after reset enable sub oscillator clock monitor: prcmdcm = ff h permit write to clms clms.clmes = 1enable sub oscillator clock monitor 2. make sure the sub oscillator is stable. 3. start sub oscillator clock monitor after reset and after power save mode wake-up: clmcs.cmrt = 1 4. wait for 65 internal oscillator periods t rosc before resetting cmrt: wait (65 x max(t rosc )) 5. clear clmcs.cmrt: clmcs.cmrt = 0 6. before cmrt should be set to 1 again, wait for 65 internal oscillator periods t rosc : wait (65 x max(t rosc )) note that the minimum internal oscillator frequency min(f rosc ) (max(t rosc )) has to be taken into account for the wait time in steps (3) and (5). caution the sub oscillator clock monitor is sometimes already started by setting clms.clmes = 1, i.e. without clmcs.cmrt = 1. in these cases it would not be required to start the sub oscillator by setting clmcs.cmrt = 1 additionally. since it is unpredictable whether the clock monitor has already started after clms.clmes = 1 the procedure described above should be followed in any case. (3) operation during and after power save modes main oscillator stopped if the main oscillator is stopped, its clock monitor changes to stand-by. when the main oscillator is restarted after power save mode release, the main oscillator clock monitor restarts automatically. sub oscillator stopped if the sub oscillator is stopped, its clock monitor stops. when the sub oscillator is restarted after power save mode release, the sub oscillator clock monitor does not start automatically. software must ensure that the sub oscillator stabilization time has elapsed and then start the monitor by setting clmcs.cmrt to 1. internal oscillator stopped if the internal oscillator is stopped, both clock monitors? operation is suspended. their operation is automatically resumed as soon as the internal oscillator is restarted.
200 chapter 4 clock generator user?s manual u17566ee5v1um00
201 user?s manual u17566ee5v1um00 chapter 5 interrupt controller (intc) this controller is provided with a dedicated interrupt controller (intc) for interrupt servicing and can process a large amount of maskable and two non- maskable interrupt requests. an interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution. generally, an exception takes precedence over an interrupt. this controller can process interrupt requests from the on-chip peripheral hardware and external sources. moreover, exception processing can be started by the trap instruction (software exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). eight levels of software-programmable priorities can be specified for each interrupt request. starting of interrupt servicing takes no fewer than 5 system clocks after the generation of an interrupt request. 5.1 features ? interrupts ? non-maskable interrupts: 2 sources ? maskable interrupts: ? 8 levels of programmable priorities (maskable interrupts) ? multiple interrupt control according to priority ? masks can be specified for each maskable interrupt request ? noise elimination, edge detection and valid edge specification, level detection for external interrupt request signals ? wake-up capable (analogue noise elimination for external interrupt request signals) ? nmi and intp0 share the same pin ? exceptions ? software exceptions: 2 channels with each 16 sources ? exception traps: 2 sources (illegal opcode exception and debug trap) interrupt source pd70f3421, pd70f3422, pd70f3423 pd70f3424, pd70f3425, pd70f3426a, pd70f3427 internal peripherals 69 85 external 7 8 software 2 2
202 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 table 5-1 interrupt/exception source list (1/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit reset interrupt reset reset input pin ? 0000h 00000000h undef. non- maskable interrupt nmi0 nmi input port ? 0010h 00000010h nextpc nmiwdt watchdog timer wdt ? 0020h 00000020h nextpc nmi2 unused ? ? 0030h 00000030h nextpc software exception exception trap0n (n = 0 to f h ) trap instruction ?? 004nh (n = 0 to f h ) 00000040h nextpc exception trap1n (n = 0 to f h ) trap instruction ?? 005nh (n = 0 to f h ) 00000050h nextpc exception trap exception ilgop/ dbtrap illegal opcode/ dbtrap instruction ? ? 0060h 00000060h nextpc maskable interrupt intvc0 voltage comparator 0 ac0 0 0080h 00000080h next pc interrupt intvc1 voltage comparator 1 ac1 1 0090h 00000090h next pc interrupt intwt0uv wt0 underflow wt0 2 00a0h 000000a0h next pc interrupt intwt1uv wt1 underflow wt1 3 00b0h 000000b0h next pc interrupt reserved reserved ? 4 00c0h 000000c0h next pc interrupt inttm01 watch calibration timer capture compare wct 5 00d0h 000000d0h next pc interrupt intp0 external interrupt 0 port 6 00e0h 000000e0h next pc interrupt intp1 external interrupt 1 port 7 00f0h 000000f0h next pc interrupt intp2 external interrupt 2 port 8 0100h 00000100h next pc interrupt intp3 external interrupt 3 port 9 0110h 00000110h next pc interrupt intp4 external interrupt 4 port 10 0120h 00000120h next pc interrupt intp5 external interrupt 5 port 11 0130h 00000130h next pc interrupt intp6 external interrupt 6 port 12 0140h 00000140h next pc interrupt inttz0uv tmz0 underflow tmz0 13 0150h 00000150h next pc interrupt inttz1uv tmz1 underflow tmz1 14 0160h 00000160h next pc interrupt inttz2uv tmz2 underflow tmz2 15 0170h 00000170h next pc interrupt inttz3uv tmz3 underflow tmz3 16 0180h 00000180h next pc interrupt inttz4uv tmz4 underflow tmz4 17 0190h 00000190h next pc interrupt inttz5uv tmz5 underflow tmz5 18 01a0h 000001a0h next pc interrupt inttp0ov tmp0 overflow tmp0 19 01b0h 000001b0h next pc interrupt inttp0cc0 tmp0 capture compare channel 0 tmp0 20 01c0h 000001c0h next pc interrupt inttp0cc1 tmp0 capture compare channel 1 tmp0 21 01d0h 000001d0h next pc interrupt inttp1ov tmp1 overflow tmp1 22 01e0h 000001e0h next pc interrupt inttp1cc0 tmp1 capture compare channel 0 tmp1 23 01f0h 000001f0h next pc interrupt inttp1cc1 tmp1 capture compare channel 1 tmp1 24 0200h 00000200h next pc interrupt inttp2ov tmp2 overflow tmp2 25 0210h 00000210h next pc
203 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 maskable interrupt inttp2cc0 tmp2 capture compare channel 0 tmp2 26 0220h 00000220h next pc interrupt inttp2cc1 tmp2 capture compare channel 1 tmp2 27 0230h 00000230h next pc interrupt inttp3ov tmp3 overflow tmp3 28 0240h 00000240h next pc interrupt inttp3cc0 tmp3 capture compare channel 0 tmp3 29 0250h 00000250h next pc interrupt inttp3cc1 tmp3 capture compare channel 1 tmp3 30 0260h 00000260h next pc interrupt inttg0ov0 tmg0 overflow interrupt 0 tmg0 31 0270h 00000270h next pc interrupt inttg0ov1 tmg0 overflow interrupt 1 tmg0 32 0280h 00000280h next pc interrupt inttg0cc0 tmg0 capture compare channel 0 tmg0 33 0290h 00000290h next pc interrupt inttg0cc1 tmg0 capture compare channel 1 tmg0 34 02a0h 000002a0h next pc interrupt inttg0cc2 tmg0 capture compare channel 2 tmg0 35 02b0h 000002b0h next pc interrupt inttg0cc3 tmg0 capture compare channel 3 tmg0 36 02c0h 000002c0h next pc interrupt inttg0cc4 tmg0 capture compare channel 4 tmg0 37 02d0h 000002d0h next pc interrupt inttg0cc5 tmg0 capture compare channel 5 tmg0 38 02e0h 000002e0h next pc interrupt inttg1ov0 tmg1 overflow interrupt 0 tmg1 39 02f0h 000002f0h next pc interrupt inttg1ov1 tmg1 overflow interrupt 1 tmg1 40 0300h 00000300h next pc interrupt inttg1cc0 tmg1 capture compare channel 0 tmg1 41 0310h 00000310h next pc interrupt inttg1cc1 tmg1 capture compare channel 1 tmg1 42 0320h 00000320h next pc interrupt inttg1cc2 tmg1 capture compare channel 2 tmg1 43 0330h 00000330h next pc interrupt inttg1cc3 tmg1 capture compare channel 3 tmg1 44 0340h 00000340h next pc interrupt inttg1cc4 tmg1 capture compare channel 4 tmg1 45 0350h 00000350h next pc interrupt inttg1cc5 tmg1 capture compare channel 5 tmg1 46 0360h 00000360h next pc interrupt intty0uv0 tmy0 channel 0 underflow tmy0 47 0370h 00000370h next pc interrupt intty0uv1 tmy0 channel 1underflow tmy0 48 0380h 00000380h next pc interrupt intad adc end of conversion adc 49 0390h 00000390h next pc interrupt intc0err can0 error interrupt can0 50 03a0h 000003a0h next pc interrupt intc0wup can0 wake up interrupt can0 51 03b0h 000003b0h next pc interrupt intc0rec can0 receive interrupt can0 52 03c0h 000003c0h next pc interrupt intc0trx can0 transmit interrupt can0 53 03d0h 000003d0h next pc table 5-1 interrupt/exception source list (2/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
204 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 maskable interrupt intcb0re csib0 receive error interrupt csib0 54 03e0h 000003e0h next pc interrupt intcb0r csib0 receive complete interrupt csib0 55 03f0h 000003f0h next pc interrupt intcb0t csib0 transmit interrupt csib0 56 0400h 00000400h next pc interrupt intua0re uarta0 receive error interrupt uarta0 57 0410h 00000410h next pc interrupt intua0r uarta0 receive complete interrupt uarta0 58 0420h 00000420h next pc interrupt intua0t uarta0 transmit interrupt uarta0 59 0430h 00000430h next pc interrupt intua1re uarta1 receive error interrupt uarta1 60 0440h 00000440h next pc interrupt intua1r uarta1 receive complete interrupt uarta1 61 0450h 00000450h next pc interrupt intua1t uarta1 transmit interrupt uarta1 62 0460h 00000460h next pc interrupt intiic0 iic0 interrupt iic0 63 0470h 00000470h next pc interrupt intiic1 iic1 interrupt iic1 64 0480h 00000480h next pc interrupt intsg0 sg0 interrupt sg0 65 0490h 00000490h next pc interrupt intdma0 dma0 transmission end dma0 66 04a0h 000004a0h next pc interrupt intdma1 dma1 transmission end dma1 67 04b0h 000004b0h next pc interrupt intdma2 dma2 transmission end dma2 68 04c0h 000004c0h next pc interrupt intdma3 dma3 transmission end dma3 69 04d0h 000004d0h next pc interrupt int70 not generated by hardware a ? 70 04e0h 000004e0h next pc interrupt int71 not generated by hardware a ? 71 04f0h 000004f0h next pc interrupt intp7 external interrupt 7 port 72 0500h 00000500h next pc interrupt intc1err can1 error interrupt can1 73 0510h 00000510h next pc interrupt intc1wup can1 wake up interrupt can1 74 0520h 00000520h next pc interrupt intc1rec can1 receive interrupt can1 75 0530h 00000530h next pc interrupt intc1trx can1 transmit interrupt can1 76 0540h 00000540h next pc interrupt inttz6uv tmz6 underflow tmz6 77 0550h 00000550h next pc interrupt inttz7cuv tmz7 underflow tmz7 78 0560h 00000560h next pc interrupt inttz8uv tmz8 underflow tmz8 79 0570h 00000570h next pc interrupt inttz9uv tmz9 underflow tmz9 80 0580h 00000580h next pc interrupt inttg2ov0 tmg2 overflow interrupt 0 tmg2 81 0590h 00000590h next pc interrupt inttg2ov1 tmg2 overflow interrupt 1 tmg2 82 05a0h 000005a0h next pc interrupt inttg2cc0 tmg2 capture compare channel 0 tmg2 83 05b0h 000005b0h next pc interrupt inttg2cc1 tmg2 capture compare channel 1 tmg2 84 05c0h 000005c0h next pc interrupt inttg2cc2 tmg2 capture compare channel 2 tmg2 85 05d0h 000005d0h next pc interrupt inttg2cc3 tmg2 capture compare channel 3 tmg2 86 05e0h 000005e0h next pc table 5-1 interrupt/exception source list (3/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
205 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 default priority: the priority order when two or more maskable interrupt requests are generated at the same time. the highest priority is 0. 1. restored pc: the value of the pc saved to eipc or fepc when interrupt/exception processing is started. however, the value of the pc saved when an inter- rupt is acknowledged during division (div, divh, divu, divhu) instruction execution is the value of the pc of the current instruction (div, divh, divu, divhu). 2. nextpc: the pc value that starts the processing following interrupt/exception processing. 3. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4). maskable interrupt inttg2cc4 tmg2 capture compare channel 4 tmg2 87 05f0h 000005f0h next pc interrupt inttg2cc5 tmg2 capture compare channel 5 tmg2 88 0600h 00000600h next pc interrupt intcb1re csib1 receive error interrupt csib1 89 0610h 00000610h next pc interrupt intcb1r csib1 receive complete interrupt csib1 90 0620h 00000620h next pc interrupt intcb1t csib1 transmit interrupt csib1 91 0630h 00000630h next pc interrupt intcb2re csib2 receive error interrupt csib2 92 0640h 00000640h next pc interrupt intcb2r csib2 receive complete interrupt csib2 93 0650h 00000650h next pc interrupt intcb2t csib2 transmit interrupt csib2 94 0660h 00000660h next pc interrupt intlcd lcdbusif transmit interrupt lcdbusif 95 0670h 00000670h next pc interrupt intc2err can2 error interrupt can2 96 0680h 00000680h next pc interrupt intc2wup can2 wake up interrupt can2 97 0690h 00000690h next pc interrupt intc2rec can2 receive interrupt can2 98 06a0h 000006a0h next pc interrupt intc2trx can2 transmit interrupt can2 99 06b0h 000006b0h next pc a) these interrupts can be used as software triggered interrupts. table 5-1 interrupt/exception source list (4/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
206 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 table 5-2 pd70f3420 (otf), pd70f3421, pd70f3421 (otf), pd70f3422, pd70f3422, (otf), pd70f3423 interrupt/exception source list (1/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit reset interrupt reset reset input pin ? 0000 h 00000000 h a undef. non- maskable interrupt nmi0 nmi input port ? 0010 h 00000010 h nextpc nmiwdt watchdog timer wdt ? 0020 h 00000020 h nextpc nmi2 unused ? ? 0030 h 00000030 h nextpc software exception exception trap0n (n = 0 to f h ) trap instruction ?? 004nh (n = 0 to f h ) 00000040 h nextpc exception trap1n (n = 0 to f h ) trap instruction ?? 005nh (n = 0 to f h ) 00000050 h nextpc exception trap exception ilgop/ dbtrap illegal opcode/ dbtrap instruction ? ? 0060 h 0 h 00000060 h nextpc maskable interrupt intvc0 voltage comparator 0 ac0 0 0080 h 00000080 h next pc interrupt intvc1 voltage comparator 1 ac1 1 0090 h 00000090 h next pc interrupt intwt0uv wt0 underflow wt0 2 00a0 h 000000a0 h next pc interrupt intwt1uv wt1 underflow wt1 3 00b0 h 000000b0 h next pc interrupt reserved reserved ?400c0 h 000000c0 h next pc interrupt inttm01 watch calibration timer capture compare wct 5 00d0 h 000000d0 h next pc interrupt intp0 external interrupt 0 port 6 00e0 h 000000e0 h next pc interrupt intp1 external interrupt 1 port 7 00f0 h 000000f0 h next pc interrupt intp2 external interrupt 2 port 8 0100 h 00000100 h next pc interrupt intp3 external interrupt 3 port 9 0110 h 00000110 h next pc interrupt intp4 external interrupt 4 port 10 0120 h 00000120 h next pc interrupt intp5 external interrupt 5 port 11 0130 h 00000130 h next pc interrupt intp6 external interrupt 6 port 12 0140 h 00000140 h next pc interrupt inttz0uv tmz0 underflow tmz0 13 0150 h 00000150 h next pc interrupt inttz1uv tmz1 underflow tmz1 14 0160 h 00000160 h next pc interrupt inttz2uv tmz2 underflow tmz2 15 0170 h 00000170 h next pc interrupt inttz3uv tmz3 underflow tmz3 16 0180 h 00000180 h next pc interrupt inttz4uv tmz4 underflow tmz4 17 0190 h 00000190 h next pc interrupt inttz5uv tmz5 underflow tmz5 18 01a0 h 000001a0 h next pc interrupt inttp0ov tmp0 overflow tmp0 19 01b0 h 000001b0 h next pc interrupt inttp0cc0 tmp0 capture compare channel 0 tmp0 20 01c0 h 000001c0 h next pc interrupt inttp0cc1 tmp0 capture compare channel 1 tmp0 21 01d0 h 000001d0 h next pc interrupt inttp1ov tmp1 overflow tmp1 22 01e0 h 000001e0 h next pc interrupt inttp1cc0 tmp1 capture compare channel 0 tmp1 23 01f0 h 000001f0 h next pc interrupt inttp1cc1 tmp1 capture compare channel 1 tmp1 24 0200 h 00000200 h next pc
207 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 maskable interrupt inttp2ov tmp2 overflow tmp2 25 0210 h 00000210 h next pc interrupt inttp2cc0 tmp2 capture compare channel 0 tmp2 26 0220 h 00000220 h next pc interrupt inttp2cc1 tmp2 capture compare channel 1 tmp2 27 0230 h 00000230 h next pc interrupt inttp3ov tmp3 overflow tmp3 28 0240 h 00000240 h next pc interrupt inttp3cc0 tmp3 capture compare channel 0 tmp3 29 0250 h 00000250 h next pc interrupt inttp3cc1 tmp3 capture compare channel 1 tmp3 30 0260 h 00000260 h next pc interrupt inttg0ov0 tmg0 overflow interrupt 0 tmg0 31 0270 h 00000270 h next pc interrupt inttg0ov1 tmg0 overflow interrupt 1 tmg0 32 0280 h 00000280 h next pc interrupt inttg0cc0 tmg0 capture compare channel 0 tmg0 33 0290 h 00000290 h next pc interrupt inttg0cc1 tmg0 capture compare channel 1 tmg0 34 02a0 h 000002a0 h next pc interrupt inttg0cc2 tmg0 capture compare channel 2 tmg0 35 02b0 h 000002b0 h next pc interrupt inttg0cc3 tmg0 capture compare channel 3 tmg0 36 02c0 h 000002c0 h next pc interrupt inttg0cc4 tmg0 capture compare channel 4 tmg0 37 02d0 h 000002d0 h next pc interrupt inttg0cc5 tmg0 capture compare channel 5 tmg0 38 02e0 h 000002e0 h next pc interrupt inttg1ov0 tmg1 overflow interrupt 0 tmg1 39 02f0 h 000002f0 h next pc interrupt inttg1ov1 tmg1 overflow interrupt 1 tmg1 40 0300 h 00000300 h next pc interrupt inttg1cc0 tmg1 capture compare channel 0 tmg1 41 0310 h 00000310 h next pc interrupt inttg1cc1 tmg1 capture compare channel 1 tmg1 42 0320 h 00000320 h next pc interrupt inttg1cc2 tmg1 capture compare channel 2 tmg1 43 0330 h 00000330 h next pc interrupt inttg1cc3 tmg1 capture compare channel 3 tmg1 44 0340 h 00000340 h next pc interrupt inttg1cc4 tmg1 capture compare channel 4 tmg1 45 0350 h 00000350 h next pc interrupt inttg1cc5 tmg1 capture compare channel 5 tmg1 46 0360 h 00000360 h next pc interrupt intty0uv0 tmy0 channel 0 underflow tmy0 47 0370 h 00000370 h next pc interrupt intty0uv1 tmy0 channel 1underflow tmy0 48 0380 h 00000380 h next pc table 5-2 pd70f3420 (otf), pd70f3421, pd70f3421 (otf), pd70f3422, pd70f3422, (otf), pd70f3423 interrupt/exception source list (2/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
208 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 maskable interrupt intad adc end of conversion adc 49 0390 h 00000390 h next pc interrupt intc0err can0 error interrupt can0 50 03a0 h 000003a0 h next pc interrupt intc0wup can0 wake up interrupt can0 51 03b0 h 000003b0 h next pc interrupt intc0rec can0 receive interrupt can0 52 03c0 h 000003c0 h next pc interrupt intc0trx can0 transmit interrupt can0 53 03d0 h 000003d0 h next pc interrupt intcb0re csib0 receive error interrupt csib0 54 03e0 h 000003e0 h next pc interrupt intcb0r csib0 receive complete interrupt csib0 55 03f0 h 000003f0 h next pc interrupt intcb0t csib0 transmit interrupt csib0 56 0400 h 00000400 h next pc interrupt intua0re uarta0 receive error interrupt uarta0 57 0410 h 00000410 h next pc interrupt intua0r uarta0 receive complete interrupt uarta0 58 0420 h 00000420 h next pc interrupt intua0t uarta0 transmit interrupt uarta0 59 0430 h 00000430 h next pc interrupt intua1re uarta1 receive error interrupt uarta1 60 0440 h 00000440 h next pc interrupt intua1r uarta1 receive complete interrupt uarta1 61 0450 h 00000450 h next pc interrupt intua1t uarta1 transmit interrupt uarta1 62 0460 h 00000460 h next pc interrupt intiic0 iic0 interrupt iic0 63 0470 h 00000470 h next pc interrupt intiic1 iic1 interrupt iic1 64 0480 h 00000480 h next pc interrupt intsg0 sg0 interrupt sg0 65 0490 h 00000490 h next pc interrupt intdma0 dma0 transmission end dma0 66 04a0 h 000004a0 h next pc interrupt intdma1 dma1 transmission end dma1 67 04b0 h 000004b0 h next pc interrupt intdma2 dma2 transmission end dma2 68 04c0 h 000004c0 h next pc interrupt intdma3 dma3 transmission end dma3 69 04d0 h 000004d0 h next pc interrupt int70 not generated by hardware b ?7004e0 h 000004e0 h next pc interrupt int71 not generated by hardware a ?7104f0 h 000004f0 h next pc interrupt reserved reserved ? 72 0500 h 00000500 h next pc interrupt intc1err can1 error interrupt can1 73 0510 h 00000510 h next pc interrupt intc1wup can1 wake up interrupt can1 74 0520 h 00000520 h next pc interrupt intc1rec can1 receive interrupt can1 75 0530 h 00000530 h next pc interrupt intc1trx can1 transmit interrupt can1 76 0540 h 00000540 h next pc table 5-2 pd70f3420 (otf), pd70f3421, pd70f3421 (otf), pd70f3422, pd70f3422, (otf), pd70f3423 interrupt/exception source list (3/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
209 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 maskable interrupt reserved reserved ? 77 ... 88 0xx0 h 00000xx0 h next pc interrupt intcb1re csib1 receive error interrupt csib1 89 0610 h 00000610 h next pc interrupt intcb1r csib1 receive complete interrupt csib1 90 0620 h 00000620 h next pc interrupt intcb1t csib1 transmit interrupt csib1 91 0630 h 00000630 h next pc interrupt reserved reserved ? 92 ... 95 0xx0 h 00000xx0 h next pc interrupt intc2err can2 error interrupt c can2 96 0680 h 00000680 h next pc interrupt intc2wup can2 wake up interrupt c can2 97 0690 h 00000690 h next pc interrupt intc2rec can2 receive interrupt c can2 98 06a0 h 000006a0 h next pc interrupt intc2trx can2 transmit interrupt c can2 99 06b0 h 000006b0 h next pc a) the internal firmware starts after reset at 0000 0000 h . the firmware starts the user?s program - for otf devices at address 0000 0000 h - for flash memory devices at the address obtained from the variable reset vector b) these interrupts can be used as software triggered interrupts. c) pd70f3423 only table 5-2 pd70f3420 (otf), pd70f3421, pd70f3421 (otf), pd70f3422, pd70f3422, (otf), pd70f3423 interrupt/exception source list (4/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
210 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 table 5-3 pd70f3424, pd70f3425, pd70f3426, pd70f3427 interrupt/ exception source list (1/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit reset interrupt reset reset input pin ? 000 0 h 0000000 0 h a undef. non- maskable interrupt nmi0 nmi input port ? 001 0 h 0000001 0 h nextpc nmiwdt watchdog timer wdt ? 002 0 h 0000002 0 h nextpc nmi2 unused ? ? 003 0 h 0000003 0 h nextpc software exception exception trap0n (n = 0 to f h ) trap instruction ?? 004nh (n = 0 to f h ) 0000004 0 h nextpc exception trap1n (n = 0 to f h ) trap instruction ?? 005nh (n = 0 to f h ) 0000005 0 h nextpc exception trap exception ilgop/ dbtrap illegal opcode/ dbtrap instruction ? ? 006 0 h 0000006 0 h nextpc maskable interrupt intvc0 voltage comparator 0 ac0 0 008 0 h 0000008 0 h next pc interrupt intvc1 voltage comparator 1 ac1 1 009 0 h 0000009 0 h next pc interrupt intwt0uv wt0 underflow wt0 2 00a 0 h 000000a 0 h next pc interrupt intwt1uv wt1 underflow wt1 3 00b 0 h 000000b 0 h next pc interrupt reserved reserved ?400c 0 h 000000c 0 h next pc interrupt inttm01 watch calibration timer capture compare wct 5 00d 0 h 000000d 0 h next pc interrupt intp0 external interrupt 0 port 6 00e 0 h 000000e 0 h next pc interrupt intp1 external interrupt 1 port 7 00f 0 h 000000f 0 h next pc interrupt intp2 external interrupt 2 port 8 010 0 h 0000010 0 h next pc interrupt intp3 external interrupt 3 port 9 011 0 h 0000011 0 h next pc interrupt intp4 external interrupt 4 port 10 012 0 h 0000012 0 h next pc interrupt intp5 external interrupt 5 port 11 013 0 h 0000013 0 h next pc interrupt intp6 external interrupt 6 port 12 014 0 h 0000014 0 h next pc interrupt inttz0uv tmz0 underflow tmz0 13 015 0 h 0000015 0 h next pc interrupt inttz1uv tmz1 underflow tmz1 14 016 0 h 0000016 0 h next pc interrupt inttz2uv tmz2 underflow tmz2 15 017 0 h 0000017 0 h next pc interrupt inttz3uv tmz3 underflow tmz3 16 018 0 h 0000018 0 h next pc interrupt inttz4uv tmz4 underflow tmz4 17 019 0 h 0000019 0 h next pc interrupt inttz5uv tmz5 underflow tmz5 18 01a 0 h 000001a 0 h next pc interrupt inttp0ov tmp0 overflow tmp0 19 01b 0 h 000001b 0 h next pc interrupt inttp0cc0 tmp0 capture compare channel 0 tmp0 20 01c 0 h 000001c 0 h next pc interrupt inttp0cc1 tmp0 capture compare channel 1 tmp0 21 01d 0 h 000001d 0 h next pc interrupt inttp1ov tmp1 overflow tmp1 22 01e 0 h 000001e 0 h next pc interrupt inttp1cc0 tmp1 capture compare channel 0 tmp1 23 01f 0 h 000001f 0 h next pc interrupt inttp1cc1 tmp1 capture compare channel 1 tmp1 24 020 0 h 0000020 0 h next pc interrupt inttp2ov tmp2 overflow tmp2 25 021 0 h 0000021 0 h next pc
211 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 maskable interrupt inttp2cc0 tmp2 capture compare channel 0 tmp2 26 022 0 h 0000022 0 h next pc interrupt inttp2cc1 tmp2 capture compare channel 1 tmp2 27 023 0 h 0000023 0 h next pc interrupt inttp3ov tmp3 overflow tmp3 28 024 0 h 0000024 0 h next pc interrupt inttp3cc0 tmp3 capture compare channel 0 tmp3 29 025 0 h 0000025 0 h next pc interrupt inttp3cc1 tmp3 capture compare channel 1 tmp3 30 026 0 h 0000026 0 h next pc interrupt inttg0ov0 tmg0 overflow interrupt 0 tmg0 31 027 0 h 0000027 0 h next pc interrupt inttg0ov1 tmg0 overflow interrupt 1 tmg0 32 028 0 h 0000028 0 h next pc interrupt inttg0cc0 tmg0 capture compare channel 0 tmg0 33 029 0 h 0000029 0 h next pc interrupt inttg0cc1 tmg0 capture compare channel 1 tmg0 34 02a 0 h 000002a 0 h next pc interrupt inttg0cc2 tmg0 capture compare channel 2 tmg0 35 02b 0 h 000002b 0 h next pc interrupt inttg0cc3 tmg0 capture compare channel 3 tmg0 36 02c 0 h 000002c 0 h next pc interrupt inttg0cc4 tmg0 capture compare channel 4 tmg0 37 02d 0 h 000002d 0 h next pc interrupt inttg0cc5 tmg0 capture compare channel 5 tmg0 38 02e 0 h 000002e 0 h next pc interrupt inttg1ov0 tmg1 overflow interrupt 0 tmg1 39 02f 0 h 000002f 0 h next pc interrupt inttg1ov1 tmg1 overflow interrupt 1 tmg1 40 030 0 h 0000030 0 h next pc interrupt inttg1cc0 tmg1 capture compare channel 0 tmg1 41 031 0 h 0000031 0 h next pc interrupt inttg1cc1 tmg1 capture compare channel 1 tmg1 42 032 0 h 0000032 0 h next pc interrupt inttg1cc2 tmg1 capture compare channel 2 tmg1 43 033 0 h 0000033 0 h next pc interrupt inttg1cc3 tmg1 capture compare channel 3 tmg1 44 034 0 h 0000034 0 h next pc interrupt inttg1cc4 tmg1 capture compare channel 4 tmg1 45 035 0 h 0000035 0 h next pc interrupt inttg1cc5 tmg1 capture compare channel 5 tmg1 46 036 0 h 0000036 0 h next pc interrupt intty0uv0 tmy0 channel 0 underflow tmy0 47 037 0 h 0000037 0 h next pc interrupt intty0uv1 tmy0 channel 1underflow tmy0 48 038 0 h 0000038 0 h next pc interrupt intad adc end of conversion adc 49 039 0 h 0000039 0 h next pc interrupt intc0err can0 error interrupt can0 50 03a 0 h 000003a 0 h next pc interrupt intc0wup can0 wake up interrupt can0 51 03b 0 h 000003b 0 h next pc interrupt intc0rec can0 receive interrupt can0 52 03c 0 h 000003c 0 h next pc interrupt intc0trx can0 transmit interrupt can0 53 03d 0 h 000003d 0 h next pc table 5-3 pd70f3424, pd70f3425, pd70f3426, pd70f3427 interrupt/ exception source list (2/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
212 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 maskable interrupt intcb0re csib0 receive error interrupt csib0 54 03e 0 h 000003e 0 h next pc interrupt intcb0r csib0 receive complete interrupt csib0 55 03f 0 h 000003f 0 h next pc interrupt intcb0t csib0 transmit interrupt csib0 56 040 0 h 0000040 0 h next pc interrupt intua0re uarta0 receive error interrupt uarta0 57 041 0 h 0000041 0 h next pc interrupt intua0r uarta0 receive complete interrupt uarta0 58 042 0 h 0000042 0 h next pc interrupt intua0t uarta0 transmit interrupt uarta0 59 043 0 h 0000043 0 h next pc interrupt intua1re uarta1 receive error interrupt uarta1 60 044 0 h 0000044 0 h next pc interrupt intua1r uarta1 receive complete interrupt uarta1 61 045 0 h 0000045 0 h next pc interrupt intua1t uarta1 transmit interrupt uarta1 62 046 0 h 0000046 0 h next pc interrupt intiic0 iic0 interrupt iic0 63 047 0 h 0000047 0 h next pc interrupt intiic1 iic1 interrupt iic1 64 048 0 h 0000048 0 h next pc interrupt intsg0 sg0 interrupt sg0 65 049 0 h 0000049 0 h next pc interrupt intdma0 dma0 transmission end dma0 66 04a 0 h 000004a 0 h next pc interrupt intdma1 dma1 transmission end dma1 67 04b 0 h 000004b 0 h next pc interrupt intdma2 dma2 transmission end dma2 68 04c 0 h 000004c 0 h next pc interrupt intdma3 dma3 transmission end dma3 69 04d 0 h 000004d 0 h next pc interrupt int70 not generated by hardware b ?7004e 0 h 000004e 0 h next pc interrupt int71 not generated by hardware a ?7104f 0 h 000004f 0 h next pc interrupt intp7 external interrupt 7 port 72 050 0 h 0000050 0 h next pc interrupt intc1err can1 error interrupt can1 73 051 0 h 0000051 0 h next pc interrupt intc1wup can1 wake up interrupt can1 74 052 0 h 0000052 0 h next pc interrupt intc1rec can1 receive interrupt can1 75 053 0 h 0000053 0 h next pc interrupt intc1trx can1 transmit interrupt can1 76 054 0 h 0000054 0 h next pc interrupt inttz6uv tmz6 underflow tmz6 77 055 0 h 0000055 0 h next pc interrupt inttz7cuv tmz7 underflow tmz7 78 056 0 h 0000056 0 h next pc interrupt inttz8uv tmz8 underflow tmz8 79 057 0 h 0000057 0 h next pc interrupt inttz9uv tmz9 underflow tmz9 80 058 0 h 0000058 0 h next pc interrupt inttg2ov0 tmg2 overflow interrupt 0 tmg2 81 059 0 h 0000059 0 h next pc interrupt inttg2ov1 tmg2 overflow interrupt 1 tmg2 82 05a 0 h 000005a 0 h next pc interrupt inttg2cc0 tmg2 capture compare channel 0 tmg2 83 05b 0 h 000005b 0 h next pc interrupt inttg2cc1 tmg2 capture compare channel 1 tmg2 84 05c 0 h 000005c 0 h next pc interrupt inttg2cc2 tmg2 capture compare channel 2 tmg2 85 05d 0 h 000005d 0 h next pc table 5-3 pd70f3424, pd70f3425, pd70f3426, pd70f3427 interrupt/ exception source list (3/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
213 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 default priority: the priority order when two or more maskable interrupt requests are generated at the same time. the highest priority is 0. 1. restored pc: the value of the pc saved to eipc or fepc when interrupt/exception processing is started. however, the value of the pc saved when an inter- rupt is acknowledged during division (div, divh, divu, divhu) instruction execution is the value of the pc of the current instruction (div, divh, divu, divhu). 2. nextpc: the pc value that starts the processing following interrupt/exception processing. 3. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4). maskable interrupt inttg2cc3 tmg2 capture compare channel 3 tmg2 86 05e 0 h 000005e 0 h next pc interrupt inttg2cc4 tmg2 capture compare channel 4 tmg2 87 05f 0 h 000005f 0 h next pc interrupt inttg2cc5 tmg2 capture compare channel 5 tmg2 88 060 0 h 0000060 0 h next pc interrupt intcb1re csib1 receive error interrupt csib1 89 061 0 h 0000061 0 h next pc interrupt intcb1r csib1 receive complete interrupt csib1 90 062 0 h 0000062 0 h next pc interrupt intcb1t csib1 transmit interrupt csib1 91 063 0 h 0000063 0 h next pc interrupt intcb2re csib2 receive error interrupt csib2 92 064 0 h 0000064 0 h next pc interrupt intcb2r csib2 receive complete interrupt csib2 93 065 0 h 0000065 0 h next pc interrupt intcb2t csib2 transmit interrupt csib2 94 066 0 h 0000066 0 h next pc interrupt intlcd lcdbusif transmit interrupt lcdbusif 95 067 0 h 0000067 0 h next pc interrupt intc2err c can2 error interrupt can2 96 068 0 h 0000068 0 h next pc interrupt intc2wup c can2 wake up interrupt can2 97 069 0 h 0000069 0 h next pc interrupt intc2rec c can2 receive interrupt can2 98 06a 0 h 000006a 0 h next pc interrupt intc2trx c can2 transmit interrupt can2 99 06b 0 h 000006b 0 h next pc a) the internal firmware starts after reset at 0000 0000 h . the firmware starts the user?s program - for otf devices at address 0000 0000 h - for flash memory devices at the address obtained from the variable reset vector b) these interrupts can be used as software triggered interrupts. c) pd70f3424, pdf3427 only table 5-3 pd70f3424, pd70f3425, pd70f3426, pd70f3427 interrupt/ exception source list (4/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
214 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 table 5-4 pd70f3421, pd70f3422, pd70f3423 interrupt/exception source list (1/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit reset interrupt reset reset input pin ? 000 0 h 0000000 0 h undef. non- maskable interrupt nmi0 nmi input port ? 001 0 h 0000001 0 h nextpc nmiwdt watchdog timer wdt ? 002 0 h 0000002 0 h nextpc nmi2 unused ? ? 003 0 h 0000003 0 h nextpc software exception exception trap0n (n = 0 to f h ) trap instruction ?? 004nh (n = 0 to f h ) 0000004 0 h nextpc exception trap1n (n = 0 to f h ) trap instruction ?? 005nh (n = 0 to f h ) 0000005 0 h nextpc exception trap exception ilgop/ dbtrap illegal opcode/ dbtrap instruction ? ? 006 0 h 0000006 0 h nextpc maskable interrupt intvc0 voltage comparator 0 ac0 0 008 0 h 0000008 0 h next pc interrupt intvc1 voltage comparator 1 ac1 1 009 0 h 0000009 0 h next pc interrupt intwt0uv wt0 underflow wt0 2 00a 0 h 000000a 0 h next pc interrupt intwt1uv wt1 underflow wt1 3 00b 0 h 000000b 0 h next pc interrupt reserved reserved ?400c 0 h 000000c 0 h next pc interrupt inttm01 watch calibration timer capture compare wct 5 00d 0 h 000000d 0 h next pc interrupt intp0 external interrupt 0 port 600e 0 h 000000e 0 h next pc interrupt intp1 external interrupt 1 7 00f 0 h 000000f 0 h next pc interrupt intp2 external interrupt 2 8 010 0 h 0000010 0 h next pc interrupt intp3 external interrupt 3 9 011 0 h 0000011 0 h next pc interrupt intp4 external interrupt 4 10 012 0 h 0000012 0 h next pc interrupt intp5 external interrupt 5 11 013 0 h 0000013 0 h next pc interrupt intp6 external interrupt 6 12 014 0 h 0000014 0 h next pc interrupt inttz0uv tmz0 underflow tmz0 13 015 0 h 0000015 0 h next pc interrupt inttz1uv tmz1 underflow tmz1 14 016 0 h 0000016 0 h next pc interrupt inttz2uv tmz2 underflow tmz2 15 017 0 h 0000017 0 h next pc interrupt inttz3uv tmz3 underflow tmz3 16 018 0 h 0000018 0 h next pc interrupt inttz4uv tmz4 underflow tmz4 17 019 0 h 0000019 0 h next pc interrupt inttz5uv tmz5 underflow tmz5 18 01a 0 h 000001a 0 h next pc interrupt inttp0ov tmp0 overflow tmp0 19 01b 0 h 000001b 0 h next pc interrupt inttp0cc0 tmp0 capture compare channel 0 20 01c 0 h 000001c 0 h next pc interrupt inttp0cc1 tmp0 capture compare channel 1 21 01d 0 h 000001d 0 h next pc interrupt inttp1ov tmp1 overflow tmp1 22 01e 0 h 000001e 0 h next pc interrupt inttp1cc0 tmp1 capture compare channel 0 23 01f 0 h 000001f 0 h next pc interrupt inttp1cc1 tmp1 capture compare channel 1 24 020 0 h 0000020 0 h next pc
215 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 maskable interrupt inttp2ov tmp2 overflow tmp2 25 021 0 h 0000021 0 h next pc interrupt inttp2cc0 tmp2 capture compare channel 0 26 022 0 h 0000022 0 h next pc interrupt inttp2cc1 tmp2 capture compare channel 1 27 023 0 h 0000023 0 h next pc interrupt inttp3ov tmp3 overflow tmp3 28 024 0 h 0000024 0 h next pc interrupt inttp3cc0 tmp3 capture compare channel 0 29 025 0 h 0000025 0 h next pc interrupt inttp3cc1 tmp3 capture compare channel 1 30 026 0 h 0000026 0 h next pc interrupt inttg0ov0 tmg0 overflow interrupt 0 tmg0 31 027 0 h 0000027 0 h next pc interrupt inttg0ov1 tmg0 overflow interrupt 1 32 028 0 h 0000028 0 h next pc interrupt inttg0cc0 tmg0 capture compare channel 0 33 029 0 h 0000029 0 h next pc interrupt inttg0cc1 tmg0 capture compare channel 1 34 02a 0 h 000002a 0 h next pc interrupt inttg0cc2 tmg0 capture compare channel 2 35 02b 0 h 000002b 0 h next pc interrupt inttg0cc3 tmg0 capture compare channel 3 36 02c 0 h 000002c 0 h next pc interrupt inttg0cc4 tmg0 capture compare channel 4 37 02d 0 h 000002d 0 h next pc interrupt inttg0cc5 tmg0 capture compare channel 5 38 02e 0 h 000002e 0 h next pc interrupt inttg1ov0 tmg1 overflow interrupt 0 tmg1 39 02f 0 h 000002f 0 h next pc interrupt inttg1ov1 tmg1 overflow interrupt 1 40 030 0 h 0000030 0 h next pc interrupt inttg1cc0 tmg1 capture compare channel 0 41 031 0 h 0000031 0 h next pc interrupt inttg1cc1 tmg1 capture compare channel 1 42 032 0 h 0000032 0 h next pc interrupt inttg1cc2 tmg1 capture compare channel 2 43 033 0 h 0000033 0 h next pc interrupt inttg1cc3 tmg1 capture compare channel 3 44 034 0 h 0000034 0 h next pc interrupt inttg1cc4 tmg1 capture compare channel 4 45 035 0 h 0000035 0 h next pc interrupt inttg1cc5 tmg1 capture compare channel 5 46 036 0 h 0000036 0 h next pc interrupt intty0uv0 tmy0 channel 0 underflow tmy0 47 037 0 h 0000037 0 h next pc interrupt intty0uv1 tmy0 channel 1 underflow 48 038 0 h 0000038 0 h next pc interrupt intad adc end of conversion adc 49 039 0 h 0000039 0 h next pc table 5-4 pd70f3421, pd70f3422, pd70f3423 interrupt/exception source list (2/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
216 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 maskable interrupt intc0err can0 error interrupt can0 50 03a 0 h 000003a 0 h next pc interrupt intc0wup can0 wake up interrupt 51 03b 0 h 000003b 0 h next pc interrupt intc0rec can0 receive interrupt 52 03c 0 h 000003c 0 h next pc interrupt intc0trx can0 transmit interrupt 53 03d 0 h 000003d 0 h next pc interrupt intcb0re csib0 receive error interrupt csib0 54 03e 0 h 000003e 0 h next pc interrupt intcb0r csib0 receive complete interrupt 55 03f 0 h 000003f 0 h next pc interrupt intcb0t csib0 transmit interrupt 56 040 0 h 0000040 0 h next pc interrupt intua0re uarta0 receive error interrupt uarta0 57 041 0 h 0000041 0 h next pc interrupt intua0r uarta0 receive complete interrupt 58 042 0 h 0000042 0 h next pc interrupt intua0t uarta0 transmit interrupt 59 043 0 h 0000043 0 h next pc interrupt intua1re uarta1 receive error interrupt uarta1 60 044 0 h 0000044 0 h next pc interrupt intua1r uarta1 receive complete interrupt 61 045 0 h 0000045 0 h next pc interrupt intua1t uarta1 transmit interrupt 62 046 0 h 0000046 0 h next pc interrupt intiic0 iic0 interrupt iic0 63 047 0 h 0000047 0 h next pc interrupt intiic1 iic1 interrupt iic1 64 048 0 h 0000048 0 h next pc interrupt intsg0 sg0 interrupt sg0 65 049 0 h 0000049 0 h next pc interrupt intdma0 dma0 transmission end dma0 66 04a 0 h 000004a 0 h next pc interrupt intdma1 dma1 transmission end dma1 67 04b 0 h 000004b 0 h next pc interrupt intdma2 dma2 transmission end dma2 68 04c 0 h 000004c 0 h next pc interrupt intdma3 dma3 transmission end dma3 69 04d 0 h 000004d 0 h next pc interrupt int70 not generated by hardware a ?7004e 0 h 000004e 0 h next pc interrupt int71 not generated by hardware a ?7104f 0 h 000004f 0 h next pc interrupt reserved reserved ? 72 050 0 h 0000050 0 h next pc interrupt intc1err can1 error interrupt can1 73 051 0 h 0000051 0 h next pc interrupt intc1wup can1 wake up interrupt 74 052 0 h 0000052 0 h next pc interrupt intc1rec can1 receive interrupt 75 053 0 h 0000053 0 h next pc interrupt intc1trx can1 transmit interrupt 76 054 0 h 0000054 0 h next pc interrupt reserved reserved ? 77 055 0 h 0000055 0 h next pc ? 78 056 0 h 0000056 0 h next pc ? 79 057 0 h 0000057 0 h next pc ? 80 058 0 h 0000058 0 h next pc table 5-4 pd70f3421, pd70f3422, pd70f3423 interrupt/exception source list (3/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
217 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 maskable interrupt inttg2ov0 tmg2 overflow interrupt 0 tmg2 81 059 0 h 0000059 0 h next pc interrupt inttg2ov1 tmg2 overflow interrupt 1 82 05a 0 h 000005a 0 h next pc interrupt inttg2cc0 tmg2 capture compare channel 0 83 05b 0 h 000005b 0 h next pc interrupt inttg2cc1 tmg2 capture compare channel 1 84 05c 0 h 000005c 0 h next pc interrupt inttg2cc2 tmg2 capture compare channel 2 85 05d 0 h 000005d 0 h next pc interrupt inttg2cc3 tmg2 capture compare channel 3 86 05e 0 h 000005e 0 h next pc interrupt inttg2cc4 tmg2 capture compare channel 4 87 05f 0 h 000005f 0 h next pc interrupt inttg2cc5 tmg2 capture compare channel 5 88 060 0 h 0000060 0 h next pc interrupt intcb1re csib1 receive error interrupt csib1 89 061 0 h 0000061 0 h next pc interrupt intcb1r csib1 receive complete interrupt 90 062 0 h 0000062 0 h next pc interrupt intcb1t csib1 transmit interrupt 91 063 0 h 0000063 0 h next pc interrupt reserved reserved ? 92 064 0 h 0000064 0 h next pc ? 93 065 0 h 0000065 0 h next pc ? 94 066 0 h 0000066 0 h next pc interrupt intlcd lcdbusif transmit interrupt lcdbusif 95 067 0 h 0000067 0 h next pc interrupt intc2err can2 error interrupt can2 96 068 0 h 0000068 0 h next pc interrupt intc2wup can2 wake up interrupt 97 069 0 h 0000069 0 h next pc interrupt intc2rec can2 receive interrupt 98 06a 0 h 000006a 0 h next pc interrupt intc2trx can2 transmit interrupt 99 06b 0 h 000006b 0 h next pc a) these interrupts can be used as software triggered interrupts. table 5-4 pd70f3421, pd70f3422, pd70f3423 interrupt/exception source list (4/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
218 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 table 5-5 pd70f3424, pd70f3425, pd70f3426a, pd70f3427 interrupt/ exception source list (1/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit reset interrupt reset reset input pin ? 000 0 h 0000000 0 h undef. non- maskable interrupt nmi0 nmi input port ? 001 0 h 0000001 0 h nextpc nmiwdt watchdog timer wdt ? 002 0 h 0000002 0 h nextpc nmi2 unused ? ? 003 0 h 0000003 0 h nextpc software exception exception trap0n (n = 0 to f h ) trap instruction ?? 004nh (n = 0 to f h ) 0000004 0 h nextpc exception trap1n (n = 0 to f h ) trap instruction ?? 005nh (n = 0 to f h ) 0000005 0 h nextpc exception trap exception ilgop/ dbtrap illegal opcode/ dbtrap instruction ? ? 006 0 h 0000006 0 h nextpc maskable interrupt intvc0 voltage comparator 0 ac0 0 008 0 h 0000008 0 h next pc interrupt intvc1 voltage comparator 1 ac1 1 009 0 h 0000009 0 h next pc interrupt intwt0uv wt0 underflow wt0 2 00a 0 h 000000a 0 h next pc interrupt intwt1uv wt1 underflow wt1 3 00b 0 h 000000b 0 h next pc interrupt reserved reserved ?400c 0 h 000000c 0 h next pc interrupt inttm01 watch calibration timer capture compare wct 5 00d 0 h 000000d 0 h next pc interrupt intp0 external interrupt 0 port 600e 0 h 000000e 0 h next pc interrupt intp1 external interrupt 1 7 00f 0 h 000000f 0 h next pc interrupt intp2 external interrupt 2 8 010 0 h 0000010 0 h next pc interrupt intp3 external interrupt 3 9 011 0 h 0000011 0 h next pc interrupt intp4 external interrupt 4 10 012 0 h 0000012 0 h next pc interrupt intp5 external interrupt 5 11 013 0 h 0000013 0 h next pc interrupt intp6 external interrupt 6 12 014 0 h 0000014 0 h next pc interrupt inttz0uv tmz0 underflow tmz0 13 015 0 h 0000015 0 h next pc interrupt inttz1uv tmz1 underflow tmz1 14 016 0 h 0000016 0 h next pc interrupt inttz2uv tmz2 underflow tmz2 15 017 0 h 0000017 0 h next pc interrupt inttz3uv tmz3 underflow tmz3 16 018 0 h 0000018 0 h next pc interrupt inttz4uv tmz4 underflow tmz4 17 019 0 h 0000019 0 h next pc interrupt inttz5uv tmz5 underflow tmz5 18 01a 0 h 000001a 0 h next pc interrupt inttp0ov tmp0 overflow tmp0 19 01b 0 h 000001b 0 h next pc interrupt inttp0cc0 tmp0 capture compare channel 0 20 01c 0 h 000001c 0 h next pc interrupt inttp0cc1 tmp0 capture compare channel 1 21 01d 0 h 000001d 0 h next pc interrupt inttp1ov tmp1 overflow tmp1 22 01e 0 h 000001e 0 h next pc interrupt inttp1cc0 tmp1 capture compare channel 0 23 01f 0 h 000001f 0 h next pc interrupt inttp1cc1 tmp1 capture compare channel 1 24 020 0 h 0000020 0 h next pc
219 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 maskable interrupt inttp2ov tmp2 overflow tmp2 25 021 0 h 0000021 0 h next pc interrupt inttp2cc0 tmp2 capture compare channel 0 26 022 0 h 0000022 0 h next pc interrupt inttp2cc1 tmp2 capture compare channel 1 27 023 0 h 0000023 0 h next pc interrupt inttp3ov tmp3 overflow tmp3 28 024 0 h 0000024 0 h next pc interrupt inttp3cc0 tmp3 capture compare channel 0 29 025 0 h 0000025 0 h next pc interrupt inttp3cc1 tmp3 capture compare channel 1 30 026 0 h 0000026 0 h next pc interrupt inttg0ov0 tmg0 overflow interrupt 0 tmg0 31 027 0 h 0000027 0 h next pc interrupt inttg0ov1 tmg0 overflow interrupt 1 32 028 0 h 0000028 0 h next pc interrupt inttg0cc0 tmg0 capture compare channel 0 33 029 0 h 0000029 0 h next pc interrupt inttg0cc1 tmg0 capture compare channel 1 34 02a 0 h 000002a 0 h next pc interrupt inttg0cc2 tmg0 capture compare channel 2 35 02b 0 h 000002b 0 h next pc interrupt inttg0cc3 tmg0 capture compare channel 3 36 02c 0 h 000002c 0 h next pc interrupt inttg0cc4 tmg0 capture compare channel 4 37 02d 0 h 000002d 0 h next pc interrupt inttg0cc5 tmg0 capture compare channel 5 38 02e 0 h 000002e 0 h next pc interrupt inttg1ov0 tmg1 overflow interrupt 0 tmg1 39 02f 0 h 000002f 0 h next pc interrupt inttg1ov1 tmg1 overflow interrupt 1 40 030 0 h 0000030 0 h next pc interrupt inttg1cc0 tmg1 capture compare channel 0 41 031 0 h 0000031 0 h next pc interrupt inttg1cc1 tmg1 capture compare channel 1 42 032 0 h 0000032 0 h next pc interrupt inttg1cc2 tmg1 capture compare channel 2 43 033 0 h 0000033 0 h next pc interrupt inttg1cc3 tmg1 capture compare channel 3 44 034 0 h 0000034 0 h next pc interrupt inttg1cc4 tmg1 capture compare channel 4 45 035 0 h 0000035 0 h next pc interrupt inttg1cc5 tmg1 capture compare channel 5 46 036 0 h 0000036 0 h next pc interrupt intty0uv0 tmy0 channel 0 underflow tmy0 47 037 0 h 0000037 0 h next pc interrupt intty0uv1 tmy0 channel 1 underflow 48 038 0 h 0000038 0 h next pc interrupt intad adc end of conversion adc 49 039 0 h 0000039 0 h next pc table 5-5 pd70f3424, pd70f3425, pd70f3426a, pd70f3427 interrupt/ exception source list (2/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
220 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 maskable interrupt intc0err can0 error interrupt can0 50 03a 0 h 000003a 0 h next pc interrupt intc0wup can0 wake up interrupt 51 03b 0 h 000003b 0 h next pc interrupt intc0rec can0 receive interrupt 52 03c 0 h 000003c 0 h next pc interrupt intc0trx can0 transmit interrupt 53 03d 0 h 000003d 0 h next pc interrupt intcb0re csib0 receive error interrupt csib0 54 03e 0 h 000003e 0 h next pc interrupt intcb0r csib0 receive complete interrupt 55 03f 0 h 000003f 0 h next pc interrupt intcb0t csib0 transmit interrupt 56 040 0 h 0000040 0 h next pc interrupt intua0re uarta0 receive error interrupt uarta0 57 041 0 h 0000041 0 h next pc interrupt intua0r uarta0 receive complete interrupt 58 042 0 h 0000042 0 h next pc interrupt intua0t uarta0 transmit interrupt 59 043 0 h 0000043 0 h next pc interrupt intua1re uarta1 receive error interrupt uarta1 60 044 0 h 0000044 0 h next pc interrupt intua1r uarta1 receive complete interrupt 61 045 0 h 0000045 0 h next pc interrupt intua1t uarta1 transmit interrupt 62 046 0 h 0000046 0 h next pc interrupt intiic0 iic0 interrupt iic0 63 047 0 h 0000047 0 h next pc interrupt intiic1 iic1 interrupt iic1 64 048 0 h 0000048 0 h next pc interrupt intsg0 sg0 interrupt sg0 65 049 0 h 0000049 0 h next pc interrupt intdma0 dma0 transmission end dma0 66 04a 0 h 000004a 0 h next pc interrupt intdma1 dma1 transmission end dma1 67 04b 0 h 000004b 0 h next pc interrupt intdma2 dma2 transmission end dma2 68 04c 0 h 000004c 0 h next pc interrupt intdma3 dma3 transmission end dma3 69 04d 0 h 000004d 0 h next pc interrupt int70 not generated by hardware a ?7004e 0 h 000004e 0 h next pc interrupt int71 not generated by hardware a ?7104f 0 h 000004f 0 h next pc interrupt intp7 external interrupt 7 port 72 050 0 h 0000050 0 h next pc interrupt intc1err can1 error interrupt can1 73 051 0 h 0000051 0 h next pc interrupt intc1wup can1 wake up interrupt 74 052 0 h 0000052 0 h next pc interrupt intc1rec can1 receive interrupt 75 053 0 h 0000053 0 h next pc interrupt intc1trx can1 transmit interrupt 76 054 0 h 0000054 0 h next pc interrupt inttz6uv tmz6 underflow tmz6 77 055 0 h 0000055 0 h next pc interrupt inttz7cuv tmz7 underflow tmz7 78 056 0 h 0000056 0 h next pc interrupt inttz8uv tmz8 underflow tmz8 79 057 0 h 0000057 0 h next pc interrupt inttz9uv tmz9 underflow tmz9 80 058 0 h 0000058 0 h next pc table 5-5 pd70f3424, pd70f3425, pd70f3426a, pd70f3427 interrupt/ exception source list (3/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
221 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 default priority: the priority order when two or more maskable interrupt requests are generated at the same time. the highest priority is 0. 1. restored pc: the value of the pc saved to eipc or fepc when interrupt/exception processing is started. however, the value of the pc saved when an inter- rupt is acknowledged during division (div, divh, divu, divhu) instruction execution is the value of the pc of the current instruction (div, divh, divu, divhu). 2. nextpc: the pc value that starts the processing following interrupt/exception processing. maskable interrupt inttg2ov0 tmg2 overflow interrupt 0 tmg2 81 059 0 h 0000059 0 h next pc interrupt inttg2ov1 tmg2 overflow interrupt 1 82 05a 0 h 000005a 0 h next pc interrupt inttg2cc0 tmg2 capture compare channel 0 83 05b 0 h 000005b 0 h next pc interrupt inttg2cc1 tmg2 capture compare channel 1 84 05c 0 h 000005c 0 h next pc interrupt inttg2cc2 tmg2 capture compare channel 2 85 05d 0 h 000005d 0 h next pc interrupt inttg2cc3 tmg2 capture compare channel 3 86 05e 0 h 000005e 0 h next pc interrupt inttg2cc4 tmg2 capture compare channel 4 87 05f 0 h 000005f 0 h next pc interrupt inttg2cc5 tmg2 capture compare channel 5 88 060 0 h 0000060 0 h next pc interrupt intcb1re csib1 receive error interrupt csib1 89 061 0 h 0000061 0 h next pc interrupt intcb1r csib1 receive complete interrupt 90 062 0 h 0000062 0 h next pc interrupt intcb1t csib1 transmit interrupt 91 063 0 h 0000063 0 h next pc interrupt intcb2re csib2 receive error interrupt csib2 92 064 0 h 0000064 0 h next pc interrupt intcb2r csib2 receive complete interrupt 93 065 0 h 0000065 0 h next pc interrupt intcb2t csib2 transmit interrupt 94 066 0 h 0000066 0 h next pc interrupt intlcd lcdbusif transmit interrupt lcdbusif 95 067 0 h 0000067 0 h next pc interrupt intc2err b can2 error interrupt can2 96 068 0 h 0000068 0 h next pc interrupt intc2wup b can2 wake up interrupt 97 069 0 h 0000069 0 h next pc interrupt intc2rec b can2 receive interrupt 98 06a 0 h 000006a 0 h next pc interrupt intc2trx b can2 transmit interrupt 99 06b 0 h 000006b 0 h next pc a) these interrupts can be used as software triggered interrupts. b) not available on pd70f3426a table 5-5 pd70f3424, pd70f3425, pd70f3426a, pd70f3427 interrupt/ exception source list (4/4) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
222 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 3. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4).
223 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 table 5-6 interrupt/exception source list (1/3) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit reset interrupt reset reset input pin ? 000 0 h 0000000 0 h undef. non- maskable interrupt nmi0 nmi input port ? 001 0 h 0000001 0 h nextpc nmiwdt watchdog timer wdt ? 002 0 h 0000002 0 h nextpc nmi2 unused ? ? 003 0 h 0000003 0 h nextpc software exception exception trap0n (n = 0 to f h ) trap instruction ?? 004nh (n = 0 to f h ) 0000004 0 h nextpc exception trap1n (n = 0 to f h ) trap instruction ?? 005nh (n = 0 to f h ) 0000005 0 h nextpc exception trap exception ilgop/ dbtrap illegal opcode/ dbtrap instruction ? ? 006 0 h 0000006 0 h nextpc maskable interrupt reserved reserved ? 0...1 0xx 0 h 00000xx 0 h nextpc interrupt intwt0uv wt0 underflow wt0 2 00a 0 h 000000a 0 h next pc interrupt intwt1uv wt1 underflow wt1 3 00b 0 h 000000b 0 h next pc interrupt reserved reserved ?400c 0 h 000000c 0 h next pc interrupt inttm01 watch calibration timer capture compare wct 5 00d 0 h 000000d 0 h next pc interrupt intp0 external interrupt 0 port 6 00e 0 h 000000e 0 h next pc interrupt intp1 external interrupt 1 port 7 00f 0 h 000000f 0 h next pc interrupt intp2 external interrupt 2 port 8 010 0 h 0000010 0 h next pc interrupt intp3 external interrupt 3 port 9 011 0 h 0000011 0 h next pc interrupt reserved reserved ? 10...12 0xx 0 h 00000xx 0 h nextpc interrupt inttz0uv tmz0 underflow tmz0 13 015 0 h 0000015 0 h next pc interrupt inttz1uv tmz1 underflow tmz1 14 016 0 h 0000016 0 h next pc interrupt inttz2uv tmz2 underflow tmz2 15 017 0 h 0000017 0 h next pc interrupt inttz3uv tmz4 underflow tmz3 16 018 0 h 0000018 0 h next pc interrupt inttz4uv tmz4 underflow tmz4 17 019 0 h 0000019 0 h nextpc interrupt inttz5uv tmz5 underflow tmz5 18 01a 0 h 0000019 0 h nextpc interrupt inttp0ov tmp0 overflow tmp0 19 01b 0 h 000001b 0 h next pc interrupt inttp0cc0 tmp0 capture compare channel 0 tmp0 20 01c 0 h 000001c 0 h next pc interrupt inttp0cc1 tmp0 capture compare channel 1 tmp0 21 01d 0 h 000001d 0 h next pc interrupt reserved reserved ? 22...30 0xx 0 h 00000xx 0 h nextpc interrupt inttg0ov0 tmg0 overflow interrupt 0 tmg0 31 027 0 h 0000027 0 h next pc interrupt inttg0ov1 tmg0 overflow interrupt 1 tmg0 32 028 0 h 0000028 0 h next pc interrupt inttg0cc0 tmg0 capture compare channel 0 tmg0 33 029 0 h 0000029 0 h next pc interrupt inttg0cc1 tmg0 capture compare channel 1 tmg0 34 02a 0 h 000002a 0 h next pc interrupt inttg0cc2 tmg0 capture compare channel 2 tmg0 35 02b 0 h 000002b 0 h next pc
224 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 maskable interrupt inttg0cc3 tmg0 capture compare channel 3 tmg0 36 02c 0 h 000002c 0 h next pc interrupt inttg0cc4 tmg0 capture compare channel 4 tmg0 37 02d 0 h 000002d 0 h next pc interrupt inttg0cc5 tmg0 capture compare channel 5 tmg0 38 02e 0 h 000002e 0 h next pc interrupt inttg1ov0 tmg1 overflow interrupt 0 tmg1 39 02f 0 h 000002f 0 h next pc interrupt inttg1ov1 tmg1 overflow interrupt 1 tmg1 40 030 0 h 0000030 0 h next pc interrupt inttg1cc0 tmg1 capture compare channel 0 tmg1 41 031 0 h 0000031 0 h next pc interrupt inttg1cc1 tmg1 capture compare channel 1 tmg1 42 032 0 h 0000032 0 h next pc interrupt inttg1cc2 tmg1 capture compare channel 2 tmg1 43 033 0 h 0000033 0 h next pc interrupt inttg1cc3 tmg1 capture compare channel 3 tmg1 44 034 0 h 0000034 0 h next pc interrupt inttg1cc4 tmg1 capture compare channel 4 tmg1 45 035 0 h 0000035 0 h next pc interrupt inttg1cc5 tmg1 capture compare channel 5 tmg1 46 036 0 h 0000036 0 h next pc interrupt reserved reserved ? 47...48 0xx 0 h 00000xx 0 h next pc interrupt intad adc end of conversion adc 49 039 0 h 0000039 0 h next pc interrupt intc0err can0 error interrupt can0 50 03a 0 h 000003a 0 h next pc interrupt intc0wup can0 wake up interrupt can0 51 03b 0 h 000003b 0 h next pc interrupt intc0rec can0 receive interrupt can0 52 03c 0 h 000003c 0 h next pc interrupt intc0trx can0 transmit interrupt can0 53 03d 0 h 000003d 0 h next pc interrupt intcb0re csib0 receive error interrupt csib0 54 03e 0 h 000003e 0 h next pc interrupt intcb0r csib0 receive complete interrupt csib0 55 03f 0 h 000003f 0 h next pc interrupt intcb0t csib0 transmit interrupt csib0 56 040 0 h 0000040 0 h next pc interrupt intua0re uarta0 receive error interrupt uarta0 57 041 0 h 0000041 0 h next pc interrupt intua0r uarta0 receive complete interrupt uarta0 58 042 0 h 0000042 0 h next pc interrupt intua0t uarta0 transmit interrupt uarta0 59 043 0 h 0000043 0 h next pc interrupt intua1re uarta1 receive error interrupt uarta1 60 044 0 h 0000044 0 h next pc interrupt intua1r uarta1 receive complete interrupt uarta1 61 045 0 h 0000045 0 h next pc interrupt intua1t uarta1 transmit interrupt uarta1 62 046 0 h 0000046 0 h next pc interrupt intiic0 iic0 interrupt iic0 63 047 0 h 0000047 0 h next pc table 5-6 interrupt/exception source list (2/3) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
225 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 default priority: the priority order when two or more maskable interrupt requests are generated at the same time. the highest priority is 0. 1. restored pc: the value of the pc saved to eipc or fepc when interrupt/exception processing is started. however, the value of the pc saved when an inter- rupt is acknowledged during division (div, divh, divu, divhu) instruction execution is the value of the pc of the current instruction (div, divh, divu, divhu). 2. nextpc: the pc value that starts the processing following interrupt/exception processing. 3. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4). maskable interrupt reserved reserved ? 64...69 0xx 0 h 00000xx 0 h next pc interrupt int70 not generated by hardware a ?7004e 0 h 000004e 0 h next pc interrupt int71 not generated by hardware a ?7104f 0 h 000004f 0 h next pc interrupt reserved reserved ? 72...88 0xx 0 h 00000xx 0 h next pc interrupt intcb1re csib1 receive error interrupt csib1 89 061 0 h 0000061 0 h next pc interrupt intcb1r csib1 receive complete interrupt csib1 90 062 0 h 0000062 0 h next pc interrupt intcb1t csib1 transmit interrupt csib1 91 063 0 h 0000063 0 h next pc a) these interrupts can be used as software triggered interrupts. table 5-6 interrupt/exception source list (3/3) type classific ation interrupt/exception source default priority exception code handler address restored pc name generating source generating unit
226 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 5.2 non-maskable interrupts a non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (di) status. non-maskable interrupts of this microcontroller are available for the following two requests: ? nmi0: nmi pin input ? nmiwdt: non-maskable watchdog timer interrupt request when the valid edge specified by the esel0, esel00 and esel01 bits of the interrupt mode register 0(intm0) is detected on the nmi pin, the interrupt occurs. the watchdog timer interrupt request is only effective as non-maskable interrupt if the wdtmode bit of the watchdog timer mode register (wdtm) is set 0. if multiple non-maskable interrupts are generated at the same time, the highest priority servicing is executed according to the following priority order (the lower priority interrupt is ignored): nmiwdt > nmi0 note that if a nmi from port pin or nmiwdt request is generated while nmi from port pin is being serviced, the service is executed as follows. (1) if a nmi0 is generated while nmi0 is being serviced the new nmi0 request is held pending regardless of the value of the psw.np bit. the pending nmivc request is acknowledged after servicing of the current nmi0 request has finished (after execution of the reti instruction). (2) if a nmiwdt request is generated while nmi0 is being serviced if the psw.np bit remains set (1) while nmi0 is being serviced, the new nmiwdt request is held pending. the pending nmiwdt request is acknowledge after servicing of the current nmi0 request has finished (after execution of the reti instruction). if the psw.np bit is cleared (0) while nmi0 is being serviced, the newly generated nmiwdt request is executed (nmi0 servicing is halted). caution 1. although the values of the pc and psw are saved to an nmi status save register (fepc, fepsw) when a non-maskable interrupt request is generated, only the nmi0 can be restored by the reti instruction at this time. because nmiwdt cannot be restored by the reti instruction, the system must be reset after servicing this interrupt. 2. if psw.np is cleared to 0 by the ldsr instruction during non-maskable interrupt servicing, a nmi0 interrupt afterwards cannot be acknowledged correctly.
227 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 figure 5-1 example of non-maskable interrupt request acknowledgement operation: multiple nmi requests generated at the same time nmi0 and nmiwdt requests generated simultaneously nmi0 and nmiwdt requests (generated simultaneously) main routine nmiwdt servicing system reset
228 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 figure 5-2 example of non-maskable interrupt request acknowledgement operation: nmi request generated during nmi servicing main routine nmi0 request nmiwdt request nmi0 servicing (held pending) system reset nmi request generated during nmi servicing nmi being serviced nmi0 nmiwdt nmi0 nmi0 request generated during nmi0 servicing nmiwdt request generated during nmi0 servicing (np = 1 retained before nmi1 request) nmiwdt request generated during nmi0 servicing (np=0 set before nmiwdt request) nmiwdt nmi0 request generated during nmiwdt servicing nmi1 request generated during nm iwdt servicing main routine nmi0 request nmi0 request nmi0 servicing (held pending) servicing of pending nmi0 main routine nmi0 request (invalid) system reset main routine (invalid) system reset main routine nmi0 request nmi0 servicing system reset np = 0 main routine nmi0 request nmi0 servicing system reset np = 0 (held pending) nmiwdt servicing nmiwdt request nmiwdt servicing nmiwdt request generated during nmi0 servicing (np=0 set after nmiwdt request) nmiwdt servicing nmiwdt request nmiwdt request nmiwdt request nmiwdt request nmiwdt servicing nmiwdt servicing
229 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 5.2.1 operation if a non-maskable interrupt is generated, the cpu performs the following processing, and transfers control to the handler routine: (1) saves the restored pc to fepc. (2) saves the current psw to fepsw. (3) writes exception code 0010 h to the higher halfword (fecc) of ecr. (4) sets the np and id bits of the psw and clears the ep bit. (5) sets the handler address corresponding to the non-maskable interrupt to the pc, and transfers control. the processing configuration of a non-maskable interrupt is shown in figure 5-3 . figure 5-3 processing configuration of non-maskable interrupt non-maskable interrupt request fepc  restored pc fepsw  psw ecr.fecc  exception code psw.np  1 psw.ep  0 psw.id  1 pc  nmi-handler address 0 psw.np intc acknowledgement cpu processing 1 nmi input interrupt service interrupt request pending
230 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 5.2.2 restore (1) nmi0 execution is restored from the non-maskable interrupt (nmi0) processing by the reti instruction. when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. <1> restores the values of the pc and the psw from fepc and fepsw, respectively, because the ep bit of the psw is 0 and the np bit of the psw is 1. <2> transfers control back to the address of the restored pc and psw. figure 5-4 illustrates how the reti instruction is processed. figure 5-4 reti instruction processing caution when the psw.ep bit and psw.np bit are changed by the ldsr instruction during non-maskable interrupt processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately before the reti instruction. note the solid line indicates the cpu processing flow. (2) nmiwdt restoring by reti instruction is not possible. perform a system reset after interrupt servicing. psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw
231 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 5.2.3 non-maskable interrupt status flag (np) the np flag is a status flag that indicates that non-maskable interrupt (nmi) processing is under execution. this flag is set when an nmi interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged. 5.2.4 nmi0 control the nmi0 can be configured to generate an nmi upon a rising, falling or both edges at the nmi pin. to enable respectively disable the nmi0 and to configure the edge refer to ?edge and level detection configuration? on page 257 . 31 8 7 6 5 4 3 2 1 0 initial value psw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 np ep id sat cy ov s z 00000020h bit position bit name function 7 np indicates whether nmi interrupt processing is in progress. 0: no nmi interrupt processing 1: nmi interrupt currently being processed
232 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 5.3 maskable interrupts maskable interrupt requests can be masked by interrupt control registers. if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). when an interrupt request has been acknowledged, the acknowledgement of other maskable interrupt requests is disabled and the interrupt disabled (di) status is set. when the ei instruction is executed in an interrupt processing routine, the interrupt enabled (ei) status is set, which enables servicing of interrupts having a higher priority than the interrupt request in progress (specified by the interrupt control register). note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. however, if multiple interrupts are executed, the following processing is necessary. (1) save eipc and eipsw in memory or a general-purpose register before executing the ei instruction. (2) execute the di instruction before executing the reti instruction, then reset eipc and eipsw with the values saved in (1). 5.3.1 operation if a maskable interrupt occurs by int input, the cpu performs the following processing, and transfers control to a handler routine: (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower halfword of ecr (eicc). (4) sets the id bit of the psw and clears the ep bit. (5) sets the handler address corresponding to each interrupt to the pc, and transfers control. the processing configuration of a maskable interrupt is shown in figure 5-5 .
233 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 figure 5-5 maskable interrupt processing note for the ispr register, see ?ispr - in-service priority register? on page 255 . an int input masked by the interrupt controllers and an int input that occurs while another interrupt is being processed (when psw.np = 1 or psw.id = 1) are held pending internally by the interrupt controller. in such case, if the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 as set by the reti and ldsr instructions, input of the pending int starts the new maskable interrupt processing. int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request pending psw.np psw.id 1 1 interrupt request pending 0 0 interrupt processing cpu processing intc accepted yes yes yes priority higher than that of interrupt currently processed? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 0 1 handler address
234 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 5.3.2 restore recovery from maskable interrupt processing is carried out by the reti instruction. when the reti instruction is executed, the cpu performs the following steps, and transfers control to the address of the restored pc. (1) restores the values of the pc and the psw from eipc and eipsw because the ep bit of the psw is 0 and the np bit of the psw is 0. (2) transfers control to the address of the restored pc and psw. figure 5-6 illustrates the processing of the reti instruction. figure 5-6 reti instruction processing note 1. for the ispr register, see ?ispr - in-service priority register? on page 255 . 2. the solid lines show the cpu processing flow. caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during maskable interrupt processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw
235 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 5.3.3 priorities of maskable interrupts this microcontroller provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxprn) of the interrupt control register (xxicn). when two or more interrupts having the same priority level specified by the xxprn bit are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. for more information, refer to the interrupt/exception source list table. the programmable priority control customizes interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is acknowledged, the id flag of psw is automatically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 beforehand (for example, by placing the ei instruction in the interrupt service program) to set the interrupt enable mode.
236 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 figure 5-7 example of processing in which another interrupt request is issued while an interrupt is being processed (1/2) caution the values of the eipc and eipsw registers must be saved before executing multiple interrupts. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. note 1. to in the figure are the temporary names of interrupt requests shown for the sake of explanation. main routine ei ei interrupt request a (level 3) processing of a processing of b processing of c interrupt request c (level 3) processing of d processing of e ei interrupt request e (level 2) processing of f ei processing of g interrupt request g (level 1) interrupt request h (level 1) processing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3)
237 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 2. the default priority in the figure indicates the relative priority between two interrupt requests. figure 5-8 example of processing in which another interrupt request is issued while an interrupt is being processed (2/2) main routine ei interrupt request i (level 2) processing of i processing of k interrupt request j (level 3) processing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) processing of l processing of n processing of m processing of s processing of u processing of t interrupt request m (level 3) interrupt request n (level 1) processing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 processing of p processing of q processing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because processing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after processing of interrupt request l. at this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after processing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated.
238 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 caution the values of the eipc and eipsw registers must be saved before executing multiple interrupts. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. note 1. lower default priority 2. higher default priority figure 5-9 example of processing interrupt requests simultaneously generated caution the values of the eipc and eipsw registers must be saved before executing multiple interrupts. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remark to in the figure are the temporary names of interrupt requests shown for the sake of explanation. default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) processing of interrupt request b . . processing of interrupt request c processing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. nmi request
239 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 5.3.4 xxic - maskable interrupts control register an interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. access this register can be read/written in 8-bit or 1-bit units. address ffff f110 h to ffff f18e h (refer to table 5-11 on page 247 ) initial value 47 h note xx: identification name of each peripheral unit (vc0-vc1, wt0uv-wt1uv, tm01, p0-p7, tz0uv-tz9uv, tp0ov-tp3ov, tp0cc0-tp3cc0, tp0cc1- tp3cc1, tg0ov0-tg2ov0, tg0ov1-tg2ov1, tg0cc0-tg2cc0, tg0cc1-tg2cc1, tg0cc2-tg2 cc2, tg0cc3-tg2cc3, tg0cc4- tg2cc4, tg0cc5-tg2cc5, ty0cc0 , ty0cc1, ad, c0err-c2err, c0wup-c2wup, c0rec-c2rec, c0trx-c2trx, cb0re-cb2re, cb0r- cb2r, cb0t-cb2t, ua0re-ua1re, ua0r-ua1r, ua0t-ua1t, iic0-iic1, sg0, dma0-dma3, int70, int71, lcd) the address and bit of each interrupt control register are shown in the following table. 76543210 xxif xxmk 0 0 0 xxpr2 xxpr1 xxpr0 r/w r/w r/w r/w r/w r/w r/w r/w table 5-7 xxic register contents bit position bit name function 7 xxif this is an interrupt request flag. 0: interrupt request not issued 1: interrupt request issued the flag xxifn is reset automatically by the hardware if an interrupt request is acknowledged. 6 xxmk this is an interrupt mask flag. 0: enables interrupt processing 1: disables interrupt processing (pending) 2 to 0 xxpr2 to xxpr0 8 levels of priority order are specified for each interrupt. xxpr2 xxpr1 xxpr0 interrupt priority specification bit 0 0 0 specifies level 0 (highest) 0 0 1 specifies level 1 0 1 0 specifies level 2 0 1 1 specifies level 3 1 0 0 specifies level 4 1 0 1 specifies level 5 1 1 0 specifies level 6 1 1 1 specifies level 7 (lowest)
240 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 table 5-8 addresses and bits of interrupt control registers (1/3) address register bit 7 6 5 4 3 2 1 0 fffff11 0 h vc0ic vc0if vc0mk 0 0 0 vc0pr2 vc0pr1 vc0pr0 fffff112 h vc1ic vc1if vc1mk 0 0 0 vc1pr2 vc1pr1 vc1pr0 fffff114 h wt0uvic wt0uvif wt0uvmk 0 0 0 wt0uvpr2 wt0uvpr1 wt0uvpr0 fffff116 h wt1uvic wt1uvif wt1uvmk 0 0 0 wt1uvpr2 wt1uvpr1 wt1uvpr0 fffff11a h tm01ic tm01if tm01mk 0 0 0 tm01pr2 tm01pr1 tm01pr0 fffff11c h p0ic p0if p0mk 0 0 0 p0pr2 p0pr1 p0pr0 fffff11e h p1ic p1if p1mk 0 0 0 p1pr2 p1pr1 p1pr0 fffff12 0 h p2ic p2if p2mk 0 0 0 p2pr2 p2pr1 p2pr0 fffff122 h p3ic p3if p3mk 0 0 0 p3pr2 p3pr1 p3pr0 fffff124 h p4ic p4if p4mk 0 0 0 p4pr2 p4pr1 p4pr0 fffff126 h p5ic p5if p5mk 0 0 0 p5pr2 p5pr1 p5pr0 fffff128 h p6ic p6if p6mk 0 0 0 p6pr2 p6pr1 p6pr0 fffff12a h tz0uvic tz0uvif tz0uvmk 0 0 0 tz0uvpr2 tz0uvpr1 tz0uvpr0 fffff12c h tz1uvic tz1uvif tz1uvmk 0 0 0 tz1uvpr2 tz1uvpr1 tz1uvpr0 fffff12e h tz2uvic tz2uvif tz2uvmk 0 0 0 tz2uvpr2 tz2uvpr1 tz2uvpr0 fffff13 0 h tz3uvic tz3uvif tz3uvmk 0 0 0 tz3uvpr2 tz3uvpr1 tz3uvpr0 fffff132 h tz4uvic tz4uvif tz4uvmk 0 0 0 tz4uvpr2 tz4uvpr1 tz4uvpr0 fffff134 h tz5uvic tz5uvif tz5uvmk 0 0 0 tz5uvpr2 tz5uvpr1 tz5uvpr0 fffff136 h tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff138 h tp0cc0ic tp0cc0if tp0cc0mk 0 0 0 tp0cc0pr2 tp0cc0pr1 tp0cc0pr0 fffff13a h tp0cc1ic tp0cc1if tp0cc1mk 0 0 0 tp0cc1pr2 tp0cc1pr1 tp0cc1pr0 fffff13c h tp1ovic tp1ovif tp1ovmk 0 0 0 tp1ovpr2 tp1ovpr1 tp1ovpr0 fffff13e h tp1cc0ic tp1cc0if tp1cc0mk 0 0 0 tp1cc0pr2 tp1cc0pr1 tp1cc0pr0 fffff14 0 h tp1cc1ic tp1cc1if tp1cc1mk 0 0 0 tp1cc1pr2 tp1cc1pr1 tp1cc1pr0 fffff142 h tp2ovic tp2ovif tp2ovmk 0 0 0 tp2ovpr2 tp2ovpr1 tp2ovpr0 fffff144 h tp2cc0ic tp2cc0if tp2cc0mk 0 0 0 tp2cc0pr2 tp2cc0pr1 tp2cc0pr0 fffff146 h tp2cc1ic tp2cc1if tp2cc1mk 0 0 0 tp2cc1pr2 tp2cc1pr1 tp2cc1pr0 fffff148 h tp3ovic tp3ovif tp3ovmk 0 0 0 tp3ovpr2 tp3ovpr1 tp3ovpr0 fffff14a h tp3cc0ic tp3cc0if tp3cc0mk 0 0 0 tp3cc0pr2 tp3cc0pr1 tp3cc0pr0 fffff14c h tp3cc1ic tp3cc1if tp3cc1mk 0 0 0 tp3cc1pr2 tp3cc1pr1 tp3cc1pr0 fffff14e h tg0ov0ic tg0ov0if tg0ov0mk 0 0 0 tg0ov0pr2 tg0ov0pr1 tg0ov0pr0 fffff15 0 h tg0ov1ic tg0ov1if tg0ov1mk 0 0 0 tg0ov1pr2 tg0ov1pr1 tg0ov1pr0 fffff152 h tg0cc0ic tg0cc0if tg0cc0mk 0 0 0 tg0cc0pr2 tg0cc0pr1 tg0cc0pr0 fffff154 h tg0cc1ic tg0cc1if tg0cc1mk 0 0 0 tg0cc1pr2 tg0cc1pr1 tg0cc1pr0 fffff156 h tg0cc2ic tg0cc2if tg0cc2mk 0 0 0 tg0cc2pr2 tg0cc2pr1 tg0cc2pr0 fffff158 h tg0cc3ic tg0cc3if tg0cc3mk 0 0 0 tg0cc3pr2 tg0cc3pr1 tg0cc3pr0 fffff15a h tg0cc4ic tg0cc4if tg0cc4mk 0 0 0 tg0cc4pr2 tg0cc4pr1 tg0cc4pr0 fffff15c h tg0cc5ic tg0cc5if tg0cc5mk 0 0 0 tg0cc5pr2 tg0cc5pr1 tg0cc5pr0 fffff15e h tg1ov0ic tg1ov0if tg1ov0mk 0 0 0 tg1ov0pr2 tg1ov0pr1 tg1ov0pr0 fffff16 0 h tg1ov1ic tg1ov1if tg1ov1mk 0 0 0 tg1ov1pr2 tg1ov1pr1 tg1ov1pr0
241 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 fffff162 h tg1cc0c tg1cc0if tg1cc0mk 0 0 0 tg1cc0pr2 tg1cc0pr1 tg1cc0pr0 fffff164 h tg1cc1ic tg1cc1if tg1cc1mk 0 0 0 tg1cc1pr2 tg1cc1pr1 tg1cc1pr0 fffff166 h tg1cc2ic tg1cc2if tg1cc2mk 0 0 0 tg1cc2pr2 tg1cc2pr1 tg1cc2pr0 fffff168 h tg1cc3ic tg1cc3if tg1cc3mk 0 0 0 tg1cc3pr2 tg1cc3pr1 tg1cc3pr0 fffff16a h tg1cc4ic tg1cc4if tg1cc4mk 0 0 0 tg1cc4pr2 tg1cc4pr1 tg1cc4pr0 fffff16c h tg1cc5ic tg1cc5if tg1cc5mk 0 0 0 tg1cc5pr2 tg1cc5pr1 tg1cc5pr0 fffff16e h ty0uv0ic ty0uv0if ty0uv0mk 0 0 0 ty0uv0pr2 ty0uv0pr1 ty0uv0pr0 fffff17 0 h ty0uv1ic ty0uv1if ty0uv1mk 0 0 0 ty0uv1pr2 ty0uv1pr1 ty0uv1pr0 fffff172 h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff174 h c0erric c0errif c0errmk 0 0 0 c0errpr2 c0errpr1 c0errpr0 fffff176 h c0wupic c0wupif c0wupmk 0 0 0 c0wuppr2 c0wuppr1 c0wuppr0 fffff178 h c0recic c0recif c0recmk 0 0 0 c0recpr2 c0recpr1 c0recpr0 fffff17a h c0trxic c0trxif c0trxmk 0 0 0 c0trxpr2 c0trxpr1 c0trxpr0 fffff17c h cb0reic cb0reif cb0remk 0 0 0 cb0repr2 cb0repr1 cb0repr0 fffff17e h cb0ric cb0rif cb0rmk 0 0 0 cb0rpr2 cb0rpr1 cb0rpr0 fffff18 0 h cb0tic cb0tif cb0tmk 0 0 0 cb0tpr2 cb0tpr1 cb0tpr0 fffff182 h ua0reic ua0reif ua0remk 0 0 0 ua0repr2 ua0repr1 ua0repr0 fffff184 h ua0ric ua0rif ua0rmk 0 0 0 ua0rpr2 ua0rpr1 ua0rpr0 fffff186 h ua0tic ua0tif ua0tmk 0 0 0 ua0tpr2 ua0tpr1 ua0tpr0 fffff188 h ua1reic ua1reif ua1remk 0 0 0 ua1repr2 ua1repr1 ua1repr0 fffff18a h ua1ric ua1rif ua1rmk 0 0 0 ua1rpr2 ua1rpr1 ua1rpr0 fffff18c h ua1tic ua1tif ua1tmk 0 0 0 ua1tpr2 ua1tpr1 ua1tpr0 fffff18e h iic0ic iic0if iic0mk 0 0 0 iic0pr2 iic0pr1 iic0pr0 fffff19 0 h iic1ic iic1if iic1mk 0 0 0 iic1pr2 iic1pr1 iic1pr0 fffff192 h sg0ic sg0if sg0mk 0 0 0 sg0pr2 sg0pr1 sg0pr0 fffff194 h dma0ic dma0if dma0mk 0 0 0 dma0pr2 dma0pr1 dma0pr0 fffff196 h dma1ic dma1if dma1mk 0 0 0 dma1pr2 dma1pr1 dma1pr0 fffff198 h dma2ic dma2if dma2mk 0 0 0 dma2pr2 dma2pr1 dma2pr0 fffff19a h dma3ic dma3if dma3mk 0 0 0 dma3pr2 dma3pr1 dma3pr0 fffff19c h int70ic int70if int70mk 0 0 0 int70pr2 int70pr1 int70pr0 fffff19e h int71ic int71if int71mk 0 0 0 int71pr2 int71pr1 int71pr0 fffff1a 0 h p7ic p7if p7mk 0 0 0 p7pr2 p7pr1 p7pr0 fffff1a2 h c1erric c1errif c1errmk 0 0 0 c1errpr2 c1errpr1 c1errpr0 fffff1a4 h c1wupic c1wupif c1wupmk 0 0 0 c1wuppr2 c1wuppr1 c1wuppr0 fffff1a6 h c1recic c1recif c1recmk 0 0 0 c1recpr2 c1recpr1 c1recpr0 fffff1a8 h c1trxic c1trxif c1trxmk 0 0 0 c1trxpr2 c1trxpr1 c1trxpr0 fffff1aa h tz6uvic tz6uvif tz6uvmk 0 0 0 tz6uvpr2 tz6uvpr1 tz6uvpr0 fffff1ac h tz7uvic tz7uvif tz7uvmk 0 0 0 tz7uvpr2 tz7uvpr1 tz7uvpr0 fffff1ae h tz8uvic tz8uvif tz8uvmk 0 0 0 tz8uvpr2 tz8uvpr1 tz8uvpr0 fffff1b 0 h tz9uvic tz9uvif tz9uvmk 0 0 0 tz9uvpr2 tz9uvpr1 tz9uvpr0 table 5-8 addresses and bits of interrupt control registers (2/3) address register bit 7 6 5 4 3 2 1 0
242 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 fffff1b2 h tg2ov0ic tg2ov0if tg2ov0mk 0 0 0 tg2ov0pr2 tg2ov0pr1 tg2ov0pr0 fffff1b4 h tg2ov1ic tg2ov1if tg2ov1mk 0 0 0 tg2ov1pr2 tg2ov1pr1 tg2ov1pr0 fffff1b6 h tg2cc0ic tg2cc0if tg2cc0mk 0 0 0 tg2cc0pr2 tg2cc0pr1 tg2cc0pr0 fffff1b8 h tg2cc1ic tg2cc1if tg2cc1mk 0 0 0 tg2cc1pr2 tg2cc1pr1 tg2cc1pr0 fffff1ba h tg2cc2ic tg2cc2if tg2cc2mk 0 0 0 tg2cc2pr2 tg2cc2pr1 tg2cc2pr0 fffff1bc h tg2cc3ic tg2cc3if tg2cc3mk 0 0 0 tg2cc3pr2 tg2cc3pr1 tg2cc3pr0 fffff1be h tg2cc4ic tg2cc4if tg2cc4mk 0 0 0 tg2cc4pr2 tg2cc4pr1 tg2cc4pr0 fffff1c 0 h tg2cc5ic tg2cc5if tg2cc5mk 0 0 0 tg2cc5pr2 tg2cc5pr1 tg2cc5pr0 fffff1c2 h cb1reic cb1reif cb1remk 0 0 0 cb1repr2 cb1repr1 cb1repr0 fffff1c4 h cb1ric cb1rif cb1rmk 0 0 0 cb1rpr2 cb1rpr1 cb1rpr0 fffff1c6 h cb1tic cb1tif cb1tmk 0 0 0 cb1tpr2 cb1tpr1 cb1tpr0 fffff1c8 h cb2reic cb2reif cb2remk 0 0 0 cb2repr2 cb2repr1 cb2repr0 fffff1ca h cb2ric cb2rif cb2rmk 0 0 0 cb2rpr2 cb2rpr1 cb2rpr0 fffff1cc h cb2tic cb2tif cb2tmk 0 0 0 cb2tpr2 cb2tpr1 cb2tpr0 fffff1ce h lcdic lcdif lcdmk 0 0 0 lcdpr2 lcdpr1 lcdpr0 fffff1d 0 h c2erric c2errif c2errmk 0 0 0 c2errpr2 c2errpr1 c2errpr0 fffff1d2 h c2wupic c2wupif c2wupmk 0 0 0 c2wuppr2 c2wuppr1 c2wuppr0 fffff1d4 h c2recic c2recif c2recmk 0 0 0 c2recpr2 c2recpr1 c2recpr0 fffff1d6 h c2trxic c2trxif c2trxmk 0 0 0 c2trxpr2 c2trxpr1 c2trxpr0 table 5-9 addresses and bits of interrupt control registers of pd70f3420 (otf), pd70f3421, pd70f3421 (otf), pd70f3422, pd70f3422 (otf), pd70f3423 (1/3) address register bit 7 6 5 4 3 2 1 0 fffff110 h vc0ic vc0if vc0mk 0 0 0 vc0pr2 vc0pr1 vc0pr0 fffff112 h vc1ic vc1if vc1mk 0 0 0 vc1pr2 vc1pr1 vc1pr0 fffff114 h wt0uvic wt0uvif wt0uvmk 0 0 0 wt0uvpr2 wt0uvpr1 wt0uvpr0 fffff116 h wt1uvic wt1uvif wt1uvmk 0 0 0 wt1uvpr2 wt1uvpr1 wt1uvpr0 fffff11a h tm01ic tm01if tm01mk 0 0 0 tm01pr2 tm01pr1 tm01pr0 fffff11c h p0ic p0if p0mk 0 0 0 p0pr2 p0pr1 p0pr0 fffff11e h p1ic p1if p1mk 0 0 0 p1pr2 p1pr1 p1pr0 fffff120 h p2ic p2if p2mk 0 0 0 p2pr2 p2pr1 p2pr0 fffff122 h p3ic p3if p3mk 0 0 0 p3pr2 p3pr1 p3pr0 fffff124 h p4ic p4if p4mk 0 0 0 p4pr2 p4pr1 p4pr0 fffff126 h p5ic p5if p5mk 0 0 0 p5pr2 p5pr1 p5pr0 fffff128 h p6ic p6if p6mk 0 0 0 p6pr2 p6pr1 p6pr0 fffff12a h tz0uvic tz0uvif tz0uvmk 0 0 0 tz0uvpr2 tz0uvpr1 tz0uvpr0 fffff12c h tz1uvic tz1uvif tz1uvmk 0 0 0 tz1uvpr2 tz1uvpr1 tz1uvpr0 fffff12e h tz2uvic tz2uvif tz2uvmk 0 0 0 tz2uvpr2 tz2uvpr1 tz2uvpr0 fffff130 h tz3uvic tz3uvif tz3uvmk 0 0 0 tz3uvpr2 tz3uvpr1 tz3uvpr0 table 5-8 addresses and bits of interrupt control registers (3/3) address register bit 7 6 5 4 3 2 1 0
243 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 fffff132 h tz4uvic tz4uvif tz4uvmk 0 0 0 tz4uvpr2 tz4uvpr1 tz4uvpr0 fffff134 h tz5uvic tz5uvif tz5uvmk 0 0 0 tz5uvpr2 tz5uvpr1 tz5uvpr0 fffff136 h tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff138 h tp0cc0ic tp0cc0if tp0cc0mk 0 0 0 tp0cc0pr2 tp0cc0pr1 tp0cc0pr0 fffff13a h tp0cc1ic tp0cc1if tp0cc1mk 0 0 0 tp0cc1pr2 tp0cc1pr1 tp0cc1pr0 fffff13c h tp1ovic tp1ovif tp1ovmk 0 0 0 tp1ovpr2 tp1ovpr1 tp1ovpr0 fffff13e h tp1cc0ic tp1cc0if tp1cc0mk 0 0 0 tp1cc0pr2 tp1cc0pr1 tp1cc0pr0 fffff140 h tp1cc1ic tp1cc1if tp1cc1mk 0 0 0 tp1cc1pr2 tp1cc1pr1 tp1cc1pr0 fffff142 h tp2ovic tp2ovif tp2ovmk 0 0 0 tp2ovpr2 tp2ovpr1 tp2ovpr0 fffff144 h tp2cc0ic tp2cc0if tp2cc0mk 0 0 0 tp2cc0pr2 tp2cc0pr1 tp2cc0pr0 fffff146 h tp2cc1ic tp2cc1if tp2cc1mk 0 0 0 tp2cc1pr2 tp2cc1pr1 tp2cc1pr0 fffff148 h tp3ovic tp3ovif tp3ovmk 0 0 0 tp3ovpr2 tp3ovpr1 tp3ovpr0 fffff14a h tp3cc0ic tp3cc0if tp3cc0mk 0 0 0 tp3cc0pr2 tp3cc0pr1 tp3cc0pr0 fffff14c h tp3cc1ic tp3cc1if tp3cc1mk 0 0 0 tp3cc1pr2 tp3cc1pr1 tp3cc1pr0 fffff14e h tg0ov0ic tg0ov0if tg0ov0mk 0 0 0 tg0ov0pr2 tg0ov0pr1 tg0ov0pr0 fffff150 h tg0ov1ic tg0ov1if tg0ov1mk 0 0 0 tg0ov1pr2 tg0ov1pr1 tg0ov1pr0 fffff152 h tg0cc0ic tg0cc0if tg0cc0mk 0 0 0 tg0cc0pr2 tg0cc0pr1 tg0cc0pr0 fffff154 h tg0cc1ic tg0cc1if tg0cc1mk 0 0 0 tg0cc1pr2 tg0cc1pr1 tg0cc1pr0 fffff156 h tg0cc2ic tg0cc2if tg0cc2mk 0 0 0 tg0cc2pr2 tg0cc2pr1 tg0cc2pr0 fffff158 h tg0cc3ic tg0cc3if tg0cc3mk 0 0 0 tg0cc3pr2 tg0cc3pr1 tg0cc3pr0 fffff15a h tg0cc4ic tg0cc4if tg0cc4mk 0 0 0 tg0cc4pr2 tg0cc4pr1 tg0cc4pr0 fffff15c h tg0cc5ic tg0cc5if tg0cc5mk 0 0 0 tg0cc5pr2 tg0cc5pr1 tg0cc5pr0 fffff15e h tg1ov0ic tg1ov0if tg1ov0mk 0 0 0 tg1ov0pr2 tg1ov0pr1 tg1ov0pr0 fffff160 h tg1ov1ic tg1ov1if tg1ov1mk 0 0 0 tg1ov1pr2 tg1ov1pr1 tg1ov1pr0 fffff162 h tg1cc0c tg1cc0if tg1cc0mk 0 0 0 tg1cc0pr2 tg1cc0pr1 tg1cc0pr0 fffff164 h tg1cc1ic tg1cc1if tg1cc1mk 0 0 0 tg1cc1pr2 tg1cc1pr1 tg1cc1pr0 fffff166 h tg1cc2ic tg1cc2if tg1cc2mk 0 0 0 tg1cc2pr2 tg1cc2pr1 tg1cc2pr0 fffff168 h tg1cc3ic tg1cc3if tg1cc3mk 0 0 0 tg1cc3pr2 tg1cc3pr1 tg1cc3pr0 fffff16a h tg1cc4ic tg1cc4if tg1cc4mk 0 0 0 tg1cc4pr2 tg1cc4pr1 tg1cc4pr0 fffff16c h tg1cc5ic tg1cc5if tg1cc5mk 0 0 0 tg1cc5pr2 tg1cc5pr1 tg1cc5pr0 fffff16e h ty0uv0ic ty0uv0if ty0uv0mk 0 0 0 ty0uv0pr2 ty0uv0pr1 ty0uv0pr0 fffff170 h ty0uv1ic ty0uv1if ty0uv1mk 0 0 0 ty0uv1pr2 ty0uv1pr1 ty0uv1pr0 fffff172 h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff174 h c0erric c0errif c0errmk 0 0 0 c0errpr2 c0errpr1 c0errpr0 fffff176 h c0wupic c0wupif c0wupmk 0 0 0 c0wuppr2 c0wuppr1 c0wuppr0 fffff178 h c0recic c0recif c0recmk 0 0 0 c0recpr2 c0recpr1 c0recpr0 fffff17a h c0trxic c0trxif c0trxmk 0 0 0 c0trxpr2 c0trxpr1 c0trxpr0 fffff17c h cb0reic cb0reif cb0remk 0 0 0 cb0repr2 cb0repr1 cb0repr0 fffff17e h cb0ric cb0rif cb0rmk 0 0 0 cb0rpr2 cb0rpr1 cb0rpr0 table 5-9 addresses and bits of interrupt control registers of pd70f3420 (otf), pd70f3421, pd70f3421 (otf), pd70f3422, pd70f3422 (otf), pd70f3423 (2/3) address register bit 7 6 5 4 3 2 1 0
244 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 fffff180 h cb0tic cb0tif cb0tmk 0 0 0 cb0tpr2 cb0tpr1 cb0tpr0 fffff182 h ua0reic ua0reif ua0remk 0 0 0 ua0repr2 ua0repr1 ua0repr0 fffff184 h ua0ric ua0rif ua0rmk 0 0 0 ua0rpr2 ua0rpr1 ua0rpr0 fffff186 h ua0tic ua0tif ua0tmk 0 0 0 ua0tpr2 ua0tpr1 ua0tpr0 fffff188 h ua1reic ua1reif ua1remk 0 0 0 ua1repr2 ua1repr1 ua1repr0 fffff18a h ua1ric ua1rif ua1rmk 0 0 0 ua1rpr2 ua1rpr1 ua1rpr0 fffff18c h ua1tic ua1tif ua1tmk 0 0 0 ua1tpr2 ua1tpr1 ua1tpr0 fffff18e h iic0ic iic0if iic0mk 0 0 0 iic0pr2 iic0pr1 iic0pr0 fffff190 h iic1ic iic1if iic1mk 0 0 0 iic1pr2 iic1pr1 iic1pr0 fffff192 h sg0ic sg0if sg0mk 0 0 0 sg0pr2 sg0pr1 sg0pr0 fffff194 h dma0ic dma0if dma0mk 0 0 0 dma0pr2 dma0pr1 dma0pr0 fffff196 h dma1ic dma1if dma1mk 0 0 0 dma1pr2 dma1pr1 dma1pr0 fffff198 h dma2ic dma2if dma2mk 0 0 0 dma2pr2 dma2pr1 dma2pr0 fffff19a h dma3ic dma3if dma3mk 0 0 0 dma3pr2 dma3pr1 dma3pr0 fffff19c h int70ic int70if int70mk 0 0 0 int70pr2 int70pr1 int70pr0 fffff19e h int71ic int71if int71mk 0 0 0 int71pr2 int71pr1 int71pr0 fffff1a2 h c1erric c1errif c1errmk 0 0 0 c1errpr2 c1errpr1 c1errpr0 fffff1a4 h c1wupic c1wupif c1wupmk 0 0 0 c1wuppr2 c1wuppr1 c1wuppr0 fffff1a6 h c1recic c1recif c1recmk 0 0 0 c1recpr2 c1recpr1 c1recpr0 fffff1a8 h c1trxic c1trxif c1trxmk 0 0 0 c1trxpr2 c1trxpr1 c1trxpr0 fffff1c2 h cb1reic cb1reif cb1remk 0 0 0 cb1repr2 cb1repr1 cb1repr0 fffff1c4 h cb1ric cb1rif cb1rmk 0 0 0 cb1rpr2 cb1rpr1 cb1rpr0 fffff1c6 h cb1tic cb1tif cb1tmk 0 0 0 cb1tpr2 cb1tpr1 cb1tpr0 fffff1d0 h c2erric a c2errif c2errmk 0 0 0 c2errpr2 c2errpr1 c2errpr0 fffff1d2 h c2wupic a c2wupif c2wupmk 0 0 0 c2wuppr2 c2wuppr1 c2wuppr0 fffff1d4 h c2recic a c2recif c2recmk 0 0 0 c2recpr2 c2recpr1 c2recpr0 fffff1d6 h c2trxic a c2trxif c2trxmk 0 0 0 c2trxpr2 c2trxpr1 c2trxpr0 a) pd70f3423 only table 5-10 addresses and bits of interrupt control registers of pd70f3424, pd70f3425, pd70f3426, pd70f3427 (1/4) address register bit 7 6 5 4 3 2 1 0 fffff110 h vc0ic vc0if vc0mk 0 0 0 vc0pr2 vc0pr1 vc0pr0 fffff112 h vc1ic vc1if vc1mk 0 0 0 vc1pr2 vc1pr1 vc1pr0 fffff114 h wt0uvic wt0uvif wt0uvmk 0 0 0 wt0uvpr2 wt0uvpr1 wt0uvpr0 fffff116 h wt1uvic wt1uvif wt1uvmk 0 0 0 wt1uvpr2 wt1uvpr1 wt1uvpr0 fffff11a h tm01ic tm01if tm01mk 0 0 0 tm01pr2 tm01pr1 tm01pr0 fffff11c h p0ic p0if p0mk 0 0 0 p0pr2 p0pr1 p0pr0 table 5-9 addresses and bits of interrupt control registers of pd70f3420 (otf), pd70f3421, pd70f3421 (otf), pd70f3422, pd70f3422 (otf), pd70f3423 (3/3) address register bit 7 6 5 4 3 2 1 0
245 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 fffff11e h p1ic p1if p1mk 0 0 0 p1pr2 p1pr1 p1pr0 fffff120 h p2ic p2if p2mk 0 0 0 p2pr2 p2pr1 p2pr0 fffff122 h p3ic p3if p3mk 0 0 0 p3pr2 p3pr1 p3pr0 fffff124 h p4ic p4if p4mk 0 0 0 p4pr2 p4pr1 p4pr0 fffff126 h p5ic p5if p5mk 0 0 0 p5pr2 p5pr1 p5pr0 fffff128 h p6ic p6if p6mk 0 0 0 p6pr2 p6pr1 p6pr0 fffff12a h tz0uvic tz0uvif tz0uvmk 0 0 0 tz0uvpr2 tz0uvpr1 tz0uvpr0 fffff12c h tz1uvic tz1uvif tz1uvmk 0 0 0 tz1uvpr2 tz1uvpr1 tz1uvpr0 fffff12e h tz2uvic tz2uvif tz2uvmk 0 0 0 tz2uvpr2 tz2uvpr1 tz2uvpr0 fffff130 h tz3uvic tz3uvif tz3uvmk 0 0 0 tz3uvpr2 tz3uvpr1 tz3uvpr0 fffff132 h tz4uvic tz4uvif tz4uvmk 0 0 0 tz4uvpr2 tz4uvpr1 tz4uvpr0 fffff134 h tz5uvic tz5uvif tz5uvmk 0 0 0 tz5uvpr2 tz5uvpr1 tz5uvpr0 fffff136 h tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff138 h tp0cc0ic tp0cc0if tp0cc0mk 0 0 0 tp0cc0pr2 tp0cc0pr1 tp0cc0pr0 fffff13a h tp0cc1ic tp0cc1if tp0cc1mk 0 0 0 tp0cc1pr2 tp0cc1pr1 tp0cc1pr0 fffff13c h tp1ovic tp1ovif tp1ovmk 0 0 0 tp1ovpr2 tp1ovpr1 tp1ovpr0 fffff13e h tp1cc0ic tp1cc0if tp1cc0mk 0 0 0 tp1cc0pr2 tp1cc0pr1 tp1cc0pr0 fffff140 h tp1cc1ic tp1cc1if tp1cc1mk 0 0 0 tp1cc1pr2 tp1cc1pr1 tp1cc1pr0 fffff142 h tp2ovic tp2ovif tp2ovmk 0 0 0 tp2ovpr2 tp2ovpr1 tp2ovpr0 fffff144 h tp2cc0ic tp2cc0if tp2cc0mk 0 0 0 tp2cc0pr2 tp2cc0pr1 tp2cc0pr0 fffff146 h tp2cc1ic tp2cc1if tp2cc1mk 0 0 0 tp2cc1pr2 tp2cc1pr1 tp2cc1pr0 fffff148 h tp3ovic tp3ovif tp3ovmk 0 0 0 tp3ovpr2 tp3ovpr1 tp3ovpr0 fffff14a h tp3cc0ic tp3cc0if tp3cc0mk 0 0 0 tp3cc0pr2 tp3cc0pr1 tp3cc0pr0 fffff14c h tp3cc1ic tp3cc1if tp3cc1mk 0 0 0 tp3cc1pr2 tp3cc1pr1 tp3cc1pr0 fffff14e h tg0ov0ic tg0ov0if tg0ov0mk 0 0 0 tg0ov0pr2 tg0ov0pr1 tg0ov0pr0 fffff150 h tg0ov1ic tg0ov1if tg0ov1mk 0 0 0 tg0ov1pr2 tg0ov1pr1 tg0ov1pr0 fffff152 h tg0cc0ic tg0cc0if tg0cc0mk 0 0 0 tg0cc0pr2 tg0cc0pr1 tg0cc0pr0 fffff154 h tg0cc1ic tg0cc1if tg0cc1mk 0 0 0 tg0cc1pr2 tg0cc1pr1 tg0cc1pr0 fffff156 h tg0cc2ic tg0cc2if tg0cc2mk 0 0 0 tg0cc2pr2 tg0cc2pr1 tg0cc2pr0 fffff158 h tg0cc3ic tg0cc3if tg0cc3mk 0 0 0 tg0cc3pr2 tg0cc3pr1 tg0cc3pr0 fffff15a h tg0cc4ic tg0cc4if tg0cc4mk 0 0 0 tg0cc4pr2 tg0cc4pr1 tg0cc4pr0 fffff15c h tg0cc5ic tg0cc5if tg0cc5mk 0 0 0 tg0cc5pr2 tg0cc5pr1 tg0cc5pr0 fffff15e h tg1ov0ic tg1ov0if tg1ov0mk 0 0 0 tg1ov0pr2 tg1ov0pr1 tg1ov0pr0 fffff160 h tg1ov1ic tg1ov1if tg1ov1mk 0 0 0 tg1ov1pr2 tg1ov1pr1 tg1ov1pr0 fffff162 h tg1cc0c tg1cc0if tg1cc0mk 0 0 0 tg1cc0pr2 tg1cc0pr1 tg1cc0pr0 fffff164 h tg1cc1ic tg1cc1if tg1cc1mk 0 0 0 tg1cc1pr2 tg1cc1pr1 tg1cc1pr0 fffff166 h tg1cc2ic tg1cc2if tg1cc2mk 0 0 0 tg1cc2pr2 tg1cc2pr1 tg1cc2pr0 fffff168 h tg1cc3ic tg1cc3if tg1cc3mk 0 0 0 tg1cc3pr2 tg1cc3pr1 tg1cc3pr0 fffff16a h tg1cc4ic tg1cc4if tg1cc4mk 0 0 0 tg1cc4pr2 tg1cc4pr1 tg1cc4pr0 fffff16c h tg1cc5ic tg1cc5if tg1cc5mk 0 0 0 tg1cc5pr2 tg1cc5pr1 tg1cc5pr0 table 5-10 addresses and bits of interrupt control registers of pd70f3424, pd70f3425, pd70f3426, pd70f3427 (2/4) address register bit 7 6 5 4 3 2 1 0
246 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 fffff16e h ty0uv0ic ty0uv0if ty0uv0mk 0 0 0 ty0uv0pr2 ty0uv0pr1 ty0uv0pr0 fffff170 h ty0uv1ic ty0uv1if ty0uv1mk 0 0 0 ty0uv1pr2 ty0uv1pr1 ty0uv1pr0 fffff172 h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff174 h c0erric c0errif c0errmk 0 0 0 c0errpr2 c0errpr1 c0errpr0 fffff176 h c0wupic c0wupif c0wupmk 0 0 0 c0wuppr2 c0wuppr1 c0wuppr0 fffff178 h c0recic c0recif c0recmk 0 0 0 c0recpr2 c0recpr1 c0recpr0 fffff17a h c0trxic c0trxif c0trxmk 0 0 0 c0trxpr2 c0trxpr1 c0trxpr0 fffff17c h cb0reic cb0reif cb0remk 0 0 0 cb0repr2 cb0repr1 cb0repr0 fffff17e h cb0ric cb0rif cb0rmk 0 0 0 cb0rpr2 cb0rpr1 cb0rpr0 fffff180 h cb0tic cb0tif cb0tmk 0 0 0 cb0tpr2 cb0tpr1 cb0tpr0 fffff182 h ua0reic ua0reif ua0remk 0 0 0 ua0repr2 ua0repr1 ua0repr0 fffff184 h ua0ric ua0rif ua0rmk 0 0 0 ua0rpr2 ua0rpr1 ua0rpr0 fffff186 h ua0tic ua0tif ua0tmk 0 0 0 ua0tpr2 ua0tpr1 ua0tpr0 fffff188 h ua1reic ua1reif ua1remk 0 0 0 ua1repr2 ua1repr1 ua1repr0 fffff18a h ua1ric ua1rif ua1rmk 0 0 0 ua1rpr2 ua1rpr1 ua1rpr0 fffff18c h ua1tic ua1tif ua1tmk 0 0 0 ua1tpr2 ua1tpr1 ua1tpr0 fffff18e h iic0ic iic0if iic0mk 0 0 0 iic0pr2 iic0pr1 iic0pr0 fffff190 h iic1ic iic1if iic1mk 0 0 0 iic1pr2 iic1pr1 iic1pr0 fffff192 h sg0ic sg0if sg0mk 0 0 0 sg0pr2 sg0pr1 sg0pr0 fffff194 h dma0ic dma0if dma0mk 0 0 0 dma0pr2 dma0pr1 dma0pr0 fffff196 h dma1ic dma1if dma1mk 0 0 0 dma1pr2 dma1pr1 dma1pr0 fffff198 h dma2ic dma2if dma2mk 0 0 0 dma2pr2 dma2pr1 dma2pr0 fffff19a h dma3ic dma3if dma3mk 0 0 0 dma3pr2 dma3pr1 dma3pr0 fffff19c h int70ic int70if int70mk 0 0 0 int70pr2 int70pr1 int70pr0 fffff19e h int71ic int71if int71mk 0 0 0 int71pr2 int71pr1 int71pr0 fffff1a0 h p7ic p7if p7mk 0 0 0 p7pr2 p7pr1 p7pr0 fffff1a2 h c1erric c1errif c1errmk 0 0 0 c1errpr2 c1errpr1 c1errpr0 fffff1a4 h c1wupic c1wupif c1wupmk 0 0 0 c1wuppr2 c1wuppr1 c1wuppr0 fffff1a6 h c1recic c1recif c1recmk 0 0 0 c1recpr2 c1recpr1 c1recpr0 fffff1a8 h c1trxic c1trxif c1trxmk 0 0 0 c1trxpr2 c1trxpr1 c1trxpr0 fffff1aa h tz6uvic tz6uvif tz6uvmk 0 0 0 tz6uvpr2 tz6uvpr1 tz6uvpr0 fffff1ac h tz7uvic tz7uvif tz7uvmk 0 0 0 tz7uvpr2 tz7uvpr1 tz7uvpr0 fffff1ae h tz8uvic tz8uvif tz8uvmk 0 0 0 tz8uvpr2 tz8uvpr1 tz8uvpr0 fffff1b0 h tz9uvic tz9uvif tz9uvmk 0 0 0 tz9uvpr2 tz9uvpr1 tz9uvpr0 fffff1b2 h tg2ov0ic tg2ov0if tg2ov0mk 0 0 0 tg2ov0pr2 tg2ov0pr1 tg2ov0pr0 fffff1b4 h tg2ov1ic tg2ov1if tg2ov1mk 0 0 0 tg2ov1pr2 tg2ov1pr1 tg2ov1pr0 fffff1b6 h tg2cc0ic tg2cc0if tg2cc0mk 0 0 0 tg2cc0pr2 tg2cc0pr1 tg2cc0pr0 fffff1b8 h tg2cc1ic tg2cc1if tg2cc1mk 0 0 0 tg2cc1pr2 tg2cc1pr1 tg2cc1pr0 fffff1ba h tg2cc2ic tg2cc2if tg2cc2mk 0 0 0 tg2cc2pr2 tg2cc2pr1 tg2cc2pr0 fffff1bc h tg2cc3ic tg2cc3if tg2cc3mk 0 0 0 tg2cc3pr2 tg2cc3pr1 tg2cc3pr0 table 5-10 addresses and bits of interrupt control registers of pd70f3424, pd70f3425, pd70f3426, pd70f3427 (3/4) address register bit 7 6 5 4 3 2 1 0
247 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 fffff1be h tg2cc4ic tg2cc4if tg2cc4mk 0 0 0 tg2cc4pr2 tg2cc4pr1 tg2cc4pr0 fffff1c0 h tg2cc5ic tg2cc5if tg2cc5mk 0 0 0 tg2cc5pr2 tg2cc5pr1 tg2cc5pr0 fffff1c2 h cb1reic cb1reif cb1remk 0 0 0 cb1repr2 cb1repr1 cb1repr0 fffff1c4 h cb1ric cb1rif cb1rmk 0 0 0 cb1rpr2 cb1rpr1 cb1rpr0 fffff1c6 h cb1tic cb1tif cb1tmk 0 0 0 cb1tpr2 cb1tpr1 cb1tpr0 fffff1c8 h cb2reic cb2reif cb2remk 0 0 0 cb2repr2 cb2repr1 cb2repr0 fffff1ca h cb2ric cb2rif cb2rmk 0 0 0 cb2rpr2 cb2rpr1 cb2rpr0 fffff1cc h cb2tic cb2tif cb2tmk 0 0 0 cb2tpr2 cb2tpr1 cb2tpr0 fffff1ce h lcdic lcdif lcdmk 0 0 0 lcdpr2 lcdpr1 lcdpr0 fffff1d0 h c2erric a c2errif c2errmk 0 0 0 c2errpr2 c2errpr1 c2errpr0 fffff1d2 h c2wupic a c2wupif c2wupmk 0 0 0 c2wuppr2 c2wuppr1 c2wuppr0 fffff1d4 h c2recic a c2recif c2recmk 0 0 0 c2recpr2 c2recpr1 c2recpr0 fffff1d6 h c2trxic a c2trxif c2trxmk 0 0 0 c2trxpr2 c2trxpr1 c2trxpr0 a) pd70f3424, pd70f3427 only table 5-11 addresses and bits of interrupt control registers (1/3) address register bit 7 6 5 4 3 2 1 0 fffff110 h vc0ic vc0if vc0mk 0 0 0 vc0pr2 vc0pr1 vc0pr0 fffff112 h vc1ic vc1if vc1mk 0 0 0 vc1pr2 vc1pr1 vc1pr0 fffff114 h wt0uvic wt0uvif wt0uvmk 0 0 0 wt0uvpr2 wt0uvpr1 wt0uvpr0 fffff116 h wt1uvic wt1uvif wt1uvmk 0 0 0 wt1uvpr2 wt1uvpr1 wt1uvpr0 fffff11a h tm01ic tm01if tm01mk 0 0 0 tm01pr2 tm01pr1 tm01pr0 fffff11c h p0ic p0if p0mk 0 0 0 p0pr2 p0pr1 p0pr0 fffff11e h p1ic p1if p1mk 0 0 0 p1pr2 p1pr1 p1pr0 fffff120 h p2ic p2if p2mk 0 0 0 p2pr2 p2pr1 p2pr0 fffff122 h p3ic p3if p3mk 0 0 0 p3pr2 p3pr1 p3pr0 fffff124 h p4ic p4if p4mk 0 0 0 p4pr2 p4pr1 p4pr0 fffff126 h p5ic p5if p5mk 0 0 0 p5pr2 p5pr1 p5pr0 fffff128 h p6ic p6if p6mk 0 0 0 p6pr2 p6pr1 p6pr0 fffff12a h tz0uvic tz0uvif tz0uvmk 0 0 0 tz0uvpr2 tz0uvpr1 tz0uvpr0 fffff12c h tz1uvic tz1uvif tz1uvmk 0 0 0 tz1uvpr2 tz1uvpr1 tz1uvpr0 fffff12e h tz2uvic tz2uvif tz2uvmk 0 0 0 tz2uvpr2 tz2uvpr1 tz2uvpr0 fffff130 h tz3uvic tz3uvif tz3uvmk 0 0 0 tz3uvpr2 tz3uvpr1 tz3uvpr0 fffff132 h tz4uvic tz4uvif tz4uvmk 0 0 0 tz4uvpr2 tz4uvpr1 tz4uvpr0 fffff134 h tz5uvic tz5uvif tz5uvmk 0 0 0 tz5uvpr2 tz5uvpr1 tz5uvpr0 fffff136 h tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff138 h tp0cc0ic tp0cc0if tp0cc0mk 0 0 0 tp0cc0pr2 tp0cc0pr1 tp0cc0pr0 fffff13a h tp0cc1ic tp0cc1if tp0cc1mk 0 0 0 tp0cc1pr2 tp0cc1pr1 tp0cc1pr0 table 5-10 addresses and bits of interrupt control registers of pd70f3424, pd70f3425, pd70f3426, pd70f3427 (4/4) address register bit 7 6 5 4 3 2 1 0
248 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 fffff13c h tp1ovic tp1ovif tp1ovmk 0 0 0 tp1ovpr2 tp1ovpr1 tp1ovpr0 fffff13e h tp1cc0ic tp1cc0if tp1cc0mk 0 0 0 tp1cc0pr2 tp1cc0pr1 tp1cc0pr0 fffff140 h tp1cc1ic tp1cc1if tp1cc1mk 0 0 0 tp1cc1pr2 tp1cc1pr1 tp1cc1pr0 fffff142 h tp2ovic tp2ovif tp2ovmk 0 0 0 tp2ovpr2 tp2ovpr1 tp2ovpr0 fffff144 h tp2cc0ic tp2cc0if tp2cc0mk 0 0 0 tp2cc0pr2 tp2cc0pr1 tp2cc0pr0 fffff146 h tp2cc1ic tp2cc1if tp2cc1mk 0 0 0 tp2cc1pr2 tp2cc1pr1 tp2cc1pr0 fffff148 h tp3ovic tp3ovif tp3ovmk 0 0 0 tp3ovpr2 tp3ovpr1 tp3ovpr0 fffff14a h tp3cc0ic tp3cc0if tp3cc0mk 0 0 0 tp3cc0pr2 tp3cc0pr1 tp3cc0pr0 fffff14c h tp3cc1ic tp3cc1if tp3cc1mk 0 0 0 tp3cc1pr2 tp3cc1pr1 tp3cc1pr0 fffff14e h tg0ov0ic tg0ov0if tg0ov0mk 0 0 0 tg0ov0pr2 tg0ov0pr1 tg0ov0pr0 fffff150 h tg0ov1ic tg0ov1if tg0ov1mk 0 0 0 tg0ov1pr2 tg0ov1pr1 tg0ov1pr0 fffff152 h tg0cc0ic tg0cc0if tg0cc0mk 0 0 0 tg0cc0pr2 tg0cc0pr1 tg0cc0pr0 fffff154 h tg0cc1ic tg0cc1if tg0cc1mk 0 0 0 tg0cc1pr2 tg0cc1pr1 tg0cc1pr0 fffff156 h tg0cc2ic tg0cc2if tg0cc2mk 0 0 0 tg0cc2pr2 tg0cc2pr1 tg0cc2pr0 fffff158 h tg0cc3ic tg0cc3if tg0cc3mk 0 0 0 tg0cc3pr2 tg0cc3pr1 tg0cc3pr0 fffff15a h tg0cc4ic tg0cc4if tg0cc4mk 0 0 0 tg0cc4pr2 tg0cc4pr1 tg0cc4pr0 fffff15c h tg0cc5ic tg0cc5if tg0cc5mk 0 0 0 tg0cc5pr2 tg0cc5pr1 tg0cc5pr0 fffff15e h tg1ov0ic tg1ov0if tg1ov0mk 0 0 0 tg1ov0pr2 tg1ov0pr1 tg1ov0pr0 fffff160 h tg1ov1ic tg1ov1if tg1ov1mk 0 0 0 tg1ov1pr2 tg1ov1pr1 tg1ov1pr0 fffff162 h tg1cc0c tg1cc0if tg1cc0mk 0 0 0 tg1cc0pr2 tg1cc0pr1 tg1cc0pr0 fffff164 h tg1cc1ic tg1cc1if tg1cc1mk 0 0 0 tg1cc1pr2 tg1cc1pr1 tg1cc1pr0 fffff166 h tg1cc2ic tg1cc2if tg1cc2mk 0 0 0 tg1cc2pr2 tg1cc2pr1 tg1cc2pr0 fffff168 h tg1cc3ic tg1cc3if tg1cc3mk 0 0 0 tg1cc3pr2 tg1cc3pr1 tg1cc3pr0 fffff16a h tg1cc4ic tg1cc4if tg1cc4mk 0 0 0 tg1cc4pr2 tg1cc4pr1 tg1cc4pr0 fffff16c h tg1cc5ic tg1cc5if tg1cc5mk 0 0 0 tg1cc5pr2 tg1cc5pr1 tg1cc5pr0 fffff16e h ty0cc0ic ty0cc0if ty0cc0mk 0 0 0 ty0cc0pr2 ty0cc0pr1 ty0cc0pr0 fffff170 h ty0cc1ic ty0cc1if ty0cc1mk 0 0 0 ty0cc1pr2 ty0cc1pr1 ty0cc1pr0 fffff172 h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff174 h c0erric c0errif c0errmk 0 0 0 c0errpr2 c0errpr1 c0errpr0 fffff176 h c0wupic c0wupif c0wupmk 0 0 0 c0wuppr2 c0wuppr1 c0wuppr0 fffff178 h c0recic c0recif c0recmk 0 0 0 c0recpr2 c0recpr1 c0recpr0 fffff17a h c0trxic c0trxif c0trxmk 0 0 0 c0trxpr2 c0trxpr1 c0trxpr0 fffff17c h cb0reic cb0reif cb0remk 0 0 0 cb0repr2 cb0repr1 cb0repr0 fffff17e h cb0ric cb0rif cb0rmk 0 0 0 cb0rpr2 cb0rpr1 cb0rpr0 fffff180 h cb0tic cb0tif cb0tmk 0 0 0 cb0tpr2 cb0tpr1 cb0tpr0 fffff182 h ua0reic ua0reif ua0remk 0 0 0 ua0repr2 ua0repr1 ua0repr0 fffff184 h ua0ric ua0rif ua0rmk 0 0 0 ua0rpr2 ua0rpr1 ua0rpr0 fffff186 h ua0tic ua0tif ua0tmk 0 0 0 ua0tpr2 ua0tpr1 ua0tpr0 fffff188 h ua1reic ua1reif ua1remk 0 0 0 ua1repr2 ua1repr1 ua1repr0 fffff18a h ua1ric ua1rif ua1rmk 0 0 0 ua1rpr2 ua1rpr1 ua1rpr0 table 5-11 addresses and bits of interrupt control registers (2/3) address register bit 7 6 5 4 3 2 1 0
249 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 fffff18c h ua1tic ua1tif ua1tmk 0 0 0 ua1tpr2 ua1tpr1 ua1tpr0 fffff18e h iic0ic iic0if iic0mk 0 0 0 iic0pr2 iic0pr1 iic0pr0 fffff190 h iic1ic iic1if iic1mk 0 0 0 iic1pr2 iic1pr1 iic1pr0 fffff192 h sg0ic sg0if sg0mk 0 0 0 sg0pr2 sg0pr1 sg0pr0 fffff194 h dma0ic dma0if dma0mk 0 0 0 dma0pr2 dma0pr1 dma0pr0 fffff196 h dma1ic dma1if dma1mk 0 0 0 dma1pr2 dma1pr1 dma1pr0 fffff198 h dma2ic dma2if dma2mk 0 0 0 dma2pr2 dma2pr1 dma2pr0 fffff19a h dma3ic dma3if dma3mk 0 0 0 dma3pr2 dma3pr1 dma3pr0 fffff19c h int70ic int70if int70mk 0 0 0 int70pr2 int70pr1 int70pr0 fffff19e h int71ic int71if int71mk 0 0 0 int71pr2 int71pr1 int71pr0 fffff1a0 h p7ic a p7if p7mk 0 0 0 p7pr2 p7pr1 p7pr0 fffff1a2 h c1erric c1errif c1errmk 0 0 0 c1errpr2 c1errpr1 c1errpr0 fffff1a4 h c1wupic c1wupif c1wupmk 0 0 0 c1wuppr2 c1wuppr1 c1wuppr0 fffff1a6 h c1recic c1recif c1recmk 0 0 0 c1recpr2 c1recpr1 c1recpr0 fffff1a8 h c1trxic c1trxif c1trxmk 0 0 0 c1trxpr2 c1trxpr1 c1trxpr0 fffff1aa h tz6uvic a tz6uvif tz6uvmk 0 0 0 tz6uvpr2 tz6uvpr1 tz6uvpr0 fffff1ac h tz7uvic a tz7uvif tz7uvmk 0 0 0 tz7uvpr2 tz7uvpr1 tz7uvpr0 fffff1ae h tz8uvic a tz8uvif tz8uvmk 0 0 0 tz8uvpr2 tz8uvpr1 tz8uvpr0 fffff1b0 h tz9uvic a tz9uvif tz9uvmk 0 0 0 tz9uvpr2 tz9uvpr1 tz9uvpr0 fffff1b2 h tg2ov0ic tg2ov0if tg2ov0mk 0 0 0 tg2ov0pr2 tg2ov0pr1 tg2ov0pr0 fffff1b4 h tg2ov1ic tg2ov1if tg2ov1mk 0 0 0 tg2ov1pr2 tg2ov1pr1 tg2ov1pr0 fffff1b6 h tg2cc0ic tg2cc0if tg2cc0mk 0 0 0 tg2cc0pr2 tg2cc0pr1 tg2cc0pr0 fffff1b8 h tg2cc1ic tg2cc1if tg2cc1mk 0 0 0 tg2cc1pr2 tg2cc1pr1 tg2cc1pr0 fffff1ba h tg2cc2ic tg2cc2if tg2cc2mk 0 0 0 tg2cc2pr2 tg2cc2pr1 tg2cc2pr0 fffff1bc h tg2cc3ic tg2cc3if tg2cc3mk 0 0 0 tg2cc3pr2 tg2cc3pr1 tg2cc3pr0 fffff1be h tg2cc4ic tg2cc4if tg2cc4mk 0 0 0 tg2cc4pr2 tg2cc4pr1 tg2cc4pr0 fffff1c0 h tg2cc5ic tg2cc5if tg2cc5mk 0 0 0 tg2cc5pr2 tg2cc5pr1 tg2cc5pr0 fffff1c2 h cb1reic cb1reif cb1remk 0 0 0 cb1repr2 cb1repr1 cb1repr0 fffff1c4 h cb1ric cb1rif cb1rmk 0 0 0 cb1rpr2 cb1rpr1 cb1rpr0 fffff1c6 h cb1tic cb1tif cb1tmk 0 0 0 cb1tpr2 cb1tpr1 cb1tpr0 fffff1c8 h cb2reic a cb2reif cb2remk 0 0 0 cb2repr2 cb2repr1 cb2repr0 fffff1ca h cb2ric a cb2rif cb2rmk 0 0 0 cb2rpr2 cb2rpr1 cb2rpr0 fffff1cc h cb2tic a cb2tif cb2tmk 0 0 0 cb2tpr2 cb2tpr1 cb2tpr0 fffff1ce h lcdic lcdif lcdmk 0 0 0 lcdpr2 lcdpr1 lcdpr0 fffff1d0 h c2erric b c2errif c2errmk 0 0 0 c2errpr2 c2errpr1 c2errpr0 fffff1d2 h c2wupic a c2wupif c2wupmk 0 0 0 c2wuppr2 c2wuppr1 c2wuppr0 fffff1d4 h c2recic a c2recif c2recmk 0 0 0 c2recpr2 c2recpr1 c2recpr0 fffff1d6 h c2trxic a c2trxif c2trxmk 0 0 0 c2trxpr2 c2trxpr1 c2trxpr0 a) pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only b) not available on pd70f3426a table 5-11 addresses and bits of interrupt control registers (3/3) address register bit 7 6 5 4 3 2 1 0
250 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 table 5-12 addresses and bits of interrupt control registers (1/2) address register bit 7 6 5 4 3 2 1 0 fffff114 h wt0uvic wt0uvif wt0uvmk 0 0 0 wt0uvpr2 wt0uvpr1 wt0uvpr0 fffff116 h wt1uvic wt1uvif wt1uvmk 0 0 0 wt1uvpr2 wt1uvpr1 wt1uvpr0 fffff11a h tm01ic tm01if tm01mk 0 0 0 tm01pr2 tm01pr1 tm01pr0 fffff11c h p0ic p0if p0mk 0 0 0 p0pr2 p0pr1 p0pr0 fffff11e h p1ic p1if p1mk 0 0 0 p1pr2 p1pr1 p1pr0 fffff120 h p2ic p2if p2mk 0 0 0 p2pr2 p2pr1 p2pr0 fffff122 h p3ic p3if p3mk 0 0 0 p3pr2 p3pr1 p3pr0 fffff12a h tz0uvic tz0uvif tz0uvmk 0 0 0 tz0uvpr2 tz0uvpr1 tz0uvpr0 fffff12c h tz1uvic tz1uvif tz1uvmk 0 0 0 tz1uvpr2 tz1uvpr1 tz1uvpr0 fffff12e h tz2uvic tz2uvif tz2uvmk 0 0 0 tz2uvpr2 tz2uvpr1 tz2uvpr0 fffff130 h tz3uvic tz3uvif tz3uvmk 0 0 0 tz3uvpr2 tz3uvpr1 tz3uvpr0 fffff132 h tz4uvic tz4uvif tz4uvmk 0 0 0 tz4uvpr2 tz4uvpr1 tz4uvpr0 fffff134 h tz5uvic tz5uvif tz5uvmk 0 0 0 tz5uvpr2 tz5uvpr1 tz5uvpr0 fffff136 h tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff138 h tp0cc0ic tp0cc0if tp0cc0mk 0 0 0 tp0cc0pr2 tp0cc0pr1 tp0cc0pr0 fffff13a h tp0cc1ic tp0cc1if tp0cc1mk 0 0 0 tp0cc1pr2 tp0cc1pr1 tp0cc1pr0 fffff14e h tg0ov0ic tg0ov0if tg0ov0mk 0 0 0 tg0ov0pr2 tg0ov0pr1 tg0ov0pr0 fffff150 h tg0ov1ic tg0ov1if tg0ov1mk 0 0 0 tg0ov1pr2 tg0ov1pr1 tg0ov1pr0 fffff152 h tg0cc0ic tg0cc0if tg0cc0mk 0 0 0 tg0cc0pr2 tg0cc0pr1 tg0cc0pr0 fffff154 h tg0cc1ic tg0cc1if tg0cc1mk 0 0 0 tg0cc1pr2 tg0cc1pr1 tg0cc1pr0 fffff156 h tg0cc2ic tg0cc2if tg0cc2mk 0 0 0 tg0cc2pr2 tg0cc2pr1 tg0cc2pr0 fffff158 h tg0cc3ic tg0cc3if tg0cc3mk 0 0 0 tg0cc3pr2 tg0cc3pr1 tg0cc3pr0 fffff15a h tg0cc4ic tg0cc4if tg0cc4mk 0 0 0 tg0cc4pr2 tg0cc4pr1 tg0cc4pr0 fffff15c h tg0cc5ic tg0cc5if tg0cc5mk 0 0 0 tg0cc5pr2 tg0cc5pr1 tg0cc5pr0 fffff15e h tg1ov0ic tg1ov0if tg1ov0mk 0 0 0 tg1ov0pr2 tg1ov0pr1 tg1ov0pr0 fffff160 h tg1ov1ic tg1ov1if tg1ov1mk 0 0 0 tg1ov1pr2 tg1ov1pr1 tg1ov1pr0 fffff162 h tg1cc0c tg1cc0if tg1cc0mk 0 0 0 tg1cc0pr2 tg1cc0pr1 tg1cc0pr0 fffff164 h tg1cc1ic tg1cc1if tg1cc1mk 0 0 0 tg1cc1pr2 tg1cc1pr1 tg1cc1pr0 fffff166 h tg1cc2ic tg1cc2if tg1cc2mk 0 0 0 tg1cc2pr2 tg1cc2pr1 tg1cc2pr0 fffff168 h tg1cc3ic tg1cc3if tg1cc3mk 0 0 0 tg1cc3pr2 tg1cc3pr1 tg1cc3pr0 fffff16a h tg1cc4ic tg1cc4if tg1cc4mk 0 0 0 tg1cc4pr2 tg1cc4pr1 tg1cc4pr0 fffff16c h tg1cc5ic tg1cc5if tg1cc5mk 0 0 0 tg1cc5pr2 tg1cc5pr1 tg1cc5pr0 fffff172 h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff174 h c0erric c0errif c0errmk 0 0 0 c0errpr2 c0errpr1 c0errpr0 fffff176 h c0wupic c0wupif c0wupmk 0 0 0 c0wuppr2 c0wuppr1 c0wuppr0 fffff178 h c0recic c0recif c0recmk 0 0 0 c0recpr2 c0recpr1 c0recpr0 fffff17a h c0trxic c0trxif c0trxmk 0 0 0 c0trxpr2 c0trxpr1 c0trxpr0 fffff17c h cb0reic cb0reif cb0remk 0 0 0 cb0repr2 cb0repr1 cb0repr0 fffff17e h cb0ric cb0rif cb0rmk 0 0 0 cb0rpr2 cb0rpr1 cb0rpr0 fffff180 h cb0tic cb0tif cb0tmk 0 0 0 cb0tpr2 cb0tpr1 cb0tpr0
251 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 fffff182 h ua0reic ua0reif ua0remk 0 0 0 ua0repr2 ua0repr1 ua0repr0 fffff184 h ua0ric ua0rif ua0rmk 0 0 0 ua0rpr2 ua0rpr1 ua0rpr0 fffff186 h ua0tic ua0tif ua0tmk 0 0 0 ua0tpr2 ua0tpr1 ua0tpr0 fffff188 h ua1reic ua1reif ua1remk 0 0 0 ua1repr2 ua1repr1 ua1repr0 fffff18a h ua1ric ua1rif ua1rmk 0 0 0 ua1rpr2 ua1rpr1 ua1rpr0 fffff18c h ua1tic ua1tif ua1tmk 0 0 0 ua1tpr2 ua1tpr1 ua1tpr0 fffff18e h iic0ic iic0if iic0mk 0 0 0 iic0pr2 iic0pr1 iic0pr0 fffff19c h int70ic int70if int70mk 0 0 0 int70pr2 int70pr1 int70pr0 fffff19e h int71ic int71if int71mk 0 0 0 int71pr2 int71pr1 int71pr0 fffff1c2 h cb1reic cb1reif cb1remk 0 0 0 cb1repr2 cb1repr1 cb1repr0 fffff1c4 h cb1ric cb1rif cb1rmk 0 0 0 cb1rpr2 cb1rpr1 cb1rpr0 fffff1c6 h cb1tic cb1tif cb1tmk 0 0 0 cb1tpr2 cb1tpr1 cb1tpr0 table 5-12 addresses and bits of interrupt control registers (2/2) address register bit 7 6 5 4 3 2 1 0
252 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 5.3.5 imr0 to imr6 - interrupt mask registers these registers set the interrupt mask state for the maskable interrupts. the xxmk bit of the imrm (m = 0 to 6) registers is equivalent to the xxmk bit of the xxic register. caution imask bits without function, indicated with ?1?, must not be altered. make sure to set them ?1? when writing to the register. access these registers can be read/written in 16-bit and 8-bit units. the address of the lower 8-bit register imrml is equal to that of the 16-bit imrm register, and the higher 8-bit register imrmh can be accessed on the following address (address (imrm) + 1). address imr0, imr0l: ffff f100 h imr0h: ffff f101 h imr1, imr1l: ffff f102 h imr0h: ffff f101 h imr2, imr2l: ffff f104 h imr0h: ffff f101 h imr3, imr3l: ffff f106 h imr0h: ffff f101 h imr4, imr4l: ffff f108 h imr0h: ffff f101 h imr5, imr5l: ffff f10a h imr0h: ffff f101 h imr6, imr6l: ffff f10c h imr0h: ffff f101 h initial value ffff h 15 14 13 12 11 10 9 8 imr0 tz2uvmk tz1uvmk tz0uvmk p6mk p5mk p4mk p3mk p2mk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 p1mk p0mk tm01mk 1 wt1uvmk wt0uvmk vc1mk vc0mk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 imr1 tg0ov0mk tp3cc1mk tp3cc0mk tp3ovmk tp2cc1mk tp2cc0mk tp2ovmk tp1cc1mk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 tp1cc0mk tp1ovmk tp0cc1mk tp0cc0mk tp0ovmk tz5uvmk tz4uvmk tz3uvmk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 imr2 ty0uv0mk tg1cc5mk tg1cc4mk tg1cc3mk tg1cc2mk tg1cc1mk tg1cc0mk tg1ov1mk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 tg1ov0mk tg0cc5mk tg0cc4mk tg0cc3mk tg0cc2mk tg0cc1mk tg0cc0mk tg0ov1mk r/w r/w r/w r/w r/w r/w r/w r/w
253 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 for pd70f3421, pd70f3422, pd70f3423 only: 76543210 imr3 iic0mk ua1tmk ua1rmk ua1remk ua0tmk ua0rmk ua0remk cb0tmk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 cb0rmk cb0remk c0trxmk c0recmk c0wupmk c0errmk admk ty0uv1mk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 imr4 tz8uvmk tz7uvmk tz6uvmk c1trxmk c1recmk c1wupmk c1errmk p7mk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 int71mk int70mk dma3mk dma2mk dma1mk dma0mk sg0mk iic1mk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 imr5 lcdmk cb2tmk cb2rmk cb2remk cb1tmk cb1rmk cb1remk tg2cc5mk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 tg2cc4mk tg2cc3mk tg2cc2mk tg2cc1mk tg2cc0mk tg2ov1mk tg2ov0mk tz9uvmk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 imr6 11111111 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 1 1 1 1 c2trxmk c2recmk c2wupmk c2errmk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 imr4 1 1 1 c1trxmk c1recmk c1wupmk c1errmk 1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 int71mk int70mk dma3mk dma2mk dma1mk dma0mk sg0mk iic1mk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 imr5 lcdmk 1 1 1 cb1tmk cb1rmk cb1remk tg2cc5mk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 tg2cc4mk tg2cc3mk tg2cc2mk tg2cc1mk tg2cc0mk tg2ov1mk tg2ov0mk 1 r/w r/w r/w r/w r/w r/w r/w r/w
254 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 for pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only: for pd70f3421, pd70f3422, pd70f3423, pd70f3424, pd70f3425, pd70f3427 only: note xx: identification name of each peripheral unit (vc0-vc1, wt0uv-wt1uv, tm01, p0-p7, tz0uv-tz9uv, tp0ov-tp3ov, tp0cc0-tp3cc0, tp0cc1- tp3cc1, tg0ov0-tg2ov0, tg0ov1-tg2ov1, tg0cc0-tg2cc0, tg0cc1-tg2cc1, tg0cc2-tg2 cc2, tg0cc3-tg2cc3, tg0cc4- tg2cc4, tg0cc5-tg2cc5, ty0cc0 , ty0cc1, adc0err-c2err, c0wup-c2wup, c0rec-c2rec, c0trx-c2trx, cb0re-cb2re, cb0r- cb2r, cb0t-cb2t, ua0re-ua1re, ua0r-ua1r, ua0t-ua1t, iic0-iic1, sg0, dma0-dma3, int70, int71, lcd) 76543210 imr4 tz8uvmk tz7uvmk tz6uvmk c1trxmk c1recmk c1wupmk c1errmk p7mk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 int71mk int70mk dma3mk dma2mk dma1mk dma0mk sg0mk iic1mk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 imr5 lcdmk cb2tmk cb2rmk cb2remk cb1tmk cb1rmk cb1remk tg2cc5mk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 tg2cc4mk tg2cc3mk tg2cc2mk tg2cc1mk tg2cc0mk tg2ov1mk tg2ov0mk tz9uvmk r/w r/w r/w r/w r/w r/w r/w r/w 76543210 imr6 11111111 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 1 1 1 1 c2trxmk c2recmk c2wupmk c2errmk r/w r/w r/w r/w r/w r/w r/w r/w bit position bit name function 15 to 0 xxmk interrupt mask flag. 0: interrupt servicing enabled 1: interrupt servicing disabled (pending)
255 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 5.3.6 ispr - in-service priority register this register holds the priority level of the maskable interrupt currently acknowledged. when an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the interrupt request having the highest priority is automatically reset to 0 by hardware. however, it is not reset to 0 when execution is returned from non-maskable interrupt servicing or exception processing. this register is read-only in 8-bit or 1-bit units. this register can be read/written in 8-bit or 1-bit units. address ffff f19a h initial value 00 h note n = 0 to 7 (priority level) 5.3.7 maskable interrupt status flag (id) the id flag is bit 5 of the psw and this controls the maskable interrupt?s operating state, and stores control information regarding enabling or disabling of interrupt requests. initial value 0000 0020 h . the program status is initialized by any reset. 76543210 ispr7 ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 r/w r/w r/w r/w r/w r/w r/w r/w bit position bit name function 7 to 0 ispr7 to ispr0 indicates priority of interrupt currently acknowledged 0: interrupt request with priority n not acknowledged 1: interrupt request with priority n acknowledged 31 876543210 fixed to 0 np ep id sat cy ov s z r r r/w r/w r/w r/w r/w r/w r/w r/w bit position bit name function 5 id indicates whether maskable interrupt processing is enabled or disabled. 0: maskable interrupt request acknowledgement enabled 1: maskable interrupt request acknowledgement disabled (pending) this bit is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing to psw. non-maskable interrupt requests and exceptions are acknowledged regardless of this flag. when a maskable interrupt is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request generated during the acknowledgement disabled period (id = 1) is acknowledged when the pifn bit of picn register is set to 1, and the id flag is reset to 0.
256 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 5.3.8 external maskable interrupts this microcontroller provides maskable external interrupts intpn with the following features: ? analog input filter (refer to ?analog filtered inputs? on page 104 ) ? interrupt detection selectable for each interrupt input: ? rising edge ? falling edge ? both edges: rising and falling edge ? high level ?low level ? wakeup capability from stand-by mode of intpn upon ? rising edge ? falling edge ? both edges: rising and falling edge for configuration of the external interrupt events refer to ?edge and level detection configuration? on page 257 . 5.3.9 software interrupts this microcontroller provides maskable software interrupts to for processing of an interrupt service routine by the application software. for initiating a software interrupt the interrupt request flag xxic.xxif of the concerned software interrupt ?xx? must be set to 1. the following processing is identical to that of all other maskable interrupts.
257 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 5.4 edge and level detection configuration the microcontroller provides the maskable external interrupts intpn and one non-maskable interrupt (nmi). intpn can be configured to generate interrupts upon edges or levels, the nmi can be set up to react on edges. (1) intm0 to intm3 - external interrupt configuration register external interrupt function is configured by the registers intm0?intm3. access these registers can be read/written in 8-bit and 1-bit units. address intm0: ffff f700 h intm1: ffff f702 h intm2: ffff f704 h intm3: ffff f706 h initial value 00 h the register bits elseln, eseln1 and eseln0 configure the intpn interrupt function: 76543210 intm0 0 elsel1 esel11 esel10 nmien elsel0 esel01 esel00 r r/w r/w r/w r/w r/w r/w r/w 76543210 intm1 0 elsel3 esel31 esel30 0 elsel2 esel21 esel20 rr/wr/wr/wrr/wr/wr/w 76543210 intm2 0 elsel5 esel51 esel50 0 elsel4 esel41 esel40 rr/wr/wr/wrr/wr/wr/w 76543210 intm3 0 elsel7 esel71 esel70 0 elsel6 esel61 esel60 rr/wr/wr/wrr/wr/wr/w elseln eseln1 eseln0 function 0 0 0 falling edge 0 0 1 rising edge 0 1 0 prohibited to use 0 1 1 falling and rising edge 1 0 0 low level detection 1 0 1 high level detection 1 1 0 low level detection 1 1 1 high level detection
258 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 the nmi and intp0 share the same pin. the register bits nmien, esel0, esel01 and esel00 configure the nmi and intp0 interrupt function: caution the nmi configuration bits intm0.nmien and intm0.esel0[1:0] can only be changed if intm0.nmien = 0. due to intm0.nmien = 0 after reset the nmi function is disabled and must be enabled by the application software. once enabled, the nmi function cannot be disabled by software. specify intm0.esel0[1:0] before or at the same time with setting intm0.nmien = 1. note that intm0.esel0 can be written independently of intm0.nmien. nmien esel0 esel01 esel00 function nmi intp0 0 000 masked falling edge 0 0 1 rising edge 010 prohibited 0 1 1 both edges 100 low level 1 0 1 high level 110 low level 1 1 1 high level 1 0 0 0 falling edge falling edge 0 0 1 rising edge rising edge 0 1 0 prohibited prohibited 0 1 1 both edges both edges 1 0 0 falling edge low level 1 0 1 rising edge high level 1 1 0 prohibited low level 1 1 1 both edges high level
259 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 5.5 software exception a software exception is generated when the cpu executes the trap instruction, and can be always acknowledged. 5.5.1 operation if a software exception occurs, the cpu performs the following processing, and transfers control to the handler routine: (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). (4) sets the ep and id bits of the psw. (5) sets the handler address (00000040 h or 00000050 h ) corresponding to the software exception to the pc, and transfers control. figure 5-10 illustrates the processing of a software exception. figure 5-10 software exception processing note trap instruction format: trap vector (the vector is a value from 0 to 1f h .) the handler address is determined by the trap instruction?s operand (vector). if the vector is 0 to 0f h , it becomes 00000040 h , and if the vector is 10 h to 1f h , it becomes 00000050 h . trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note
260 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 5.5.2 restore recovery from software exception processing is carried out by the reti instruction. by executing the reti instruction, the cpu carries out the following processing and shifts control to the restored pc?s address. (1) loads the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. (2) transfers control to the address of the restored pc and psw. figure 5-11 illustrates the processing of the reti instruction. figure 5-11 reti instruction processing caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before the reti instruction. note the solid lines show the cpu processing flow. psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0
261 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 5.5.3 exception status flag (ep) the ep flag is bit 6 of psw, and is a status flag used to indicate that exception processing is in progress. it is set when an exception occurs. initial value 0000 0020 h . the program status is initialized by any reset. 5.6 exception trap an exception trap is an interrupt that is requested when an illegal execution of an instruction takes place. for this microcontroller, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 5.6.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 111111 b , a sub-opcode (bits 23 to 26) of 0111 b to 1111 b , and a sub-opcode (bit 16) of 0 b . an exception trap is generated when an instruction applicable to this illegal instruction is executed. note : arbitrary (1) operation if an exception trap occurs, the cpu performs the following processing, and transfers control to the handler routine: (1) saves the restored pc to dbpc. (2) saves the current psw to dbpsw. (3) sets the np, ep, and id bits of the psw. (4) sets the handler address (00000060 h ) corresponding to the exception trap to the pc, and transfers control. figure 5-12 illustrates the processing of the exception trap. 31 876543210 fixed to 0 np ep id sat cy ov s z r r r/w r/w r/w r/w r/w r/w r/w r/w bit position bit name function 6 ep shows that exception processing is in progress. 0: exception processing not in progress. 1: exception processing in progress. 31 27 26 23 22 16 15 11 10 5 4 0 0111 to 0 111111 1111
262 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 figure 5-12 exception trap processing (2) restore recovery from an exception trap is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. (1) loads the restored pc and psw from dbpc and dbpsw. (2) transfers control to the address indicated by the restored pc and psw. figure 5-13 illustrates the restore processing from an exception trap. figure 5-13 restore processing from exception trap exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing dbret instruction pc psw dbpc dbpsw jump to address of restored pc
263 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 5.6.2 debug trap the debug trap is an exception that can be acknowledged every time and is generated by execution of the dbtrap instruction. when the debug trap is generated, the cpu performs the following processing. (1) operation when the debug trap is generated, the cpu performs the following processing, transfers control to the debug monitor routine, and shifts to debug mode. (1) saves the restored pc to dbpc. (2) saves the current psw to dbpsw. (3) sets the np, ep and id bits of the psw. (4) sets the handler address (00000060 h ) corresponding to the debug trap to the pc and transfers control. figure 5-14 illustrates the processing of the debug trap. figure 5-14 debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing
264 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 (2) restore recovery from a debug trap is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. (1) loads the restored pc and psw from dbpc and dbpsw. (2) transfers control to the address indicated by the restored pc and psw. figure 5-15 illustrates the restore processing from a debug trap. figure 5-15 restore processing from debug trap 5.7 multiple interrupt processing control multiple interrupt processing control is a process by which an interrupt request that is currently being processed can be interrupted during processing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is received and processed first. if there is an interrupt request with a lower priority level than the interrupt request currently being processed, that interrupt request is held pending. maskable interrupt multiple processing control is executed when an interrupt has an enable status (id = 0). thus, if multiple interrupts are executed, it is necessary to have an interrupt enable status (id = 0) even for an interrupt processing routine. if a maskable interrupt enable or a software exception is generated in a maskable interrupt or software exception service program, it is necessary to save eipc and eipsw. this is accomplished by the following procedure. dbret instruction pc psw dbpc dbpsw jump to address of restored pc
265 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 (1) acknowledgment of maskable interrupts in service program service program of maskable interrupt or exception (2) generation of exception in service program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (interrupt acknowledgment enabled) ... ... higher priority maskable interrupt acknowledgment ... ... ? di instruction (interrupt acknowledgment disabled) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ... ? trap instruction ... trap/exception acknowledgment ... ... ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction
266 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00 the priority order for multiple interrupt processing control has 8 levels, from 0 to 7 for each maskable interrupt request (0 is the highest priority), but it can be set as desired via software. setting of the priority order level is done using the pprn0 to pprn2 bits of the interrupt control request register (plcn), which is provided for each maskable interrupt request. after system reset, an interrupt request is masked by the pmkn bit and the priority order is set to level 7 by the pprn0 to pprn2 bits. the priority order of maskable interrupts is as follows. (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt processing that has been suspended as a result of multiple processing control is resumed after the processing of the higher priority interrupt has been completed and the reti instruction has been executed. a pending interrupt request is acknowledged after the current interrupt processing has been completed and the reti instruction has been executed. caution in a non-maskable interrupt processing routine (time until the reti instruction is executed), maskable interrupts are suspended and not acknowledged. 5.8 interrupt response time the following table describes the interrupt response time (from interrupt generation to start of interrupt processing). except in the following cases, the interrupt response time is a minimum of 5 clocks. ? during software or hardware stop mode ? when an external bus is accessed ? when there are two or more successive interrupt request non-sampling instructions (see ?periods in which interrupts are not acknowledged? on page 267 ). ? when the interrupt control register is accessed
267 interrupt controller (intc) chapter 5 user?s manual u17566ee5v1um00 figure 5-16 pipeline operation at interrupt request acknowledgment (outline) note int1 to int4: interrupt acknowledgement processing ifx: invalid instruction fetch idx: invalid instruction decode note if the same interrupt occures during the interrupt acknowledge time of 5 cycles, this new interrupt will discarded. the next interrupt of the same source will only be registered after these 5 cycles. 5.9 periods in which interrupts are not acknowledged an interrupt is acknowledged while an instruction is being executed. however, no interrupt will be acknowledged between an interrupt non-sample instruction and the next instruction. the interrupt request non-sampling instructions are as follows: ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the store instruction for the maskable interrupt control registers (xxic), in- service priority register (ispr), and command register (prcmd). table 5-13 interrupt response time interrupt response time (internal system clocks) condition internal interrupt external interrupt minimum 5 5 + analog delay time the following cases are exceptions: ? in idle/software stop mode ? external bit access ? two or more interrupt request non- sample instructions are executed ? access to interrupt control register maximum 11 11 + analog delay time if id ex vbclk (input) instruction 1 instruction 2 interrupt acknowledgement operation instruction (first instruction of interrupt service routine) interrupt request if id ex mem wb ifx idx int1 int2 int3 int4 5 system clocks
268 chapter 5 interrupt controller (intc) user?s manual u17566ee5v1um00
269 user?s manual u17566ee5v1um00 chapter 6 flash memory the pd70f3421, pd70f3422, pd70f3423, pd70f3424, pd70f3425, pd70f3426a and pd70f3427 microcontrollers are equipped with internal flash memory. the flash memory is attached to the v850 fetch bus (vfb) interface of the v850e cpu core, or in case of more than 1 mb flash memory for the pd70f3426a additionally to the v850 system bus (vsb). it is used for program code and storage of constant data. when fetching an instruction, 4 bytes of the vfb flash memory can be accessed in 1 clock, and 4 bytes of the vsb flash memory can be accessed in 2 clocks. the flash memory can be written mounted on the target board (on-board write), by connecting a dedicated flash programmer to the target system. flash memory is commonly used in the following development environments and applications: ? for altering software after solder-mounting of the microcontroller on the target system. ? for differentiating software in small-scale production of various models. ? for data adjustment when starting mass production.
270 chapter 6 flash memory user?s manual u17566ee5v1um00 6.1 overview features summary ? internal vfb flash memory: ? pd70f3427, pd70f3426a, pd70f3425: 1 mb ? pd70f3424, pd70f3423: 512 kb ? pd70f3422: 384 kb ? pd70f3421: 256 kb ? internal vsb flash memory: ? pd70f3426a: 1 mb ? pd70f3427, pd70f3425, pd70f3424 operation speed: up to 67.2 mhz by 2-way interleaved access ? 4-byte/1 cpu clock cycle access for consecutive instruction fetches ? 4-byte/4 cpu clock cycles access for random instruction and data fetches ? pd70f3426a operation speed : up to 67.2 mhz by 2-way interleaved access internal vfb flash memory: ? 4-byte/1 cpu clock cycle access for consecutive instruction fetches ? 4-byte/4 cpu clock cycles access for random instruction and data fetches internal vsb flash memory: ? 4-byte/2 cpu clock cycle access for consecutive instruction fetches ? 4-byte/5 cpu clock cycles access for random instruction and data fetches ? pd70f3423, pd70f3422, pd70f3421 operation speed: up to 25.2 mhz by 2-way interleaved access ? 4-byte/1 cpu clock cycle access for consecutive instruction fetches ? 4-byte/3 cpu clock cycles access for random instruction and data fetches ? all-blocks batch erase or single block erase ? erase/write with single power supply ? communication with dedicated flash programmer via various serial interfaces ? on-board and off-board programming ? flash memory programming by self-programming
271 flash memory chapter 6 user?s manual u17566ee5v1um00 6.1.1 flash memory address assignment the 1 mb vfb flash memory of pd70f3427, pd70f3426a, and pd70f3425 is made up of 256 blocks. figure 6-1 shows the address assignment of the flash memory blocks. figure 6-1 address assignment of pd70f3427, pd70f3426a, and pd70f3425 flash memory blocks 0010 0000 h 000f f000 h 000f e000 h 0000 2000 h 0000 1000 h 0000 0000 h block 0 (4 kb) block 1 (4 kb) block 254 (4 kb) block 255 (4 kb)
272 chapter 6 flash memory user?s manual u17566ee5v1um00 the 512 kb flash memory of pd70f3424, and pd70f3423 is made up of 128 blocks. figure 6-2 shows the address assignment of the flash memory blocks. figure 6-2 address assignment of pd70f3424, and pd70f3423 flash memory blocks the 384 kb flash memory of pd70f3422 is made up of 96 blocks. figure 6-3 shows the address assignment of the flash memory blocks. figure 6-3 address assignment of pd70f3422 flash memory blocks 0008 0000 h 0007 f000 h 0007 e000 h 0000 2000 h 0000 1000 h 0000 0000 h block 0 (4 kb) block 1 (4 kb) block 126 (4 kb) block 127 (4 kb) 0006 0000 h 0005 f000 h 0005 e000 h 0000 2000 h 0000 1000 h 0000 0000 h block 0 (4 kb) block 1 (4 kb) block 94 (4 kb) block 95 (4 kb)
273 flash memory chapter 6 user?s manual u17566ee5v1um00 the 256 kb flash memory of pd70f3421 is made up of 64 blocks. figure 6-4 shows the address assignment of the flash memory blocks. figure 6-4 address assignment of pd70f3421 flash memory blocks 6.1.2 flash memory erasure and rewrite the following functions can be carried out by use of the flash memory self- programming library. (1) flash memory erasure according to it?s block structure the flash memory can be erased in two different modes. ? all-blocks batch erasure following areas can be erased all together: ? pd70f3427, pd70f3426a, pd70f3425: 0000 0000 h to 000f ffff h ? pd70f3424, pd70f3423: 0000 0000 h to 0007 ffff h ? pd70f3422: 0000 0000 h to 0005 ffff h ? pd70f3421: 0000 0000 h to 0003 ffff h ? block erasure each 4 kb flash memory block can be erased separately. (2) flash memory rewrite once a complete block has been erased it can be rewritten in units of 8 byte. each unit can be rewritten only once after erasure of the complete block. 0004 0000 h 0003 f000 h 0003 e000 h 0000 2000 h 0000 1000 h 0000 0000 h block 0 (4 kb) block 1 (4 kb) block 62 (4 kb) block 63 (4 kb)
274 chapter 6 flash memory user?s manual u17566ee5v1um00 6.1.3 flash memory programming the internal flash memory can be programmed in three different ways: ? programming via self-programming ? programming via n-wire interface ? programming with external flash programmer while the self-programming mode can be initiated from the normal operation mode the external flash programmer mode is entered immediately after release of a system reset. refer to ?operation modes? on page 125 for details on how to enter normal operation or external flash programming mode. 6.1.4 boot block swapping the microcontrollers with flash memory support secure boot block swapping. this will swap two 32 kb blocks at the bottom end (starting from address 0000 0000 h ) of the flash memory. the block size is fixed and can not be changed. for comprehensive information concerning secure boot block swapping refer to the application note ?self-programming? (document nr. u16929ee), which explains also the functions of the self-programming library. the latest version of this document can be loaded via the url http://www.eu.necel.com/updates
275 flash memory chapter 6 user?s manual u17566ee5v1um00 6.2 flash self-programming the internal flash memory can be programmed via the secure self-program- ming facility. this feature enables the user?s application to re-program the flash memory. the self-programming functions are part of the internal firmware, which resides in an extra internal rom. the user?s application can call the self- programming functions via the self-programming library, provided by nec. caution during self-programming make sure to disable all rom correction facilities, as enabled rom corrections may conflict with the internal firmware. start of self- programming the self-programming functions can be started out of the normal user mode of the microcontroller. self-programming must be in particular enabled in order to avoid unintended re-programming of the flash. two ways to enable self-programming are provided: ? by setting the external flmd0 pin to high level this requires some external components or wiring, e.g. connecting an output port to flmd0. ? by setting an internal register bit this way does not need any special external components or wiring. the following registers are used to enable self-programming internally by software. 6.2.1 flash self-programming registers for safety reasons flash self-programming needs to be explicitly enabled by use of two registers: table 6-1 flash self-programming enable register overview register name shortcut address self-programming enable control register selfen ffff fca0 h self-programming enable protection register selfenp ffff fca8 h
276 chapter 6 flash memory user?s manual u17566ee5v1um00 (1) selfen - self-programming enable control register the 8-bit selfen register enables the self-programming functions by software. it is an internal substitute to enabling self-programming by rising the flmd0 pin to high level. access this registers can be read/written in 8-bit or 1-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?selfenp - self-programming enable protection register? on page 276 for details. address ffff fca0 h initial value 00 h . this register is cleared by any reset. (2) selfenp - self-programming enable protection register the 8-bit selfenp register protects the register selfen from inadvertent write access, so that the system does not stop in case of a program hang-up. after data has been written to the selfenp register, the first write access to register selfen is valid. all subsequent write accesses are ignored. thus, the value of selfen can only be rewritten in a specified sequence, and illegal write access is inhibited. access this registers can be written in 8-bit units. address ffff fca8 h initial value the contents of this register is undefined. caution in case a high level programming language is used, make sure that the compiler translates the two write instructions to selfenp and selfen into two consecutive assembler ?store? instructions. peripherals and pin functions all peripheral functions of the microcontroller continue operation during the self-programming process. further the functions of all pins do not change. 76543210 0000000flen rrrrrrrr/w bit position bit name function 0 flen enable self-programming 0: flash write/erase function is controlled by the flmd0 pin 1: flash write/erase function is enabled 76543210 xxxxxxxx wwwwwwww
277 flash memory chapter 6 user?s manual u17566ee5v1um00 6.2.2 interrupt handling dur ing flash self-programming this microcontroller provides functions to maintain interrupt servicing during the self-programming procedure. it is recommended to refer to the application note ?self-programming? (document nr. u16929ee) for comprehensive information concerning flash self-programming, which explains also the functions of the self-programming library. the latest version of this document can be loaded via the url http://www.ee.nec.de/updates since neither the interrupt vector table nor the interrupt handler routines, which are normally located in the flash memory, are accessible during self- programming, interrupt acknowledges have to be re-routed to non-flash memory, i.e. to the internal ram or - for pd70f3427 only - to the external memory. therefore two prerequisites are necessary to enable interrupt servicing during self-programming: ? the concerned interrupt handler routine needs to be copied to the internal ram, respectively external memory. ? the concerned interrupt acknowledge has to be re-routed to that handler. the internal firmware and the self-programming library provide functions to initialize and process such interrupts. the interrupt handler routines can be copied from flash to the internal ram, respectively external memory, by use of the selflib_usrinttoram self- programming library function. the addresses of the interrupt handler routines are set up via the selflib_registerint self-programming library function. note 1. note that this special interrupt handling adds some interrupt latency time. 2. special interrupt handling is done only during the flash programming environment is activated. if self-programming is deactivated, the normal interrupt vector table in the flash memory is used. all interrupt vectors are relocated to one entry point in the internal ram: ? new entry point of all maskable interrupts is the 1st address of the internal ram. a handler routine must check the interrupt source. the interrupt request source can be identified via the interrupt/exception source register ecr.eicc (refer to ?system register set? on page 118 ) ? new entry point of all non maskable interrupts is the word address following the maskable interrupt entry, i.e. the second address of the internal ram. the interrupt request source can be identified via the interrupt/exception source register ecr.fecc (refer to ?system register set? on page 118 ). in general a jump to a special handler routine will be placed at the 1st and 2nd internal ram address, which identifies the interrupt sources and branches to the correct interrupt service routine. the function serving the interrupt needs to be compiled as an interrupt function (i.e. terminate with a reti instruction, save/restore all used registers, etc.).
278 chapter 6 flash memory user?s manual u17566ee5v1um00 6.3 flash programming via n-wire the microcontroller?s flash memory is programmable via the n-wire debug interface. programming of the flash memory can be performed by the debug tool running on the host machine. caution programming the flash memory during debug sessions by the debug tool adds to the performed number of write/erase cycles of the flash memory. thus devices used for debugging shall not be used for mass production purposes afterwards.
279 flash memory chapter 6 user?s manual u17566ee5v1um00 6.4 flash programming with flash programmer a dedicated flash programmer can be used for on-board or off-board writing of the flash memory. (1) on-board programming the contents of the flash memory can be rewritten with the microcontroller mounted on the target system. mount a connector that connects the flash programmer on the target system. a csi or a uart interface can optionally be used for the communication between the external flash programmer and the v850 microcontroller. all signals, including clock and power supply, can be provided by the external flash programmer. however, an on-board clock to the x1 input may be used instead of the clock, provided by the flash programmer. (2) off-board programming the flash memory of the microcontroller can be written before the device is mounted on the target system, by using a dedicated program adapter (fa series). all signals, including clock and power supply, are provided by the external flash programmer. note the fa series is a product of naito densei machida mfg. co., ltd. 6.4.1 programming environment the necessary environment to write a program to the flash memory of the microcontroller is shown below. figure 6-5 environment to write program to flash memory a host machine is required for controlling the flash programmer. following microcontroller serial interfaces can be used as the interface between the flash programmer and the microcontroller: ? asynchronous serial interface uart ? clocked serial interface csib note: flmd1 connection may be replaced by a pull-down resistor on the board ho s t m a chine r s -2 3 2-c u s b fl as h progr a mmer flmd0 (flmd1 note ) v ss v dd re s et uart/c s ib pg-fp4 (f l a s h pro 4 ) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y s tat v e v 8 50 microcontroller h s
280 chapter 6 flash memory user?s manual u17566ee5v1um00 if the csib interface is used with handshake, the flash programmer?s hs signal is connected to a certain v850 port. the port used as the handshake port is given in ta b l e 6 - 2 . flash memory programming off-board requires a dedicated program adapter. uarta0 or csib0 is used as the interface between the flash programmer and the microcontroller. flash memory programming off-board requires a dedicated program adapter (fa series). 6.4.2 communication mode the communication between the flash programmer and the microcontroller utilizes the asynchronous serial interface uarta0 or the synchronous serial interface csib0. for programming via the synchronous serial interface csib0 without handshake and with handshake modes are supported. in the latter mode the port pin p84 is used for the programmer?s handshake signal hs. (1) uarta0 transfer rate: 4.800 to 153.600 bps figure 6-6 communication with flash programmer via uarta0 flash programmer v dd v ss reset txda0 rxda0 flmd0 (flmd1 note ) flmd0 (flmd1 note ) v dd gnd reset rxd txd pg-fp4 ( f las h p r o 4) cxxxxxx bxxxxx axxxx xxx y y y x x xx x x x xx x x x x x x xx xx y y y y statve v850 microcontroller note: flmd1 connection may be replaced by a pull-down resistor on the board
281 flash memory chapter 6 user?s manual u17566ee5v1um00 (2) csib0 without handshake serial clock: up to 2.5 mhz (msb first) figure 6-7 communication with flash programmer via csib0 without handshake (3) csib0 with handshake (csib0 + hs) serial clock: up to 2.5 mhz (msb first) figure 6-8 communication with flash programmer via csib0 with handshake the flash programmer outputs a transfer clock and the microcontroller operates as a slave. if the pg-fp4 is used as the flash programmer, it generates the following signals for the microcontroller. for details, refer to the pg-fp4 user?s manual (u15260e). flash programmer flmd0 (flmd1 note ) v dd v ss reset sob0 sib0 sckb0 flmd0 (flmd1 note ) v dd gnd reset si so sck pg-fp4 (f la sh pro 4) cxxxxxx bxxxxx axxxx x x x y y y x xx xx xx xxx x xx x x x xx x y yy y statve v850 microcontroller note: flmd1 connection may be replaced by a pull-down resistor on the board flash programmer v dd v ss reset sob0 sib0 sckb0 p84 v dd flmd0 (flmd1 note ) flmd0 (flmd1 note ) gnd reset si so sck hs pg-fp4 ( f lash p ro4 ) cxxxxxx bxxxxx axxxx x xx y yy xx xx x xx xx x x x xx x x x x x y y y y statve v850 microcontroller note: flmd1 connection may be replaced by a pull-down resistor on the board
282 chapter 6 flash memory user?s manual u17566ee5v1um00 note ? ??? ??? ??? ??? ??? ??? ?? ?
283 flash memory chapter 6 user?s manual u17566ee5v1um00 6.4.3 pin connection a connector must be mounted on the target system to connect the flash programmer for on-board writing. in addition, a function to switch between the normal operation mode and flash memory programming mode must be provided on the board. when the flash memory programming mode is set, all the pins not used for flash memory programming are in the same status as immediately after reset. (1) connection to flash programmer in the normal operation mode, 0 v is input to the flmd0 pin. the pull-down resistor at the flmd0 pin ensures normal operation mode if no flash programmer is connected. in the flash memory programming mode, the v dd write voltage is supplied to the flmd0 pin. additionally the flmd1 pin, shared with port p07, has to hold 0 v level. an example of connection of the flmd0 and flmd1 pins is shown below. alternatively the flmd1 pin may also be connected directly to the flmd1 signal of the flash programmer. figure 6-9 example of connection to flash programmer pg-fp4 in csi and uart mode table 6-3 operation mode settings pins operation mode flmd0 flmd1 (p07) 0 x normal operation mode (fetch from flash) 1 0 flash programming mode 1 setting prohibited pd70f34xx pg-fp4 flmd0 flmd1 flmd0 flmd1 pd70f34xx pg-fp4 flmd0 flmd1 flmd0 flmd1
284 chapter 6 flash memory user?s manual u17566ee5v1um00 (2) serial interface pins the pins used by each serial interface are shown in the table below. in flash programming mode the output drive strength control of the pins txda0, sob0 and p84 is disabled. by this means the port pins provide maximum driver capability in order to maximize the transmission data rate to the flash programmer. caution 1. since the output drive strength control of the pins txda0, sob0 and p84 is disabled during programming these pins are not short-circuit proof any more. short circuits at these pins may permanently damage the device. 2. if other devices are connected to the serial interface pins in use for flash memory programming in on-board programming mode take care that the concerned signals do not conflict with the signals of the flash programmer and the microcontroller. output pins of the other devices must be isolated or set in high impedance state. ensure that the other devices do not malfunction because of flash programmer signals. 3. pay attention in particular if the flash programmer?s reset signal is connected also to an on-board reset generation circuit. the reset output of the reset generator may ruin the flash programming process and may need to be isolated. 4. all the port pins, including the pin connected to the flash programmer, go into an output high-impedance state in the flash memory programming mode. if there is a problem such as that an external device connected to a port prohibits the output high-impedance state, connect the port to v dd or v ss via a resistor. 5. connect all oscillator pins in the same way as in the normal operation mode. 6. supply the same power to all power supply pins, including reference voltages, power regulator pins, etc., as in the normal operation mode. table 6-4 pins used by each serial interface serial interface pins uarta0 txda0, rxda0 at pins p30/p31 csib0 sob0, sib0, sckb0 at pins p40 - p42 csib0 + hs sob0, sib0, sckb0, p84
285 flash memory chapter 6 user?s manual u17566ee5v1um00 6.4.4 programming method in the following the flash programming flow is described, if the csi or the uart is used as the communication interface. (1) flash memory control the procedure to manipulate the flash memory is illustrated below. figure 6-10 flash memory manipulation procedure (2) flash memory programming mode to rewrite the contents of the flash memory by using the flash programmer, set the microcontroller in the flash memory programming mode. to set this mode, set the flmd0 and flmd1 pins as shown in ta b l e 6 - 6 and release reset . the communication interface is chosen by applying a specified number of pulses to the mode pin after reset release. note that this is handled by the flash programmer. figure 6-11 gives an example how the uarta0 is established for the communication between the flash programmer and the microcontroller.
286 chapter 6 flash memory user?s manual u17566ee5v1um00 figure 6-11 flash memory programming mode start-up note the number of clocks to be inserted differs depending on the chosen communication mode. for details, refer to ta bl e 6 - 5 . (3) selecting communication mode the communication mode is selected by applying a specified number of pulses to the mode pin after the flash memory programming mode is set. these mode pulses are generated by the flash programmer. the relationship between the number of pulses and the communication mode is shown in the table below. note when uarta0 is selected, the receive clock is calculated based on the reset command that is sent from the flash programmer after reception of the mode pulses. v dd flmd1 (inp u t) flmd0 (inp u t) rxda0 (inp u t) txda0 (o u tp u t) 0 v 0 v 0 v 0 v 0 v 0 v re s et (inp u t) flash control command communication (such as erase and write) communication mode selection oscillation stabilization reset release power supply on (note) v dd v dd v dd v dd v dd v dd table 6-5 communication modes mode pulses communication mode remark 0 uarta0 communication rate: 9,600 bps (after reset), lsb first 8 csib0 microcontroller operates as slave, msb first 11 csib0 + hs microcontroller operates as slave, msb first others - setting prohibited
287 flash memory chapter 6 user?s manual u17566ee5v1um00 (4) communication commands the microcontroller communicates with the flash programmer via commands. the commands sent to the microcontroller are called commands, and the response signals sent by the microcontroller to the flash programmer are called response commands. figure 6-12 communication commands the following table lists the flash memory control commands of the microcontroller. all these commands are issued by the flash programmer, and the microcontroller performs the corresponding processing. flash programmer command response command pg-fp4 (f la sh p r o4 ) cxxxxxx bxxxxx axxxx x xx y y y x x x x x x x x x x x xx x x xxx x y yyy statve v850 microcontroller table 6-6 flash memory control commands classification command name support function csib csib + hs uarta blank check block blank check command checks erasure status of entire memory. erase chip erase command erase all memory contents including area that holds security flags, reset vector and other flash options block erase command erases memory contents of specified block. write write command writes data by specifying write address and number of bytes to be written, and executes verify check. verify verify command compares input data with all memory contents. read read command read flash memory contents system setting and control reset command escapes from each status. oscillation frequency setting command sets oscillation frequency. baud rate setting command sets baud rate when uart is used. silicon signature command reads silicon signature information. version acquisition command reads version information of device. status command acquires operation status. security setting command sets security of chip erasure, block erasure, and writing.
288 chapter 6 flash memory user?s manual u17566ee5v1um00 the microcontroller returns a response command to the command issued by the flash programmer. the response commands sent by the microcontroller are listed below. table 6-7 response commands response command name function ack acknowledges command/data. nak acknowledges illegal command/data.
289 user?s manual u17566ee5v1um00 chapter 7 bus and memory control (bcu, memc) besides providing access to on-chip peripheral i/os, the pd70f3427 microcontroller device supports access to external memory devices (such as external rom and ram) and external i/o. the bus control unit bcu and memory controller memc control the access to on-chip peripheral i/os and to external devices. since the bcu controls access to the on-chip peripherals, the registers bpc and vswc have to be set up correctly for all devices. note throughout this chapter, the individual chip select areas are identified by ?k? (k = 0 to 7), for example csk for the chip select signal k or bec.bek0 for setting the endian format of chip select area k. 7.1 overview the following external devices can be connected to the microcontroller device: ? sram / ram ?rom ? external i/o features summary the bus and memory control of the microcontroller device provides: ? 24 address signals (a0 to a23) ? selectable data bus width for each chip select area (8 bits, 16 bits and 32 bits) ? 4 chip select signals externally available (cs0 , cs1 , cs3 and cs4 ) ? access to memory takes a minimum of two cpu clock cycles ? up to 3 address setup wait states can be inserted for each chip select area ? up to 7 data wait states can be inserted for each chip select area (programmable wait) ? external data wait function through wait pin ? up to 3 idle states can be inserted for each chip select area ? up to 2 write strobe delay cycles can be inserted ? direct memory access (dma) support ? external bus mute function
290 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 ? page rom controller ? direct connection to 8-bit/16-bit/32-bit page rom supported ? page rom controller handles page widths from 8 to 128 bytes ? on-page judgement function ? masking addresses can be changed by register setting ? register for controlling the programmable wait during page access ? supported page access depends on data bus width: 7.2 description the figure below shows a block diagram of the modules that are necessary for accessing on-chip peripherals, external memory, or external i/o. figure 7-1 block diagram of bus and memory controller busses the busses are abbreviated as follows: ? npb: nec peripheral bus data bus width supported page access 32 bit 2/4/8/16/32 x 32 bits 16 bit 4/8/16/32/64 x 16 bits 8 bit 8/16/32/64/128 x 8 bits internal bus (npb) bus control unit (bcu) cpu dma controller bus bridge (bbr) vsb vdb vfb on-chip peripheral i/o vsb flash pd70f3426a only memory controller (memc) a[23:0] d[31:0] bclk external device pd70f3427 only wait cs0 cs1 cs3 cs4 be0 be1 be2 be3 rd wr vsb ram pd70f3426a only
291 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 ? vsb: v850 system bus ? vdb: v850 data bus ? vfb: v850 fetch bus bcu the bus control unit (bcu) controls the access to on-chip peripherals, to external memory controller (memc), the vsb ram and vsb flash of the pd70f3426a device. for access to external devices, the bcu generates the necessary control signals (chip select signals) for the memory controller. memory controller the 64 mb address range is divided into 2-mb, 4-mb and 8-mb memory banks. each of the memory banks can be assigned to an external device via the chip area select control registers csc0 and csc1. if an instruction uses such an address, a chip select signal is generated. the device supports four chip select signals (cs0 , cs1 , cs3 and cs4 ). each chip select signal covers a certain address range, also called ?chip select area?. for details see ?memory banks and chip select signals? on page 292 . additional byte enable signals be0 to be3 indicate valid data on any of the four bytes of the 32-bit data bus d[31:0]. the memory controller generates the control signals for access to the external devices. for example, it generates the read strobe (rd ) and the write strobe (wr ). from the 26 bit address of the cpu, the lower 24 bits are passed to the external device. if two chip select signals are specified in the cscn registers for a single memory bank, the priority control selects one of the chip select signals. the priority order is given in ?cscn - chip area select control registers? on page 305 . the external signals of the memory controller and their state during and after reset are listed in the following table: all port pins are in input port mode after reset. refer to ?pin functions? on page 27 . table 7-1 memory controller external connections and reset states signal name i/o state during reset state after reset function a[23:0] o hi-z (3-state) o address bus d[31:16] i/o hi-z (3-state) port input data bus d[15:0] hi-z (3-state) i cs0 o hi-z (3-state) o chip select signal cs1 cs3 cs4 be0 o hi-z (3-state) o byte enable signal be1 be2 o hi-z (3-state) port input be3 rd o hi-z (3-state) o read strobe wr o hi-z (3-state) o write strobe bclk o hi-z (3-state) port input bus clock
292 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 romc to access external rom with page access function (page rom), the page rom controller (romc) is provided. it can handle page widths from 8 to 128 bytes. for more details, see ?page rom controller? on page 320 . note if the concerned pins are configured as external memory bus pins change between input and output is performed automatically by memory controller?s read and write operations. configuration the microcontroller device supports interfacing with various memory devices. to make the bus and memory controller suitable for the connected device, the endian format, wait functions and idle state insertions can be configured. for a detailed description, see ?configuration of memory access? on page 322 . 7.2.1 memory banks and chip select signals the 64 mb address range is divided into memory banks. each memory bank is assigned to one or more chip select (csn ) signals. if a memory bank is configured for external access, access to that memory bank generates the corresponding chip select signal (see figure 7-3 on page 294 ). the combination of memory banks that activate the same chip select signal is called chip select area. pd70f3426a figure 7-2 shows the memory map of the pd70f3426a. the 1 mb vsb flash memory is mapped to the address range 0010 0000 h to 001f ffff h within bank 0. cs0 is assigned to the vsb flash memory. the 24 kb vsb ram memory is mapped to the address range 0060 0000 h to 0060 5fff h within bank 3. cs2 is assigned to the vsb ram memory. for access to the vsb flash and vsb ram the concerned bcu registers have to be set up as shown in figure 7-2 for details about the control settings refer to the description of the registers. table 7-2 bcu register settings for pd70f3426a vsb flash and vsb ram access control bit required setting comment csc0.cs0[3:0] 0001 b ? bank 0 assigned to cs0 for vsb flash ? default, don?t change csc0.cs2[3:0] 1000 b ? bank 3 assigned to cs2 for vsb ram ? no default, must be changed bec.be00 0 ? little endian for vsb flash ? default, don?t change bec.be20 0 ? little endian for vsb ram ? default, don?t change
293 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 figure 7-2 memory banks and chip select signals for pd70f3426a bank 0 (2 mb) vfb flash (1 mb) bank 1 (2 mb) bank 2 (2 mb) bank 3 (2 mb) bank 7 (8 mb) bank 6 (8 mb) bank 5 (4 mb) bank 4 (4 mb) bank 15 (2 mb) peripheral i/o area (4 kb) reserved vdb ram (60 kb) programmable peripheral i/o area (ppa) (16 kb) note bank 14 (2 mb) bank 13 (2 mb) bank 12 (2 mb) bank 8 (8 mb) bank 9 (8 mb) bank 10 (4 mb) bank 11 (4 mb) 0000 0000h 0020 0000h 0000 0000h 000f ffffh 0010 0000h 001f ffffh 0040 0000h 0060 0000h 0060 5fffh 0060 0000h 0080 0000h 00c0 0000h 0100 0000h 0180 0000h 0200 0000h 0280 0000h 0300 0000h 0340 0000h 0380 0000h 03a0 0000h 03c0 0000h 03e0 0000h 03ff ffffh 03ff ffffh 03ff f000h 03ff 0000h 03fe c000h 03e0 0000h cs1 cs0 cs2 cs6 cs7 cs5 cs3 cs4 note: the shown address range of the ppa assumes the bpc register to be set to 8ffbh. vsb flash cs0 ( 1 mb) vsb ram cs2 ( 24 kb)
294 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 figure 7-3 memory banks and chip select signals for pd70f3427 bank 0 (2 mb) vfb flash (1 mb) bank 1 (2 mb) bank 2 (2 mb) bank 3 (2 mb) bank 7 (8 mb) bank 6 (8 mb) bank 5 (4 mb) bank 4 (4 mb) bank 15 (2 mb) peripheral i/o area (4 kb) reserved vdb ram (60 kb) programmable peripheral i/o area (ppa) (16 kb) note bank 14 (2 mb) bank 13 (2 mb) bank 12 (2 mb) bank 8 (8 mb) bank 9 (8 mb) bank 10 (4 mb) bank 11 (4 mb) 0000 0000h 0020 0000h 0000 0000h 000f ffffh 0040 0000h 0040 0000h 0060 0000h 0080 0000h 0080 0000h 007f ffffh 00c0 0000h 0100 0000h 0100 0000h 00ff ffffh 0180 0000h 0200 0000h 0200 0000h 01ff ffffh 0280 0000h 0300 0000h 0300 0000h 02ff ffffh 0340 0000h 0380 0000h 0380 0000h 037f ffffh 03a0 0000h 03c0 0000h 03e0 0000h 03ff ffffh 03ff ffffh 03ff f000h 03ff 0000h 03fe c000h 03e0 0000h 03df ffffh cs1 cs0 cs2 cs6 cs7 cs5 cs3 cs4 external memory area cs4 bank 10, 11 external memory area cs4 bank 12 to 14 note: the shown address range of the ppa assumes the bpc register to be set to 8ffbh. external memory area cs4 bank 8, 9 external memory area cs3 bank 6, 7 external memory area cs1, cs3 bank 4, 5 external memory area cs0, cs1, cs3 bank 2, 3
295 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 7.2.2 chips select priority control the chip select signals cs0 to cs7 can be assigned to overlapping memory areas by setting the chip select area control registers csc0 and csc1. the chip select priority control rules the generation of chip select signals in this case. access to internal resources, which are concurrently mapped to an external memory areas overrules the external access. as a consequence, the assigned csn signal is not generated externally. if different chip select signals are set (csc0.csckm = 1) for the same memory bank, the priority order is as follows: ? internal resources > cs0 > cs2 > cs1 > cs3 ? internal resources > cs7 > cs5 > cs6 > cs4 examples: ? if both chip select signal cs0 and cs1 are set for memory bank 2, only the chip select signal cs0 will be generated. ? if during access to bank 2 cs2 should not be active, activate cs0 for this bank (csc0.cs02 = 1). due to the priority order, only chip select signal cs0 will be active for bank 2. 7.2.3 peripheral i/o area two areas of the address range are reserved for the registers of the on-chip peripheral functions. these areas are called ?peripheral i/o areas?: (1) fixed peripheral i/o area the fixed peripheral i/o area holds the registers of the on-chip peripheral i/o functions. note because the address space covers 64 mb, the address bits a[31:26] are not considered. therefore, in this manual, all addresses of peripheral i/o registers in the 4 kb peripheral i/o area are given in the range ffff f000 h to ffff ffff h instead of 03ff f000 h to 03ff ffff h . table 7-3 peripheral i/o areas name address range size fixed peripheral i/o area 03ff f000 h to 03ff ffff h 4 kb programmable peripheral i/o area (ppa) can be allocated at arbitrary addresses. base address is defined in the bpc register. 16 kb
296 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 (2) programmable peripheral i/o area (ppa) the usage and the address range of the ppa is configurable. the ppa extends the fixed peripheral i/o area and assigns an additional 12 kb address space for accessing on-chip peripherals. the figure below illustrates the programmable peripheral i/o area (ppa). figure 7-4 programmable peripheral i/o area the can modules registers and message buffers are allocated to the ppa. refer to ?can module register and message buffer addresses? on page 745 for information how the calculate the register and message buffer addresses of the can modules. caution if the programmable peripheral i/o area overlaps one of the following areas, the programmable peripheral i/o area becomes ineffective: ? peripheral i/o area ? rom area ? ram area note 1. the fixed peripheral i/o area is mirrored to the upper 4 kb of the programmable peripheral i/o area ? regardless of the base address of the ppa. if data is written in one area, data having the same contents is also written in the other area. 2. all address definitions in this manual that refer to the programmable peripheral area assume that the base address of the ppa is 03fe c000 h , that means bpc = 8ffb h . 3ff ffffh 3ff f000h 3ff efffh base + 3fffh base of ppa x3fffh x3000h x2fffh x0000h x11ffh 000 0000h peripheral i/o register programmable peripheral i/o register npb (nec peripheral bus) dedicated area for fcan controller peripheral i/o area programmable peripheral i/o area x1200h (4 kb) (16 kb) (4 kb) same area
297 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 7.2.4 npb access timing all accesses to the peripheral i/o areas are passed over to the npb bus via the vsb - npb bus bridge bbr. read and write access times to registers via the npb depend on the register (refer to ?registers access times? on page 985 ), the system clock vbclk and the setting of the vswc register. the cpu operation during an access to a register via the npb depends also on the kind of peripheral i/o area: ? fixed peripheral i/o area during a read or write access the cpu operation stops until the access via the npb is completed. ? programmable peripheral i/o area during a read access the cpu operation stops until the read access via the npb is completed. during a write access the cpu operation continues operation, provided any preceded npb access is already finished. if a preceded npb access is still ongoing the cpu stops until this access is finished and the npb is cleared. caution pay attention at write accesses to npb peripheral i/o registers via the programmable peripheral i/o area. since the cpu may continue operation, even though the data has not yet been transferred to its destination register, inconsistencies may occur between the program flow and the status of the registers. in particular register set-ups which change an operational status of a certain module require special notice, like, for instance, masking/unmasking of interrupts via maskable interrupt control registers xxic, enabling/disabling timers, etc. 7.2.5 bus properties this section summarizes the properties of the external bus. (1) bus width the microcontroller device accesses external memory and external i/o in 8-bit, 16-bit, or 32-bit units. the data bus size for each chip select area is specified in the local bus size configuration register (lbs). the operation for each type of access is given in ?access to 8-bit data busses? on page 336 and in ?access to 16-bit data busses? on page 342 . (2) bus priority order there are three kinds of external bus cycles as shown below. the dma cycle has the highest priority, followed by the operand data access, and instruction fetch, in that order.
298 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 (3) bus access the number of cpu clocks necessary for accessing each resource ? independent of the bus width ? is as follows: 7.2.6 boundary operation conditions the microcontroller device has the following boundary operation conditions: (1) program space instruction fetches from the internal peripheral i/o area are inhibited and yield nop operations. if a branch instruction exists at the upper limit of the internal ram area, a pre- fetch operation (invalid fetch) that straddles over the internal peripheral i/o area does not occur. (2) data space the microcontroller device is provided with an address misalign function. by this function, data of any format (word: 32 bit, halfword: 16 bit, byte: 8 bit) can be placed to any address in memory, even though the address is not aligned to the data format (that means address 4n for words, address 2n for halfwords). ? unaligned halfword data access when the lsb of the address is a0 =1, two byte accesses are performed. ? unaligned word data access when the lsb of the address is a0 =1, two byte and one halfword accesses are performed. in total it takes 3 bus cycles. ? when the lsbs of the address are a[1:0] =10 b , two halfword accesses are performed. note accessing data on misaligned addresses takes more than one bus cycle to complete data read/write. consequently, the bus efficiency will drop. table 7-4 bus priority order priority external bus cycle bus master high dma cycle dma controller operand data access cpu low instruction fetch cpu table 7-5 number of bus access clocks bus cycle configuration internal ram external i/o external memory instruction fetch normal access 1 a a) in case of contention with data access, the instruction fetch from internal ram takes 2 clocks. ?2 b branch 1 ? 2 b operand data access 1 3 b b) this is the minimum value. 2 b
299 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 7.2.7 initialization for access to external devices to enable access to external devices, initialize the following registers after any reset. 1. chip area select control registers cscn define the memory banks that are allocated to external devices. memory banks that are not allocated to external devices, must be deactivated. 2. bus cycle type configuration registers bctn specify the external devices that are connected to the microcontroller device. for memory banks that are not allocated to external devices, the corresponding bits in registers bct0 and bct1 should be reset. 3. local bus size configuration register lbs set the data bus width for the active chip select areas. 4. data wait control registers dwcn set the number of data wait states with respect to the starting bus cycle. 5. bus cycle control register bcc set the number of idle states for each chip select area. 6. page rom configuration register prc if page rom mode is selected (bctn.btk0 = 1), set whether a page rom cycle is on-page or off-page. 7. endian configuration register (bec) set the endian format for each chip select area. 8. address setup wait control register (asc) set the number of address setup wait states for each chip select area. 9. read delay control register (rddly) activate the delay of the rising edge of rd strobe, as required. caution 1. do not change these registers after initialization. 2. do not access external devices before initialization is finished. 7.2.8 external bus mute function if no access via the external memory interface is performed the external bus is set into a mute status. during mute the external bus interface pins take following states: ? a[22:0]: hold the address of the last external access ? d[31:0]: 3-state ?wr , rd , cs0 , cs1 , cs3 , cs4 : high level (inactive state)
300 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 7.3 registers access to on-chip peripherals, to external memory, and to external i/o is controlled and operated by registers of the bus control unit (bcu) and of the memory controller (memc): table 7-6 bus and memory control register overview module register name shortcut address bus control unit (bcu) peripheral area selection control register bpc ffff f064 h internal peripheral function wait control register vswc ffff f06e h chip area select control registers csc0 ffff f060 h csc1 ffff f062 h endian configuration register bec ffff f068 h pd70f3427 only: memory controller (memc) bus cycle configuration registers bct0 ffff f480 h bct1 ffff f482 h address setup wait control register asc ffff f48a h local bus size configuration register lbs ffff f48e h data wait control registers dwc0 ffff f484 h dwc1 ffff f486 h bus cycle control register bcc ffff f488 h bus mode control register bmc ffff f498 h read delay control register rddly ffff ff00 h page rom configuration register prc ffff f49a h
301 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 7.3.1 bcu registers the following registers are part of the bcu. they define the usage of the programmable peripheral i/o area (ppa), the data bus width, the endian format of word data, and they control access to external devices. (1) bpc - peripheral area selection control register the 16-bit bpc register defines whether the programmable peripheral i/o area (ppa) is used or not and determines the starting address of the ppa. access this register can be read/written in 16-bit units. address ffff f064 h initial value 0000 h caution bit 14 must always be 0. the base address pba of the programmable peripheral area sets the start address of the 16 kb ppa in a range of 256 mb. the 256 mb page is mirrored 16 times to the entire 32-bit address range. the base address pba is calculated by pba = bpc.pa[13:0] x 2 14 table 7-8 shows how the base address pba of the programmable peripheral area is assembled. 1514131211109876543210 pa15 0 pa13 pa12 pa11 pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 table 7-7 bpc register contents bit position bit name function 15 pa15 select usage of programmable peripheral i/o area (ppa). 0: ppa disabled 1: ppa enabled 13 to 0 pa[13:0] bits pa[13:0] specify bits 27 to 14 of the starting address of the ppa. the other bits of the address are fixed to 0. table 7-8 address range of programmable peripheral area (16 kb) 31 ? 28 27 ? 14 13 ? 1 0 bit 0 ? 0 bpc.pa[13:0] 1 ? 1 1 ?? ? 0 ? 0 bpc.pa[13:0] 0 ? 0 1 0 ? 0 bpc.pa[13:0] 0 ? 0 0 pba
302 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 note the recommended setting for the bpc register is 8ffb h . with this configuration the programmable peripheral area is mapped to the address range 03fe c000 h to 03fe ffff h . with this setting the can message buffer registers are accessible via the addresses given in ?can controller (can)? on page 719 . the fixed peripheral area is mirrored to the address range 03fe e000 h to 03fe ffff h .
303 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 (2) vswc - internal peripheral function wait control register the 8-bit vswc register defines the wait states inserted when accessing peripheral special function registers via the internal bus. both address setup and data wait states are based on the system clock. access this register can be read/written in 8-bit or 1-bit units. address ffff f06e h initial value 77 h 76543210 0 suwl2 suwl1 suwl0 0 vswl2 vswl1 vswl0 r/w r/w r/w r/w r/w r/w r/w r/w table 7-9 vswc register contents bit position bit name function 6 to 4 suwl[2:0] address setup wait for internal bus: suwl2 suwl1 suwl0 number of address setup wait states 00 0 0 00 1 1 cpu system clock (vbclk) 01 0 2 cpu system clock (vbclk) 01 1 3 cpu system clock (vbclk) 10 0 4 cpu system clock (vbclk) 10 1 5 cpu system clock (vbclk) 11 0 6 cpu system clock (vbclk) 11 1 7 cpu system clock (vbclk) 2 to 0 vswl[2:0] data wait for internal bus: vswl2 vswl1 vswl0 number of data wait states 00 0 0 00 1 1 cpu system clock (vbclk) 01 0 2 cpu system clock (vbclk) 01 1 3 cpu system clock (vbclk) 10 0 4 cpu system clock (vbclk) 10 1 5 cpu system clock (vbclk) 11 0 6 cpu system clock (vbclk) 11 1 7 cpu system clock (vbclk)
304 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 the following setups are recommended for vswc: table 7-10 recommended timing for internal bus system clock a f vbclk a) when deriving the system clock from the modulated clock of the sscg, the maxi- mum clock determines the correct register setting.  16 mhz  25 mhz  33 mhz  50 mhz  66 mhz suwl 00111 vswl 01123 vswc 00 h 01 h 11 h 12 h 13 h
305 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 (3) cscn - chip area select control registers the 16-bit registers csc0 and csc1 assign the chip select signals cs0 to cs3 and cs4 to cs7 to memory blanks (see also ?memory banks and chip select signals? on page 292 ). if a bit in cscn is set, access to the corresponding memory bank will generate the corresponding chip select signal and activate the memory controller. if several chip select signals are assigned to identical memory areas, a priority control rules the generation of the signals (refer to ?chips select priority control? on page 295 ). access these registers can be read/written in 16-bit units. address csc0: ffff f060 h csc1: ffff f062 h initial value 2c11 h these registers must be initialized as described in ta bl e 7 - 1 3 and ta bl e 7 - 1 4 . the register contents in table 7-11 and table 7-12 read as follows: ? cskm = 0: corresponding chip select signal is not active during access to memory bank. ? cskm = 1: corresponding chip select signal is active during access to memory bank. caution to initialize an external memory area after a reset, registers cscn have to be set. do not change these registers after initialization. do not access external devices before initialization is finished. csc0 1514131211109876543210 cs33 cs32 cs31 cs30 cs23 cs22 cs21 cs20 cs13 cs12 cs11 cs10 cs03 cs02 cs01 cs00 cs3 cs2 cs1 cs0 csc1 1514131211109876543210 cs43 cs42 cs41 cs40 cs53 cs52 cs51 cs50 cs63 cs62 cs61 cs60 cs73 cs72 cs71 cs70 cs4 cs5 cs6 cs7
306 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 table 7-11 csc0 register contents bit position bit name access to memory bank chip select signal 15 cs33 7 cs3 14 cs32 6 13 cs31 4 or 5 12 cs30 0, 1, 2 or 3 11 cs23 3 cs2 10 cs22 2 9cs21 1 8cs20 0 7cs13 5 cs1 6cs12 4 5cs11 2 or 3 0cs10 0 or 1 3cs03 3 cs0 2cs02 2 1cs01 1 0cs00 0 table 7-12 csc1 register contents bit position bit name access to memory bank chip select signal 15 cs43 8 cs4 14 cs42 9 13 cs41 10 or 11 12 cs40 12, 13, 14 or 15 11 cs53 12 cs5 10 cs52 13 9cs51 14 8cs50 15 7cs63 10 cs6 6cs62 11 5 cs61 12 or 13 0 cs60 14 or 15 3cs73 12 cs7 2cs72 13 1cs71 14 0cs70 15
307 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 initialization initialize the cscn registers as shown in ? ta bl e 7 - 1 3 for pd70f3426a ? ta bl e 7 - 1 4 for pd70f3427 a caution for the pd70f3426a the csc0 register must be changed to 2811 h and csc1 must be left with its default value 2c11 h . do not modify these registers after setting csc0 = 2811 h . table 7-13 initialization of the pd70f3426a cscn registers bits set to value comment csc0.cs0[3:0] 0001 b cs0 assigned to bank 0 to vsb flash memory 010 0000 h - 01f ffff h . csc0.cs0[3:0] must be left with their default value 1000 b . csc0.cs1[3:0] 1000 b csc0.cs1[3:0] must be left with their default value 1000 b . csc0.cs2[3:0] 1000 b cs2 assigned to bank 3 to vsb ram memory 060 0000 h -0605fff h . caution: csc0.cs2[3:0] must be changed to 1000 b (default value is 1100 b ). csc0.cs3[3:0] 0010 b csc0.cs3[3:0] must be left with their default value 0010 b . csc1.cs4[3:0] 0010 b csc1.cs4[3:0] must be left with their default value 0010 b . csc1.cs5[3:0] 1100 b csc1.cs5[3:0] must be left with their default value 1100 b . csc1.cs6[3:0] 0001 b csc1.cs6[3:0] must be left with their default value 0001 b . csc1.cs7[3:0] 0001 b csc1.cs7[3:0] must be left with their default value 0001 b .
308 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 table 7-14 initialization of the pd70f3427 cscn registers bits set to value comment csc0.cs0[3:0] xx00 b set csc0.cs0[3:2] as required to assign cs0 to bank 2 to 3 to external memory 040 0000 h - 07f ffff h . caution: csc0.cs0[1:0] must be changed to 00 b (default value is 01 b ). csc0.cs1[3:0] xxx0 b set csc0.cs1[3:1] as required to assign cs1 to bank 2 to 5 to external memory 040 0000 h - 0ff ffff h . caution: csc0.cs10 must be changed to 0 (default value is 1). csc0.cs2[3:0] 1100 b csc0.cs2[3:0] must be left with their default value 1100 b . csc0.cs3[3:0] xxx0 b set csc0.cs3[3:1] as required to assign cs3 to bank 4 to 7 to external memory 080 0000 h - 1ff ffff h . csc0.cs30 must be left with its default value 0. csc1.cs4[3:0] xxx0 b set csc1.cs4[3:1] as required to assign cs4 to bank 8 to 11 to external memory 200 0000 h - 37f ffff h . csc0.cs40 must be left with its default value 0. csc0.cs5[3:0] 1100 b csc0.cs5[3:0] must be left with their default value 1100 b . csc1.cs6[3:0] 0001 b csc0.cs6[3:0] must be left with their default value 0001 b . csc1.cs7[3:0] 0001 b csc0.cs7[3:0] must be left with their default value 0001 b .
309 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 (4) bec - endian configuration register the 16-bit bec register defines the endian format in which word data in the memory is processed. each chip select area is controlled separately. access this register can be read/written in 16-bit units. address ffff f068 h initial value 0000 h this register must be initialized as described in ta b l e 7 - 1 6 and ta b l e 7 - 1 7 . caution 1. the bits marked with 0 must always be 0. 2. to initialize an external memory area after a reset, register bec has to be set. do not change this register after initialization. do not access external devices before initialization is finished. note 1. accesses to all internal resources are fixed to little endian format. 2. different chip select signals can be active for the same memory bank. the priority order defines, which chip select signal is valid. 3. set the chip select area which is specified as the programmable peripheral i/o area to little endian format. 1514131211109876543210 0 be70 0 be60 0 be50 0 be40 0 be30 0 be20 0 be10 0 be00 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 table 7-15 bec register contents bit position bit name function 14, 12, 10, 8, 6, 4, 0 bek0 sets the endian format for processing of word data for each chip select area. 0: little endian 1: big endian
310 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 initialization initialize the bec register as shown in ? ta bl e 7 - 1 6 for pd70f3426a ? ta bl e 7 - 1 7 for pd70f3427 caution for the pd70f3426a the bec register must be left with its default value 0000 h . do not modify this register. table 7-16 initialization of the pd70f3426a bec register bits set to value comment bec.be00 0 endian format for vsb flash memory: little endian bec.be00 must be left with their default value 0 bec.be10 0 b bec.be10 must be left with their default value 0 bec.be20 0 endian format for vsb ram: little endian bec.be20 must be left with their default value 0 bec.be30 0 b bec.be30 must be left with their default value 0 bec.be40 0 b bec.be40 must be left with their default value 0 bec.be50 0 b bec.be50 must be left with their default value 0 bec.be60 0 b bec.be60 must be left with their default value 0 bec.be70 0 b bec.be70 must be left with their default value 0 table 7-17 initialization of the pd70f3427 bec register bits set to value comment bec.be00 x b set as required bec.be10 x b set as required bec.be20 0 b bec.be20 must be left with their default value 0 bec.be30 x b set as required bec.be40 x b set as required bec.be50 0 b bec.be50 must be left with their default value 0 bec.be60 0 b bec.be60 must be left with their default value 0 bec.be70 0 b bec.be70 must be left with their default value 0
311 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 7.3.2 memory controller registers (pd70f3427 only) the following registers are part of the memory controller. they specify the type of external device that is connected, the number of data wait states, the number of address wait states, the number of idle states, and they control features for page rom. (1) bctn - bus cycle configuration registers the 16-bit bct0 register specifies the external devices that are connected to the microcontroller device. the register enables the operation of the memory controller for each chip select signal. access these registers can be read/written in 16-bit units. address bct0: ffff f480 h bct1: ffff f482 h initial value 0000 h caution 1. the bits marked with 0 must always be 0. 2. to initialize an external memory area after a reset, registers bctn have to be set. do not change this register after initialization. do not access external devices before initialization is finished. low power mode setting the memory controller into low power mode by changing the bit bmc.pwdn impacts the bctn registers as follows: ? entering low power mode by setting bmc.pwdn = 1 bct0 1514131211109876543210 me3 0 0 bt30 me2 0 0 bt20 me1 0 0 bt10 me0 0 0 bt00 cs3 cs2 cs1 cs0 bct1 1514131211109876543210 me7 0 0 bt70 me6 0 0 bt60 me5 0 0 bt50 me4 0 0 bt40 cs7 cs6 cs5 cs4 table 7-18 bctn register contents bit position bit name function 15, 11, 7, 3 mek enables/disables memory controller operation for chip select area k. 0: operation disabled 1: operation enabled 12, 8, 4, 0 btk0 specifies the devices that are connected to chip select area k. 0: sram or external i/o connected 1: page rom connected
312 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 ? bits bctn.btm are set to 0 ? bits bctn.mem are retained ? bus clock is stopped ? entering normal operation mode by setting bmc.pwdn = 0 ? bits bctn.mem are set to 0 ? bus clock is started thus after entering and leaving the low power mode, the bctn registers hold their initial values 0000 h . (2) lbs - local bus size configuration register the 16-bit lbs register controls the data bus width for each chip select area. access this register can be read/written in 16-bit units. address ffff f48e h initial value aaaa h . 1514131211109876543210 lb71 lb70 lb61 lb60 lb51 lb50 lb41 lb40 lb31 lb30 lb21 lb20 lb11 lb10 lb01 lb00 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 table 7-19 lbs register contents bit position bit name function 15 to 0 lbk[1:0] sets the data bus width for each chip select area. lbk1 lbk0 data bus size 00 8 bit 01 16 bit 10 32 bit 11 prohibited
313 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 (3) asc - address setup wait control register the 16-bit asc register controls the number of wait states between address setup and the first access cycle (t1). each chip select area is controlled separately. a maximum of three address setup wait states is possible. address setup wait states can be inserted when accessing ?sram ? page rom access this register can be read/written in 16-bit units. address ffff f48a h initial value ffff h : after system setup, by default, three address setup wait states are inserted for each chip select area. note 1. during address setup wait, the external wait function (wait pin) is disabled. 2. for access to internal memory, the setting of register asc is neglected. no wait states are inserted after address setup. caution to initialize an external memory area after a reset, this register has to be set. do not access external devices before initialization is finished. do not change this register while an external device is accessed. 1514131211109876543210 ac71 ac70 ac61 ac60 ac51 ac50 ac41 ac40 ac31 ac30 ac21 ac20 ac11 ac10 ac01 ac00 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 table 7-20 asc register contents bit position bit name function 15 to 0 ack[1:0] sets the number of address setup wait states for each chip select area. ack[1:0] wait states inserted after address setup 00 b no wait state inserted 01 b 1 wait state 10 b 2 wait states 11 b 3 wait states
314 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 (4) dwcn - data wait control registers the 16-bit dwcn registers control the number of wait states after the first access cycle (t1). each chip select area is controlled separately. a maximum of seven data wait states is possible. access this register can be read/written in 16-bit units. address dwc0: ffff f484 h dwc1: ffff ffe0 h initial value 7777 h : after system setup, by default, seven data wait states are inserted for each chip select area. note 1. for access to internal memory, programmable waits are not carried out. 2. during page rom on-page access, wait control is performed according to prc register setting. caution to initialize an external memory area after a reset, this register has to be set. do not access external devices before initialization is finished. do not change this register while an external device is accessed. dwc0 1514131211109876543210 0 dw32 dw31 dw30 0 dw22 dw21 dw20 0 dw12 dw11 dw10 0 dw02 dw01 dw00 cs3 cs2 cs1 cs0 dwc1 1514131211109876543210 0 dw72 dw71 dw70 0 dw62 dw61 dw60 0 dw52 dw51 dw50 0 dw42 dw41 dw40 cs7 cs6 cs5 cs4 table 7-21 dwcn registers contents bit position bit name function 15 to 0 dwk[2:0] sets the number of wait states after the first access cycle (t1) for each chip select area. dwk[2:0] number of inserted wait states 000 b no wait state inserted 001 b 1 wait state 010 b 2 wait states 011 b 3 wait states ... ... 111 b 7 wait states
315 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 (5) bcc - bus cycle control register the 16-bit bcc register controls the number of idle states inserted after the t2 cycle. each chip select area is controlled separately. a maximum of three idle states is possible. idle states can be inserted when accessing sram , external i/o, external rom, or page rom. access this register can be read/written in 16-bit units. address ffff f488 h initial value ffff h . after system reset, three idle states are inserted. note for access to internal memory, no idle states are inserted. caution to initialize an external memory area after a reset, this register has to be set. do not access external devices before initialization is finished. do not change this register while an external device is accessed. 1514131211109876543210 bc71 bc70 bc61 bc60 bc51 bc50 bc41 bc40 bc31 bc30 bc21 bc20 bc11 bc10 bc01 bc00 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 table 7-22 bcc register contents bit position bit name function 15 to 0 bck[1:0] sets the number of idle states for each chip select area. bck[1:0] inserted idle states 00 b no idle state inserted 01 b 1 idle state 10 b 2 idle states 11 b 3 idle states
316 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 (6) bmc- bus mode control register the 8-bit bmc register controls the operation of the memory interface and its clock supply. access this register can be read/written in 8- and 1-bit units. address ffff f498 h initial value 00 h caution 1. to initialize an external memory area after a reset, this register has to be set. do not access external devices before initialization is finished. do not change this register while an external device is accessed. 2. if the cpu system clock vbclk is chosen above 32 mhz the memory interface clock must be set to vbclk/2, i.e. bmc.ckm0 = 1. 3. when changing the bmc.ckm0 bit, it is necessary to set vswc.vswl[2:0] = 111 b before accessing the bmc register. 4. if only the bmc.pdwn bit is changed, the presetting of the vswc register is unnecessary. 5. when bmc.pdwn bit is set to "1", the bmc.ckm0 bit is reset to ?0? and the following registers of the memory controller are reset bct0, bct1  reset value 0000 h dwc0, dwc1  reset value 7777 h bcc  reset value ffff h asc  reset value ffff h lbs  reset value aaaa h prc  reset value 7000 h therefore, it is necessary to initialize all registers again after return from power down mode. when the bcm.ckm0 bit is changed again, the presetting of the vswc register is also necessary. 76543210 00000pdwn0 a a) the default value ?0? of bit 1 must not be changed. ckm0 rrrrrrrr/w table 7-23 bmc register contents bit position bit name function 0 ckm0 memory interface clock selection 0: vbclk 1: vbclk/2 2 pdwn operation mode selection: 0: normal operation 1: low power mode (operation is stopped and memory interface output signals are set to inactive levels)
317 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 example for setting the bmc.cmk0 bit (7) rddly - read delay control register the 8-bit rddly register controls the delay of the read strobe rd of the external memory interface?s cs1 area. it provides the option to delay the rising edge of the rd by a half of the bus clock cycle bclk. access this register can be read/written in 8- and 1-bit units. address ffff ff00 h initial value 00 h caution 1. to initialize an external memory area after a reset, this register has to be set. do not access external devices before initialization is finished. do not change this register while an external device is accessed. 2. read strobe delay can only be applied to the cs1 area. ld.b vswc[r0],r11 // save the origin vswc register setting ori 0x07,r11,r10 // set vswc.vswl[2:0] bits to 1 st.b r10,vswc[r0] set1 0,bmc[r0] // set the cmk0 bit to 1 st.b r11,vswc[r0] // restore the origin vswc register setting 76543210 0000000 rddlyen rrrrrrrr/w table 7-24 rddly register contents bit position bit name function 0 rddlyen read strobe control. 0: rising rd edge not delayed 1: rising rd edge delayed by half bclk clock cycle
318 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 (8) prc - page rom configuration register the 16-bit prc register controls whether a page rom cycle is on-page or off-page. the register specifies the address mask. masked address bits are not considered when deciding between on-page or off-page access. set the mask according to the number of continuously readable bits. for page access (cycle is on-page) the register defines the number of inserted data wait cycles. access this register can be read/written in 16-bit units. address ffff f49a h initial value 7000 h 1514131211109876543210 0 prw2 prw1 prw0 0 0 0 0 0 0 0 0 ma6 ma5 ma4 ma3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 7-25 prc register contents bit position bit name function 14 to 12 prw[2:0] page rom on-page wait control. sets the number of data waits corresponding to the internal system clock. prw[2:0] inserted data wait states 000 b no wait state inserted 001 b 1 wait state 010 b 2 wait states 011 b 3 wait states ... ... 111 b 7 wait states note: the number of wait states defined in the prc register is only valid if on-page access is enabled. if on-page is disabled, the number of wait states is defined by registers dwc0 and dwc1. 3 to 0 ma[6:3] mask address. setting bits ma6 to ma3 masks the corresponding addresses a6 to a3. ma6 ma5 ma4 ma3 number of continuously readable bits bus width: 8 bits lbk[1:0]=00 b bus width: 16 bits lbk[1:0]=01 b bus width: 32 bits lbk[1:0]=10 b 0 0 0 0 8 x 8 bits 4 x 16 bits 2 x 32 bits 0 0 0 1 16 x 8 bits 8 x 16 bits 4 x 32 bits 0 0 1 1 32 x 8 bits 16 x 16 bits 8 x 32 bits 0 1 1 1 64 x 8 bits 32 x 16 bits 16 x 32 bits 1 1 1 1 128 x 8 bits 64 x 16 bits 32 x 32 bits
319 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 note to initialize an external memory area after a reset, register prc has to be set if page rom mode is selected. do not change this register after initialization. do not access external page rom devices before initialization is finished. caution to initialize an external memory area after a reset, this register has to be set. do not access external devices before initialization is finished. do not change this register while an external device is accessed.
320 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 7.4 page rom controller in page rom mode the microcontroller reads consecutive data from one page by inserting the wait cycles defined by prc.prw[2:0] instead of wait cycles defined in registers dwc0 and dwc1. the page rom controller decides whether a page rom cycle is on-page or off-page. to do so, it buffers the address of the previous cycle and compares it with the address of the current cycle. if the compare result proves that the read access is on-page the read cycle is performed with wait cycles defined by prc.prw[2:0]. in the page rom configuration register (prc), one or more of the address bits (a3 to a6) are set as masking addresses (no comparison is made for these addresses). the masking address is chosen according to the configuration of the connected page rom and the number of continuously readable bits. wait control for normal access (off-page) and page access (on-page) is specified by different registers: for page access, wait control is performed according to prc register setting. for normal access, wait control is performed according to dwc0 and dwc1 register settings. the following figures show the on-page/off-page judgment during page rom connection for a 16-mbit page rom and for different data bus widths. (1) 8-bit data bus width the page size or the number of continuously readable bits is 32 x 8 bit. to provide 32 addresses, a 5-bit on-page address is required. therefore, set prc.ma[6:3] = 0011 b . figure 7-5 16-mbit page rom (2 m 8 bits), page size 32 x 8 bit (2) 16-bit data bus width the page size or the number of continuously readable bits is 8 x 16 bit. to provide 8 addresses, a 3-bit on-page address is required. therefore, set prc.ma[6:3] = 0001 b . note for a 16-bit data bus, bit a0 of the output address is not used. a4 a0 internal address latch (immediately preceding address) output address page rom address off-page address ma6 0 ma5 0 ma4 1 ma3 1 prc register setting comparison a3 a5 a6 a7 ... ... ... a22 a4 a3 a5 a6 a7 a22 a2 a1 a2 a1 a3 a4 a5 a0 on-page address a19 a6 a7 a21 a20 a19 a20
321 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 figure 7-6 16-mbit page rom (1 m 16 bits), page size 8 x 16 bit (3) 32-bit data bus width the page size or the number of continuously readable bits is 2 x 32 bit. to provide 2 addresses, a 1-bit on-page address is required. therefore, set prc.ma[6:3] = 0000 b . note for a 32-bit data bus, bits a0 and a1 of the output address are not used. figure 7-7 16-mbit page rom (512 k 32 bits), page size 2 x 32 bit a4 a0 internal address latch (immediately preceding address) output address page rom address off-page address ma6 0 ma5 0 ma4 0 ma3 1 prc register setting comparison a3 a5 a6 a7 ... ... a22 a4 a3 a5 a6 a7 a22 a2 a1 a2 a1 a3 a4 a6 a18 a0 on-page address ... a5 a19 a19 a21 a20 a4 a0 internal address latch (immediately preceding address) output address page rom address off-page address ma6 0 ma5 0 ma4 0 ma3 0 prc register setting comparison a3 a5 a6 a7 ... ... ... a22 a4 a3 a5 a6 a7 a22 a2 a1 a2 a1 a3 a4 a5 a0 on-page address a19 a17 a21 a20 a18
322 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 7.5 configuration of memory access the microcontroller device supports interfacing with various memory devices. therefore, the endian format, wait functions and idle state insertions can be configured. 7.5.1 endian format the endian format is specified with the endian configuration register (bec). it defines the byte order in which word data is stored. "big endian" means that the high-order byte of the word is stored in memory at the lowest address, and the low-order byte at the highest address. therefore, the base address of the word addresses the high-order byte: figure 7-8 big endian addresses within a word "little endian" means that the low-order byte of the word is stored in memory at the lowest address, and the high-order byte at the highest address. therefore, the base address of the word addresses the low-order byte: figure 7-9 little endian addresses within a word 7.5.2 wait function several wait functions are supported: (1) address setup wait the microcontroller device allows insertion of address setup wait states before the first access cycle (t1 state). the number of address setup wait states can be set with the address setup wait control register asc for each cs area. address setup wait states can be inserted when accessing sram or page rom. 31 24 23 16 15 8 0 7 byte 0 byte 1 byte 2 byte 3 + 3 + 2 + 1 access via addresses byte position bit number 31 24 23 16 15 8 0 7 byte 3 byte 2 byte 1 byte 0 + 3 + 2 + 1 access via addresses byte position bit number
323 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 (2) programmable wait function with the purpose of realizing easy interfacing with low-speed memory or with i/os, it is possible to insert up to seven data wait states after the first access cycle (t1 state). the number of wait states can be specified by data wait control registers dwc0 and dwc1. for on-page access of a page rom, wait control is performed according to page rom configuration register (prc) setting. the settings of registers dwc0 and dwc1 are neglected. (3) external wait function each read or write operation takes at least two cycles (t1 and t2). to stretch the access cycle for accessing slow external devices, any number of wait states (tw) can be inserted under external control of the wait signal. the wait signal can be set asynchronously from the system clock. the wait signal is sampled at the rising edge of the clock in the t1 and tw states. depending on the level of the wait signal at sampling timing, a wait state is inserted or not. (4) relationship between programmable wait and external wait if both programmable wait and external wait (wait ) are applied, an or relation gives the resulting number of wait cycles. figure 7-10 shows that as long as any of the two waits is active, a wait cycle will be performed. figure 7-10 example of wait insertion note the circles indicate the sampling timing. t1 tw tw bclk wait pin w a it b y wait pin progr a mm ab le w a it w a it control tw t2
324 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 7.5.3 idle state insertion to facilitate interfacing with low-speed memory devices, an idle state (ti) can be inserted between two bus cycles, that means after the t2 state. idle states are inserted to meet the data output float delay time on memory read access for each cs space. idle states are used to guarantee the interval until the external data bus is released by memory. the next bus cycle is started after the idle state(s). idle states can be inserted after t2 state when accessing sram, external i/o, external rom, or page rom. the number of idle states can be specified by program using the bus cycle control register (bcc). 7.6 external devices interface timing this section presents examples of write and read operations. the states are abbreviated as: ? t1 and t2 states: basic states for access. ? tw state: wait state that is inserted according to the dwc0 and dwc1 register settings and according to the wait input. ? tasw state: address setting wait state that is inserted according to the asc register settings. ? ti state: idle state that is inserted according to the bcc register settings. note for access to page rom, see ?page rom access timing? on page 331 .
325 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 7.6.1 writing to external devices this section shows typical sequences of writing data to external devices. (1) write with external wait cycle figure 7-11 timing: write data register settings: ? bctm.btk0 = 0 (connected external device is sram or external i/o) ? asc.ack[1:0] = 00 b (no address setup wait states inserted) ? dwcm.dwk[2:0] = 000 b (no programmable data wait states inserted) ? bcc.bck[1:0] = 00 b (no idle states inserted) note 1. the circles indicate the sampling timing. 2. the broken line indicates the high-impedance state (bus is not driven). the data has to be stable at the rising edge of the wr signal. for details refer to the data sheet . t1 d a t a wait (inp u t) d] 3 1:0] (i/o) wr (o u tp u t) rd (o u tp u t) a[2 3 :0]/be[ 3 :0] (o u tp u t) bclk d a t a tw t1 c s k (o u tp u t) t2 t2 addre ss /be[ 3 :0] addre ss /be[ 3 :0]
326 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 (2) write with address setup wait and idle state insertion figure 7-12 timing: write data with address setup wait and idle state insertion register settings: ? bctm.btk0 = 0 (connected external device is sram or external i/o) ? asc.ack[1:0] = 01 b (one address setup wait state inserted) ? dwcm.dwk[2:0] = 000 b (no programmable data wait states inserted) ? bcc.bck[1:0] = 01 b (one idle state inserted) note 1. the circles indicate the sampling timing. 2. the broken line indicates the high-impedance state (bus is not driven). the data has to be stable at the rising edge of the wr signal. for details refer to the data sheet . ta s w d a t a wait (inp u t) d[ 3 1:0] (i/o) wr (o u tp u t) rd (o u tp u t) bclk ti t2 c s k (o u tp u t) t1 a[2 3 :0]/be[ 3 :0] (o u tp u t) addre ss /be[ 3 :0]
327 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 7.6.2 reading from external devices this section shows typical sequences of reading data from external devices. (1) read with external wait cycle figure 7-13 timing: read data register settings: ? bctm.btk0 = 0 (connected external device is sram or external i/o) ? asc.ack[1:0] = 00 b (no address setup wait states inserted) ? dwcm.dwk[2:0] = 000 b (no programmable data wait states inserted) ? bcc.bck[1:0] = 00 b (no idle states inserted) note 1. the circles indicate the sampling timing. 2. the broken line indicates the high-impedance state (bus is not driven). t1 d a t a wait (inp u t) d[ 3 1:0] (i/o) wr (o u tp u t) rd (o u tp u t) c s k (o u tp u t) bclk d a t a tw t1 t2 t2 a[2 3 :0]/be[ 3 :0] (o u tp u t) addre ss /be[ 3 :0] addre ss /be[ 3 :0]
328 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 (2) read with address setup wait and idle state insertion figure 7-14 timing: read data with address setup wait and idle state insertion register settings: ? bctm.btk0 = 0 (connected external device is sram or external i/o) ? asc.ack[1:0] = 01 b (one address setup wait state inserted) ? dwcm.dwk[2:0] = 000 b (no programmable data wait states inserted) ? bcc.bck[1:0] = 01 b (one idle state inserted) note 1. the circles indicate the sampling timing. 2. the broken line indicates the high-impedance state (bus is not driven). ta s w d a t a wait (inp u t) d[ 3 1:0] (i/o) wr (o u tp u t) rd (o u tp u t) c s k (o u tp u t) bclk ti t2 t1 a[2 3 :0]/be[ 3 :0] (o u tp u t) addre ss /be[ 3 :0]
329 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 7.6.3 read-write operati on on external devices figure 7-15 read-write operation register settings: ? bctm.btk0 = 0 (connected external device is sram or external i/o) ? asc.ack[1:0] = 00 b (no address setup wait states inserted) ? dwcm.dwk[2:0] = 000 b (no programmable data wait states inserted) ? bcc.bck[1:0] = 00 b (no idle states inserted) note 1. the circles indicate the sampling timing. 2. the broken line indicates the high-impedance state (bus is not driven). the data has to be stable at the rising edge of the wr signal. for details refer to the data sheet . t1 d a t a d a t a wait (inp u t) d[ 3 1:0] (i/o) wr (o u tp u t) rd (o u tp u t) bclk t2 t1 c s k (o u tp u t) t2 a[2 3 :0]/be[ 3 :0] (o u tp u t) addre ss /be[ 3 :0]
330 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 7.6.4 write-read operati on on external devices figure 7-16 write-read operation register settings: ? bctm.btk0 = 0 (connected external device is sram or external i/o) ? asc.ack[1:0] = 00 b (no address setup wait states inserted) ? dwcm.dwk[2:0] = 000 b (no programmable data wait states inserted) ? bcc.bck[1:0] = 00 b (no idle states inserted) note 1. the circles indicate the sampling timing. 2. the broken line indicates the high-impedance state (bus is not driven). the data has to be stable at the rising edge of the wr signal. for details refer to the data sheet . t1 d a t a wait (inp u t) d[ 3 1:0] (i/o) wr (o u tp u t) rd (o u tp u t) bclk t2 t1 c s k (o u tp u t) d a t a addre ss /be[ 3 :0] t2 a[2 3 :0]/be[ 3 :0] (o u tp u t)
331 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 7.7 page rom access timing this section presents examples of read operations on page rom. the states are abbreviated as: ? t1 and t2 states: basic states for access. ? tw state: wait state that is inserted according to the dwc0 and dwc1 register settings and according to the wait input. ? tow state: wait state that is inserted according to the prc.prw[2:0] settings and according to the wait input. ? to1 and to2: on-page states ? tasw state: address setting wait state that is inserted according to the asc register settings. ? ti state: idle state that is inserted according to the bcc register settings.
332 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 7.7.1 half word/word access with 8-bit bus or word access with 16- bit bus (1) read operation note that during on-page access, less data wait states are inserted than during off-page access. figure 7-17 reading page rom ? register settings: ? bctm.btk0 = 1 (connected external device is page rom) ? asc.ack[1:0] = 00 b (no address setup wait states inserted) ? dwcm.dwk[2:0] = 010 b (two programmable data wait states for off-page access inserted) ? prc.prw[2:0] = 001 b (one programmable data wait state for on-page access inserted) ? bcc.bck[1:0] = 00 b (no idle states inserted) note 1. the circles indicate the sampling timing. 2. the broken line indicates the high-impedance state (bus is not driven). t1 off-p a ge a ddre ss /be[ 3 :0] d a t a wait (inp u t) d[15:0] (i/o) d[7:0] (i/o) wr (o u tp u t) rd (o u tp u t) c s k (o u tp u t) bclk d a t a on-p a ge a ddre ss /be[ 3 :0] to1 t2 tw to2 tw tow a[2 3 :0]/be[ 3 :0] (o u tp u t)
333 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 (2) read operation with address setup wait states and idle state insertion figure 7-18 reading page rom with address setup wait states and idle state insertion register settings: ? bctm.btk0 = 1 (connected external device is page rom) ? asc.ack[1:0] = 01 b (one address setup wait state inserted) ? dwcm.dwk[2:0] = 000 b (no programmable data wait states for off-page access inserted) ? prc.prw[2:0] = 000 b (no programmable data wait states for on-page access inserted) ? bcc.bck[1:0] : see figure 7-18 note 1. the circles indicate the sampling timing. 2. the broken line indicates the high-impedance state (bus is not driven). ta s w off-p a ge a ddre ss /be[ 3 :0] d a t a wait (inp u t) d[15:0] (i/o) d[7:0] (i/o) wr (o u tp u t) rd (o u tp u t) c s k (o u tp u t) a[2 3 :0] /be[ 3 :0] (o u tp u t) bclk d a t a on-p a ge a ddre ss /be[ 3 :0] ta s w t2 t1 to2 ti to1 bcc.bck[1:0] 00b 01b
334 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 7.7.2 byte access with 8-bit bus or byte/half word access with 16- bit bus (1) read operation note that during on-page access, less data wait states are inserted than during off-page access. figure 7-19 reading page rom register settings: ? bctm.btk0 = 1 (connected external device is page rom) ? asc.ack[1:0] = 00 b (no address setup wait states inserted) ? dwcm.dwk[2:0] = 010 b (two programmable data wait states for off-page access inserted) ? prc.prw[2:0] = 001 b (one programmable data wait state for on-page access inserted) ? bcc.bck[1:0] = 00 b (no idle states inserted) note 1. the circles indicate the sampling timing. 2. the broken line indicates the high-impedance state (bus is not driven). t1 off-p a ge a ddre ss /be[ 3 :0] d a t a wait (inp u t) d[15:0] (i/o) d[7:0] (i/o) wr (o u tp u t) rd (o u tp u t) c s k (o u tp u t) bclk d a t a on-p a ge a ddre ss /be[ 3 :0] to1 t2 tw to2 tw tow a[2 3 :0] /be[ 3 :0] (o u tp u t)
335 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 (2) read operation with address setup wait states and idle state insertion figure 7-20 reading page rom with address setup wait states and idle state insertion register settings: ? bctm.btk0 = 1 (connected external device is page rom) ? asc.ack[1:0] = 01 b (one address setup wait state inserted) ? dwcm.dwk[2:0] = 000 b (no programmable data wait states for off-page access inserted) ? prc.prw[2:0] = 000 b (no programmable data wait states for on-page access inserted) ? bcc.bck[1:0] : see figure 7-20 note 1. the circles indicate the sampling timing. 2. the broken line indicates the high-impedance state (bus is not driven). ta s w off-p a ge a ddre ss /be[ 3 :0] d a t a wait (inp u t) d[15:0] (i/o) d[7:0] (i/o) wr (o u tp u t) rd (o u tp u t) c s k (o u tp u t) bclk d a t a on-p a ge a ddre ss /be[ 3 :0] ta s w t2 t1 to1 to2 ti bcc.bck[1:0] 00b 01b a[2 3 :0] /be[ 3 :0] (o u tp u t)
336 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 7.8 data access order 7.8.1 access to 8-bit data busses this section shows how byte, half word and word accesses are performed for an 8-bit data bus. (1) byte access (8 bits) (a) little endian figure 7-21 left: access to even address (2n) right: access to odd address (2n + 1) (b) big endian figure 7-22 left: access to even address (2n) right: access to odd address (2n + 1) 7 0 7 0 byte data external data bus 2n address 7 0 7 0 byte data external data bus 2n + 1 address 7 0 7 0 byte data external data bus 2n address 7 0 7 0 byte data external data bus 2n + 1 address
337 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 (2) halfword access (16 bits) (a) little endian figure 7-23 left: access to even address (2n) right: access to odd address (2n + 1) (b) big endian figure 7-24 left: access to even address (2n) right: access to odd address (2n + 1) 7 0 7 0 halfword data 15 8 external data bus address 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 2n 1-st access 2-nd access 1-st access 2-nd access 7 0 7 0 halfword data 15 8 external data bus address 7 0 7 0 halfword data 15 8 external data bus 2n + 2 address 2n + 1 1-st access 2-nd access 1-st access 2-nd access 7 0 7 0 halfword data 15 8 external data bus 2n address 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 external data bus 2n + 2 address
338 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 (3) word access (32 bits) (a) little endian figure 7-25 access to address 4n figure 7-26 access to address 4n + 1 7 0 7 0 word data external data bus address 15 8 4n 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 1-st access 2-nd access 3-rd access 4-th access 7 0 7 0 word data external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 1-st access 2-nd access 3-rd access 4-th access
339 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 figure 7-27 access to address 4n + 2 figure 7-28 access to address 4n + 3 7 0 7 0 word data external data bus address 15 8 4n + 2 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 1-st access 2-nd access 3-rd access 4-th access 7 0 7 0 word data external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 6 address 15 8 23 16 31 24 1-st access 2-nd access 3-rd access 4-th access
340 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 (b) big endian figure 7-29 access to address 4n figure 7-30 access to address 4n + 1 7 0 7 0 word data external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n address 15 8 23 16 31 24 1-st access 2-nd access 3-rd access 4-th access 7 0 7 0 word data external data bus address 15 8 4n + 4 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24 1-st access 2-nd access 3-rd access 4-th access
341 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 figure 7-31 access to address 4n + 2 figure 7-32 access to address 4n + 3 7 0 7 0 word data external data bus address 15 8 4n + 5 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 1-st access 2-nd access 3-rd access 4-th access 7 0 7 0 word data external data bus address 15 8 4n + 6 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 1-st access 2-nd access 3-rd access 4-th access
342 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 7.8.2 access to 16-bit data busses this section shows how byte, half word and word accesses are performed for a 16 bit data bus. access all data in order starting from the lower order side. (1) byte access (8 bits) (a) little endian figure 7-33 left: access to even address (2n) right: access odd address (2n + 1) (b) big endian figure 7-34 left: access to even address (2n) right: access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 byte data 15 8 external data bus 2n + 1 address 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 byte data 15 8 external data bus 2n + 1 address
343 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 (2) halfword access (16 bits) (a) little endian figure 7-35 left: access to even address (2n) right: access to odd address (2n + 1) (b) big endian figure 7-36 left: access to even address (2n) right: access to odd address (2n + 1) 1-st access 2-nd access 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 2 address 7 0 7 0 halfword data 15 8 external data bus 2n address 15 8 2n + 1 1-st access 2-nd access 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 15 8 2n 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 2 address
344 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 (3) word access (32 bits) (a) little endian figure 7-37 access to address 4n figure 7-38 access to address 4n + 1 7 0 7 0 word data 15 8 external data bus 4n address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 1-st access 2-nd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 23 16 31 24 1-st access 2-nd access 3-rd access
345 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 figure 7-39 access to address 4n + 2 figure 7-40 access to address 4n + 3 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 4n + 5 23 16 31 24 1-st access 2-nd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 4n + 5 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 6 address 15 8 23 16 31 24 1-st access 2-nd access 3-rd access
346 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00 (b) big endian figure 7-41 access to address 4n figure 7-42 access to address 4n + 1 7 0 7 0 word data 15 8 external data bus 4n + 3 address 15 8 4n + 2 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 1 address 15 8 4n 23 16 31 24 1-st access 2-nd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 3 address 15 8 4n + 2 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 23 16 31 24 1-st access 2-nd access 3-rd access
347 bus and memory control (bcu, memc) chapter 7 user?s manual u17566ee5v1um00 figure 7-43 access to address 4n + 2 figure 7-44 access to address 4n + 3 7 0 7 0 word data 15 8 external data bus 4n + 5 address 15 8 4n + 4 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 3 address 15 8 4n + 2 23 16 31 24 1-st access 2-nd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 5 address 15 8 4n + 4 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 6 address 15 8 23 16 31 24 1-st access 2-nd access 3-rd access
348 chapter 7 bus and memory control (bcu, memc) user?s manual u17566ee5v1um00
349 user?s manual u17566ee5v1um00 chapter 8 dma controller (dmac) the microcontroller includes a direct memory access (dma) controller (dmac) that executes and controls dma transfers. note throughout this chapter, the individual channels of the dma controller are identified by ?n?. the dmac controls data transfer between memory and i/o or among i/os, based on dma requests issued by the on-chip peripheral i/o, or software triggers. 8.1 features ? four independent dma channels ? transfer units: 8, 16 and 32 bits ? maximum transfer count: 65536 (2 16 ) ? two transfer modes independently selectable for each dma channel ? single transfer mode ? block transfer mode ? transfer requests ? requests by dedicated peripheral interrupts of ? pd70f3421, pd70f3422, pd70f3423: csib0, csib1, uarta0, uarta1, iic0, iic1, tmg0, tmp0, tmp1, tmz0, tmz1, tmz2, adc ? pd70f3424, pd70f3425, pd70f3426a, pd70f3427: csib0?csib2, uarta0, uarta1, iic0, iic1, tmg0, tmp0, tmp1, tmz0, tmz1, tmz2, lcdif, adc ? requests by software trigger ? transfer objects source \ destination internal ram vsb flash (pd70f3426a) vsb ram (pd70f3426a) external memory (pd70f3427) peripherals internal ram ?  vsb flash (pd70f3426a) ?? ? ?? vsb ram (pd70f3426a)   ?  external memory (pd70f3427)  ??  peripherals 
350 chapter 8 dma controller (dmac) user?s manual u17566ee5v1um00 caution special care must be taken when using the internal ram as dma source or destination. refer to ?simultaneous program execution and dma transfer with internal ram? on page 374 . ? dma transfer completion flag ? automatic restart function ? forcible dma termination by nmi
351 dma controller (dmac) chapter 8 user?s manual u17566ee5v1um00 8.2 peripheral and cpu clock settings in order to ensure safe capture of dma trigger signals from the involved peripheral functions, a certain minimum relation between the operation clock of the concerned peripheral function and the cpu system has to be regarded. in the following table the minimum cpu system clock frequency f vbclk is given for all peripheral functions operation clocks. table 8-1 peripheral functions and cpu system clocks for dma transfers (1/2) peripheral clock controller settings spclkn, pclkn configuration input clock [mhz] minimum f vbclk [mhz] peripheral clock source adc scc = 00 h spclk0 mainosc 4 6.00 scc = 01 h pll/2 16 24.00 scc= 03 h scps.spsps[2:0] = 011 b sscg: 64 mhz f sscgps 16 24.00 scc = 03 h scps.spsps[2:0] = 011 b sscg: 48 mhz f sscgps 12 18.00 uarta ckc.peric = 0 pclk1 mainosc 4 6.00 ckc.peric = 1 pll/4 8 12.00 pclk2 mainosc 4 6.00 pclk3 mainosc/2 2 3.00 pclk4 mainosc/4 1 1.5 pclk5 mainosc/8 0.5 0.75 pclk6 mainosc/16 0.25 0.38 pclk7 mainosc/32 0.125 0.19 pclk8 mainosc/64 0.0625 0.09 csib ckc.peric = 0 pclk1 mainosc 4 6.00 ckc.peric = 1 pll/4 8 12.00 pclk2 mainosc 4 6.00 pclk3 mainosc/2 2 3.00 pclk4 mainosc/4 1 1.50 pclk5 mainosc/8 0.5 0.75 pclk6 mainosc/16 0.250 0.38 scc = 00 h spclk1 via baud rate generator mainosc max. 4 min. 0.002 6.00 0.003 scc = 01 h pll/4 max. 8 min. 0.002 12.00 0.003 scc = 03 h scps.spsps[2:0] = 011 b sscg: 64 mhz f sscgps /2 max. 8 min. 0.002 12.00 0.003 scc = 03 h scps.spsps[2:0] = 011 b sscg: 48 mhz f sscgps /2 max. 8 min. 0.002 12.00 0.003
352 chapter 8 dma controller (dmac) user?s manual u17566ee5v1um00 iic icc = 00 h iiclk mainosc 4 6.00 icc = 72 h pll / 4.5 7.11 10.67 icc = 71 h , sscg: 64 mhz (sscg/2) / 4.5 7.11 10.67 icc = 51 h , sscg: 48 mhz (sscg/2) / 3.5 6.86 10.29 tmz all settings pclk1 mainosc 4 6.00 tmp ckc.peric = 0 pclk0 mainosc 4 6.00 1 pll/2 16 24.00 tmg scc = 00 h spclk0 mainosc 4 6.00 scc = 01 h pll/2 16 24.00 scc = 03 h scps.spsps[2:0] = 011 b sscg: 64 mhz f sscgps 16 24.00 scc = 03 h scps.spsps[2:0] = 011 b sscg: 48 mhz f sscgps 12 18.00 lcdif scc = 00 h spclk0 mainosc 4 6.00 spclk1 mainosc 4 6.00 spclk2 mainosc 4 6.00 spclk5 mainosc/ 0.5 0.75 scc = 01 h spclk0 pll/2 16 24.00 spclk1 pll/4 8 12.00 spclk2 mainosc 4 6.00 spclk5 mainosc/ 0.5 0.75 scc = 03 h scps.spsps[2:0] = 011 b sscg: 64 mhz spclk0 f sscgps 16 24.00 spclk1 f sscgps /2 8 12.00 spclk2 f sscgps /4 4 6.00 spclk5 f sscgps /32 0.5 0.75 scc = 03 h scps.spsps[2:0] = 011 b sscg: 48 mhz spclk0 f sscgps 12 18.00 spclk1 f sscgps /2 6 9 spclk2 f sscgps /4 3 4.50 spclk5 f sscgps /32 0.375 0.56 table 8-1 peripheral functions and cpu system clocks for dma transfers (2/2) peripheral clock controller settings spclkn, pclkn configuration input clock [mhz] minimum f vbclk [mhz] peripheral clock source
353 dma controller (dmac) chapter 8 user?s manual u17566ee5v1um00 8.3 dmac registers 8.3.1 dma source address registers these registers are used to set the dma source addresses (28 bits each) for dma channel n. they are divided into two 16-bit registers, dsahn and dsaln. since these registers are configured as 2-stage fifo buffer registers, a new source address for dma transfer can be specified during dma transfer (refer to ?automatic restart function? on page 366 ). caution dma transfers of misaligned 16-bit/32-bit data is not supported. (1) dsahn - dma source address registers hn access these registers can be read/written in 16-bit units. address dsah0: ffff f082 h dsah1: ffff f08a h dsah2: ffff f092 h dsah3: ffff f09a h initial value undefined 1514131211109876543210 ir 0 0 0 sa27 sa26 sa25 sa24 sa23 sa2 2 sa21 sa20 sa19 sa18 sa17 sa16 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 8-2 dsahn register contents bit position bit name function 15 ir specifies the dma source address. 0: external memory or on-chip peripheral i/o 1: internal ram 11 to 0 sa27 to sa16 sets the dma source addresses (a27 to a16). during dma transfer, it stores the next dma transfer source address.
354 chapter 8 dma controller (dmac) user?s manual u17566ee5v1um00 (2) dsaln - dma source address registers ln access these registers can be read/written in 16-bit units. address dsal0: ffff f080 h dsal1: ffff f088 h dsal2: ffff f090 h dsal3: ffff f098 h initial value undefined 1514131211109876543210 sa15 sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 8-3 dsaln register contents bit position bit name function 15 to 0 sa15 to sa0 sets the dma source address (a15 to a0). during dma transfer, it stores the next dma transfer source address.
355 dma controller (dmac) chapter 8 user?s manual u17566ee5v1um00 8.3.2 dma destination address registers these registers are used to set the dma destination address (28 bits each) for dma channel n. they are divided into two 16-bit registers, ddahn and ddaln. since these registers are configured as 2-stage fifo buffer registers, a new destination address for dma transfer can be specified during dma transfer (refer to ?automatic restart function? on page 366 ). caution dma transfers of misaligned 16-bit/32-bit data is not supported. (1) ddahn - dma destination address registers hn access these registers can be read/written in 16-bit units. address ddah0: ffff f086 h ddah1: ffff f08e h ddah2: ffff f096 h ddah3: ffff f09e h initial value undefined 1514131211109876543210 ir 0 0 0 da27 da26 da25 da24 da23 da22 da21 da20 da19 da18 da17 da16 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 8-4 ddahn register contents bit position bit name function 15 ir specifies the dma destination address. 0: external memory or on-chip peripheral i/o 1: internal ram 11 to 0 da27 to da16 sets the dma destination addresses (a27 to a16). during dma transfer, it stores the next dma transfer destination address.
356 chapter 8 dma controller (dmac) user?s manual u17566ee5v1um00 (2) ddaln - dma destination address registers ln access these registers can be read/written in 16-bit units. address ddal0: ffff f084 h ddal1: ffff f08c h ddal2: ffff f094 h ddal3: ffff f09c h initial value undefined 1514131211109876543210 da15 da14 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 8-5 ddaln regsiter contents bit position bit name function 15 to 0 da15 to da0 sets the dma destination address (a15 to a0). during dma transfer, it stores the next dma transfer destination address.
357 dma controller (dmac) chapter 8 user?s manual u17566ee5v1um00 8.3.3 dbcn - dma transfer count registers these 16-bit registers are used to set the transfer counts for dma channels n. they store the remaining transfer counts during dma transfer. since these registers are configured as 2-stage fifo buffer registers, a new dma transfer count for dma transfer can be specified during dma transfer (refer to ?automatic restart function? on page 366 ). during dma transfer these registers are decremented by 1 for each transfer that is performed. dma transfer is terminated when an underflow occurs (from 0 to ffffh). on terminal count these registers are rewritten with the value that was set to the dbcn master register before. access these registers can be read/written in 16-bit units. address dbc0: ffff f0c0 h dbc1: ffff f0c2 h dbc2: ffff f0c4 h dbc3: ffff f0c6 h initial value undefined 1514131211109876543210 bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 b2c bc1 bc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 8-6 dbcn register contents bit position bit name function 15 to 0 bc15 to bc0 sets the transfer count. it stores the remaining transfer count during dma transfer. dbcn states 0000h transfer count 1 or remaining transfer count 0001h transfer count 2 or remaining transfer count :: ffffh transfer count 65,536 (2 16 ) or remaining transfer count
358 chapter 8 dma controller (dmac) user?s manual u17566ee5v1um00 8.3.4 dadcn - dma addres sing control registers these 16-bit registers are used to control the dma transfer modes for dma channel n. access these registers can be read/written in 16-bit units. address dadc0: ffff f0d0 h dadc1: ffff f0d2 h dadc2: ffff f0d4 h dadc3: ffff f0d6 h initial value 0000 h 1514131211109876543210 ds1 ds0 0 0 0 0 0 0 sad1 sad0 dad1 dad0 tm1 tm0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 8-7 dadcn register contents bit position bit name function 15, 14 ds1, ds0 sets the transfer data size for dma transfer. ds1 ds0 transfer data size 008 bits 0 1 16 bits 1 0 32 bits 1 1 setting prohibited for the peripheral i/o and programmable peripheral i/o registers, ensure the transfer size matches the access size. 7, 6 sad1, sad0 sets the count direction of the source address for dma channel n. sad1 sad0 count direction 0 0 increment 0 1 decrement 10fixed 1 1 setting prohibited 5, 4 dad1, dad0 sets the count direction of the destination address for dma channel n. dad1 dad0 count direction 0 0 increment 0 1 decrement 10fixed 1 1 setting prohibited 3, 2 tm1, tm0 sets the transfer mode during dma transfer. tm1 tm0 transfer mode 0 0 single transfer mode 0 1 setting prohibited 1 0 setting prohibited 1 1 block transfer mode
359 dma controller (dmac) chapter 8 user?s manual u17566ee5v1um00 caution these registers cannot be accessed during dma operation.
360 chapter 8 dma controller (dmac) user?s manual u17566ee5v1um00 8.3.5 dchcn - dma channel control registers these 8-bit registers are used to control the dma transfer operating mode for dma channel n. access these registers can be read/written in 8-bit or 1-bit units. (however, bit 7 is read only and bits 2 and 1 are write only. if bits 2 and 1 are read, the read value is always 0.) address dchc0: ffff f0e0 h dchc1: ffff f0e2 h dchc2: ffff f0e4 h dchc3: ffff f0e6 h initial value 00 h 76543210 tcn 0 0 0 mlen initn stgn enn r/w r/w r/w r/w r/w r/w r/w r/w table 8-8 dchcn register contents bit position bit name function 7 tcn the terminal count status bit tc indicates whether dma transfer through dma channel n has ended or not. it is read-only, and is set to 1 when dma transfer ends and cleared (0) when it is read. 0: dma transfer had not ended. 1: dma transfer had ended. 3 mlen when the multi link enable bit mle is set to 1 at terminal count output, the enn bit is not cleared to 0 and the dma transfer enable state is retained (refer to ?automatic restart function? on page 366 ). moreover, the next dma transfer request can be accepted even when the tcn bit is not read, that means it is not cleared. when this bit is cleared to 0 at terminal count output, the enn bit is cleared to 0 and the dma transfer disable state is entered. at the next dma request, the setting of the enn bit to 1 and the reading of the tcn bit are required. 2 initn when this bit is set to 1, dma transfer is forcibly terminated. 1 stgn if this bit is set to 1 in the dma transfer enable state (tcn bit = 0, enn bit = 1), dma transfer is started. 0 enn specifies whether dma transfer through dma channel n is to be enabled or disabled. 0: dma transfer disabled 1: dma transfer enabled if mlen=0, this bit is cleared to 0 when dma transfer ends. if mlen=1, this bit is not cleared and the next dma transfer is automatically restarted (refer to ?automatic restart function? on page 366 ). this bit is also cleared to 0 when dma transfer is forcibly terminated by means of setting the initn bit to 1 or by nmi input.
361 dma controller (dmac) chapter 8 user?s manual u17566ee5v1um00 8.3.6 drst - dma restart register the enn bit of this register and the enn bit of the dchcn register are linked to each other. this provides a fast way to check the status of all dma channels. access this register can be read/written in 8-bit or 1-bit units. address ffff f0f2 h initial value 00 h 76543210 0000en3en2en1en0 r/w r/w r/w r/w r/w r/w r/w r/w table 8-9 drst register contents bit position bit name function 3 to 0 en3 to en0 specifies whether dma transfer through dma channel n is to be enabled or disabled. this bit is cleared to 0 when dma transfer is completed in accordance with the terminal count output. it is also cleared to 0 when dma transfer is forcibly terminated by setting the initn bit to 1 or by nmi input. 0: dma transfer disabled 1: dma transfer enabled
362 chapter 8 dma controller (dmac) user?s manual u17566ee5v1um00 8.3.7 dtfrn - dma trigger source select register the 8-bit dma trigger source selection registers are used to control the dma transfer triggers for the individual dma channels. these triggers initiate dma transfer requests received from built-in peripheral hardware. interrupt signals are used as dma transfer requests. access this register can be read/written in 8-bit or 1-bit units. address dtfr0: ffff fe00 h dtfr1: ffff fe02 h dtfr2: ffff fe04 h dtfr3: ffff fe06 h initial value 00 h note drqn and dofln are set by hardware. drqn and dofln can be reset by software. setting these bits by software is not possible. a ?0? must be written to the respective bit location to reset these bits. the bits dtfrn.ifcn[2:0] select the interrupts to be used as dma trigger sources according to the following table : caution if the dma trigger source is changed by modifying dtfrn.ifcn[2:0] bits while dma channel n is active, a dma request may be set accidentally. proceed in any of the two ways when changing the dma trigger source: 1. disable the dma channel n by dchcn.enn = 0 before changing the dma trigger source dtfrn.ifcn[2:0]. 76543210 drqn dofln dmactn 0 a a) the default value ?0? of this bit must not be changed! 0 a ifcn2 ifcn1 ifcn0 r/w r/w note r/w note r/w r/w r/w r/w r/w n 0 1 2 3 ifcn2 ifcn1 ifcn0 channel 0 channel 1 channel 2 channel 3 0 0 0 intcb1r intcb2r a a) pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only intcb1r intcb2r a 0 0 1 intcb1t intcb2t a intcb1t intcb2t a 0 1 0 intcb0r intcb0t intcb0r intcb0t 0 1 1 intua0r intua0r intua0t intua0t 1 0 0 intua1r intua1r intua1t intua1t 1 0 1 inttz0uv inttz0uv inttz1uv inttz2uv 1 1 0 intiic0 intlcd intiic1 intlcd 1 1 1 inttp0cc1 inttp1cc1 inttg0cc1 intad
363 dma controller (dmac) chapter 8 user?s manual u17566ee5v1um00 2. set the dma request bit dtfrn.drqn = 0 in parallel to changing dtfrn.ifcn[2:0], i.e. within the same write operation. thus dtfrn must be written in 8-bit access mode. do not change dtfrn.ifcn[2:0] with single-bit instructions. the following list details the functions of the individual dma trigger sources referenced in the above table. ? intcb2r...intcb0r the receive interrupts of the clocked serial interfaces csib2?csib0 are used as dma trigger sources. in case of a receive overflow condition no dma trigger will be issued. the receive error interrupt of the respective csib intcbnre should be enabled to inform the application software about the overflow condition. ? intcb2t?intcb0t the transmit interrupts of the clocked serial interfaces csib2?csib0 are used as dma trigger sources. ?intua1r, intua0r the receive interrupts of the asynchronous serial interfaces uarta1 or uarta0 are used as dma trigger sources. in case of a receive overflow, or a framing or parity error condition, no dma trigger will be issued. the receive error interrupt intuanre of the respective uartn should be enabled to inform the application software about the error condition. these interrupts are also generated upon reception of an sbf in lin mode. ? intua1t, intua0t the transmit interrupts of the asynchronous serial interfaces uarta1 or uarta0 are used as dma trigger sources. ?intlcd the interrupt signal of the lcd bus interface macro is used to trigger the dma transfer. ? intiic0, intiic1 the interrupts of the i 2 c interfaces iic0, iic1 are used to trigger the respective dma channel. note for more information concerning correct handling of drqn and dofln during dma initialization and retrigger refer to ?dma setup and retrigger? on page 365 . drqn dma request 0 no dma transfer request is pending for channel n 1 dma transfer request is pending for channel n dofln dma request overflow 0 dma transfer request overflow did not occur for channel n 1 dma transfer request overflow occurred for channel n
364 chapter 8 dma controller (dmac) user?s manual u17566ee5v1um00 set dmactn according to the following table: caution special care must be taken when using the internal ram as dma source or destination. refer to ?simultaneous program execution and dma transfer with internal ram? on page 374 . dmactn dma active count 0 dmactn=0 must be set if internal ram is not specified as source or destination 1 dmactn=1 must be set if internal ram is specified as source or destination source \ destination internal ram vsb flash (pd70f3426a) vsb ram (pd70f3426a) external memory (pd70f3427) peripherals internal ram ?  vsb flash (pd70f3426a) ?? ? ?? vsb ram (pd70f3426a)   ?  external memory (pd70f3427)  ??  peripherals 
365 dma controller (dmac) chapter 8 user?s manual u17566ee5v1um00 8.4 dma setup and retrigger the following describes the correct initial dma setup and the process for retriggering the dma process. 8.4.1 dma initial setup (status after system reset) 1. disable dma interrupts intdman in interrupt control registers by setting dmanic.dmanmk = 1. 2. configure dma source address register dsahn and set bit dsahn.ir = 1 if the dma source address is located inside the internal ram area. 3. configure dma source address register dsaln. 4. configure dma destination address register ddahn and set bit ddahn.ir = 1 if the dma destination address is located inside the internal ram area. 5. configure dma destination address register ddaln. 6. configure dma transfer count register dbcn. 7. select transfer data size, count direction of the source address, count direction of the destination address and transfer mode by setting dsn, dadn, sadn and tmn of dadcn. 8. select whether target and/or destination addresses are ram-located, select dma transfer complete mode and select trigger source by setting dmactn, tcomoden and ifcn of dtfrn. 9. always clear the drqn and dofln flags of dtfrn register regardless if these are already cleared or not. 10. clear dma interrupt requests in interrupt control registers by setting dmanic.dmanif = 0. 11. enable the dma transfer by setting dchcn.enn = 1 or the respective bit of the drst register. 12. dman transfer is then triggered either by request from the respective peripheral or by setting the software trigger bit dchcn.stgn = 1. if software trigger is used, steps 11 and 12 can be done simultanously by setting dchcn = 03 h . 8.4.2 dma retrigger 1. disable dma interrupts intdman in interrupt control registers by setting dmanic.dmanmk = 1. 2. read tcn of dchcn to clear it. 3. always clear the drqn and dofln flags of dtfrn register regardless if these are already cleared or not. 4. clear dma interrupt requests in interrupt control registers dmanic (n=0..3). 5. enable the dma transfer by setting dchcn.enn or the respective bit of the drst registers. 6. dman transfer is triggered either by request from the respective peripheral or by setting the software trigger bit dchcn.stgn = 1. if software trigger is used, steps 5 and 6 can be done simultaneously by setting dchcn = 0x03.
366 chapter 8 dma controller (dmac) user?s manual u17566ee5v1um00 8.5 automatic restart function the dma source address registers (dsahn, dsaln), dma destination address registers (ddahn, ddaln), and dma transfer count register (dbcn) are buffer registers with a 2-stage fifo structure, named master and slave register. the setup data of the slave registers is always used for the current dma transfer, while the master registers may hold a new setup to be used automatically after the first dma transfer has completed. when the terminal count dchcn.tcn=1 is issued, the slave registers are automatically rewritten with the values of the master registers. therefore, during dma transfer, transfer is automatically started when a new dma transfer setting is made for these registers and the mlen bit of the dchcn register is set (however, the dma transfer end interrupt is issued even if dma transfer is automatically started). this mode is called multi link mode and is configured by dchcn.mlen=1. if dma channel n is disabled (dchcn.enn=0), writing to dsah/ln, ddah/ln, dbcn stores the data to the master and slave registers. writing the next dma transfer setup data to the master registers only - and to keep the first setup data in the slave registers - is possible after ? the dma channel n has been enabled (dchcn.enn=1) and ? the first dma trigger interrupt for channel n has occurred. the new setup data will become effective after ? the previous dma transfer has completed (dchc.tcn=1, intdman) and ? the next following dma trigger interrupt for channel n has occurred. note that the terminal count flag dchc.tcn does not need to be cleared in multi link mode (dchc.mlen = 1) for starting up the next dma transfer automatically. figure 8-1 shows the configuration of the buffer register. figure 8-1 buffer register configuration caution dma transfer with activated mle function can only be used in conjunction with hardware requests. therefore it is not allowed to start a dma transfer by software trigger (dchcn.stg n) when dchcn.mlen is set. data read data write master register slave register address/ count controller internal bus
367 dma controller (dmac) chapter 8 user?s manual u17566ee5v1um00 8.6 transfer type all dma transfers of this microcontroller are two-cycle transfers. in two-cycle transfer, data transfer is performed in two cycles: a read cycle (source to dmac) and a write cycle (dmac to destination). in the first cycle, the source address is output and reading is performed from the source to the dmac. in the second cycle, the transfer destination address is output and writing is performed from the dmac to the transfer destination. 8.7 transfer object the following transfer objects can be specified as source and destination: table 8-10 transfer objects source \ destination internal ram peripherals internal ram ?  peripherals 
368 chapter 8 dma controller (dmac) user?s manual u17566ee5v1um00 8.8 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > ? > dma channel n in the single-step transfer mode, the dma controller releases the buses after each byte/half-word/word transfer. if a higher priority dma transfer request is issued while the bus is released, the higher priority dma transfer request is acknowledged. in the block transfer mode, the channel used for transfer is never switched. 8.9 dma transfer start factors there are two types of dma transfer start factors, as shown below. (1) request from on-chip peripheral i/o if the enn and the tcn bits of the dchcn register are set as shown below, and an interrupt request is issued from the on-chip peripheral i/o that is set in the dtfrn register, the dma transfer starts. ? enn bit = 1 ? tcn bit = 0 (2) request from software if the stgn, the enn and the tcn bits of the dchcn register are set as follows, the dma transfer starts. ?stgn bit = 1 ? enn bit = 1 ? tcn bit = 0 note for more information concerning correct dma initialization and retrigger refer to ?dma setup and retrigger? on page 365 . 8.10 forcible interruption dma transfer can be forcibly interrupted by nmi input during dma transfer. at such a time, the dmac clears the enn bit of the dchcn register of all channels and the dma transfer disabled state is entered. an nmi request can then be acknowledged after the dma transfer executed during nmi input is terminated. in block transfer mode, the dma transfer request is held in the dmac. if the enn bit is set back to "1", the dma transfer is resumed from the point where it was interrupted.
369 dma controller (dmac) chapter 8 user?s manual u17566ee5v1um00 in the single transfer mode, if the enn bit is set back to "1", the next dma transfer request is acknowledged and dma transfer is resumed. figure 8-2 example of forcible interruption of dma transfer caution the resumed dma transfer after nmi interruption cannot be executed with new settings. new settings for a dma transfer can be validated either after the end of the current transfer or after the transfer has been forcibly terminated by setting the initn bit of the dchcn register. 8.11 forcible termination in addition to the forcible interruption operation by means of the nmi input, dma transfer can be forcibly terminated by the initn bit of the dchcn register. the following is an example of the operation of a forcible termination. figure 8-3 shows a block transfer of channel 3 which begins during the dma block transfer of dma channel 2. the block transfer of dma channel 2 is forcibly terminated by setting the init2 bit of its dchc2 control register. dma transfer stop dma transfer dma transfer dma transfer stop en0 bit of dchc0 register nmi (input) forcible interruption forcible interruption transfer restart
370 chapter 8 dma controller (dmac) user?s manual u17566ee5v1um00 figure 8-3 dma transfer forcible termination example 1 note the next condition can be set even during dma transfer because the dsan, ddan, and dbcn registers are buffered registers. however, the setting to the dadcn register is invalid (refer to ?automatic restart function? on page 366 and ?dadcn - dma addressing control registers? on page 358 ). figure 8-4 shows a forcible termination of a block transfer operation of dma channel 1. a transfer containing a new configuration is executed. figure 8-4 dma transfer forcible termination example 2 note since the dsaln, dsahn, ddaln, ddahn and dbcn registers are buffered registers, the next transfer condition can be set even during a dma transfer. however, a setting in the dadcn register is ignored (refer to ?automatic restart function? on page 366 ) dma transfer request ch2 dma transfer request ch3 cpu dma3 dma3 dma3 dma3 cpu cpu cpu cpu cpu dma2 dma2 dma2 dma2 dma2 cpu cpu en3 bit = 1 tc3 bit = 0 en3 bit 0 tc3 bit 1 set register en2 bit = 1 tc2 bit = 0 set register set register en2 bit 0 tc2 bit = 0 dma channel 3 terminal count dma channel 3 transfer begins dma channel 2 transfer is forcibly terminated and the bus is released dsal2, dsah2, ddal2, ddah2 dsal3, dsah3, ddal3, ddah3 dchc2 (init2 bit = 1)    dma transfer request ch1 dsal1, dsah1, ddal1, ddah1 dchc1 (init1 bit = 1)    dma1 cpu cpu cpu cpu dma1 cpu cpu cpu cpu dma1 dma1 dma1 dma1 dma1 dma1 dma1 dma channel 1 terminal count dma channel 1 transfer is forcibly terminated and the bus is released en1 bit = 1 tc1 bit = 0 en1 bit 0 tc1 bit 1 set register cpu set register set register set register en1 bit 0 tc1 bit = 0 en1 bit 1 tc1 bit = 0 dsal1, dsah1, ddal1, ddah1 dadc1, dchc1 
371 dma controller (dmac) chapter 8 user?s manual u17566ee5v1um00 8.12 dma transfer completion when dma transfer ends and the tcn bit of the dchcn register is set, a dma transfer end interrupt (intdman) is issued to the interrupt controller (intc). 8.13 transfer mode 8.13.1 single transfer mode in single transfer mode, the dmac releases the bus after each byte/halfword/ word transfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher priority dma transfer request is issued, the higher priority dma request always takes precedence. however, if a lower priority dma transfer request is generated within one clock after the end of a single transfer, even if the previous higher priority dma transfer request signal stays active, this request is not prioritized and the next dma transfer after the bus is released for the cpu is a transfer based on the newly generated, lower priority dma transfer request. figure 8-5 shows a dmac transfer in single transfer mode. in this example the dma channel 3 is used for a single transfer. figure 8-5 single transfer example 1 note the bus is always released cpu dma3 cpu cpu dma3 cpu cpu cpu cpu cpu dma3 cpu dma3 dma3 cpu cpu cpu cpu cpu dma channel 3 terminal count note note note note dma transfer request ch3
372 chapter 8 dma controller (dmac) user?s manual u17566ee5v1um00 figure 8-6 shows dmac transfers in single transfer mode in which a higher priority dma transfer request is generated. dma channels 0 to 2 are used for a block transfer and channel 3 is used for a single transfer. figure 8-6 single transfer example 2 note the bus is always released figure 8-7 shows a dma transfer example in single transfer mode in which a lower priority dma transfer request is generated within one clock after the end of a single transfer. dma channels 0 and 3 are used for the single transfer example. when two dma transfer request signals are activated at the same time, the two dma transfers are performed alternately. figure 8-7 single transfer example 3 note the bus is always released dma transfer request ch0 dma1 dma2 cpu dma2 cpu dma3 cpu cpu cpu dma3 cpu dma0 dma0 cpu dma1 cpu dma3 note note note note dma transfer request ch1 dma transfer request ch2 dma transfer request ch3 dma channel 0 terminal count dma channel 1 terminal count dma channel 2 terminal count dma channel 3 terminal count dma transfer request ch0 dma transfer request ch3 dma channel 0 terminal count dma channel 3 terminal count cpu cpu dma3 dma0 cpu dma0 cpu cpu cpu cpu dma0 cpu dma0 dma3 cpu cpu dma0 cpu dma0 note note note note note note note
373 dma controller (dmac) chapter 8 user?s manual u17566ee5v1um00 figure 8-8 shows a single transfer mode example in which two or more lower priority dma transfer requests are generated within one clock after the end of a single transfer. dma channels 0, 2 and 3 are used for this single transfer example. when three or more dma transfer request signals are activated at the same time always the two highest priority dma transfers are performed alternately. figure 8-8 single transfer example 4 note the bus is always released 8.13.2 block transfer mode in the block transfer mode, once transfer begins, the dmac continues the transfer operation without releasing the bus until a terminal count occurs. no other dma requests are acknowledged during block transfer. after the block transfer ends and the dmac releases the bus and another dma transfer can be acknowledged. figure 8-9 shows a block transfer mode example. it is a block transfer mode example in which a higher priority dma transfer request is generated. dma channels 2 and 3 are used for the block transfer example. figure 8-9 block transfer example dma2 cpu dma3 cpu cpu dma3 cpu cpu dma2 dma0 cpu dma0 note note note note note dma2 cpu note dma3 cpu dma2 cpu cpu dma3 note cpu cpu note note dma transfer request ch0 dma transfer request ch2 dma transfer request ch3 dma channel 0 terminal count dma channel 2 terminal count dma channel 3 terminal count dma transfer request ch2 dma transfer request ch3 dma channel 3 terminal count dma3 cpu dma3 dma2 dma2 dma2 cpu cpu cpu dma3 dma3 dma3 dma3 dma3 dma3 dma2 dma2 the bus is always released
374 chapter 8 dma controller (dmac) user?s manual u17566ee5v1um00 8.14 cautions 8.14.1 simultaneous program exec ution and dma transfer with internal ram (1) details when a dma transfer with the internal ram as source or destination and one of the following instructions are fetched from the internal ram and executed, the cpu may deadlock: ?? bit manipulation instructions (set1, clr1, or not1) on any target data (ram, sfr, etc) ? - instructions with misaligned access to data in the internal ram misaligned access means ? access to 32-bit (word) data on addresses with lower 2 address bits unequal 0 ? access to 16-bit (half-word) data on addresses with lowest address bit unequal 0 once the cpu has entered this deadlock state only a reset can be acknowledged, neither maskable nor non-maskable interrupts will be acknowledged anymore. this situation does not occur if no instruction is fetched from the internal ram, or no dma transfer is performed on the internal ram. (2) workaround implement any of the following workarounds: ? do not perform any dma transfers with the internal ram when an instruction allocated in the internal ram is being executed. ? do not execute an instruction allocated in the internal ram when a dma transfer with the internal ram is being performed. ? disable dma transfer when the cpu is executing instruction code that is allocated in the internal ram. ? do not use either a bit manipulation instruction or a misaligned memory access.
375 user?s manual u17566ee5v1um00 chapter 9 rom correction function (romc) this microcontroller features following rom correction facilities: ? ?data replacement? rom correction: ? 1 x 6 channels for vfb flash memory and rom the individual channels of each ?data replacement? rom correction are identified by ?n? (n = 0 to 5) ? ?dbtrap? rom correction: ? 1x 8 channels for vfb flash memory ? 1 x 8 channels for vsb flash memory (for pd70f3426a only) the individual channels of each ?dbtrap? rom correction are identified by ?m? (m = 0 to 7) caution during self-programming make sure to disable all rom correction facilities, as enabled rom corrections may conflict with the internal firmware. 9.1 overview the rom correction function is used to replace part of the internal flash memory with user defined data. by using this function, program bugs found in the internal flash memory can be corrected. the ?dbtrap? rom correction unit substitutes an instruction fetched from flash memory by the dbtrap instruction. thus a dbtrap exception is excited and program execution branches to the dbtrap vector 0000 0060 h . note that the ?dbtrap? rom correction unit is utilized by the n-wire on-chip debug unit. therefore rom corrections by dbtrap are not available, when n- wire on-chip debugging is performed.
376 chapter 9 rom correction function (romc) user?s manual u17566ee5v1um00 9.2 ?data replacement? rom correction unit 9.2.1 features ? 6 correction channels for vfb flash/rom (n = 0 to 5) ? programmable correction address for each channel ? programmable correction value for each channel (the value can be an instructions as well as data) ? correction of aligned and unaligned instructions/data ? correction of halfwords and words ? enable/disable of each channel individually by software figure 9-1 ?data replacement? rom correction block diagram vfb a ddre ss bus vfb d a t a bus correction a ddre ss regi s ter coradrn corctl0.corenn comp a r a tor rom/fl as h corctl1.hwn corval - rom/fl as h d a t a repl a cement rom/fl as h d a t a correction v a l u e regi s ter corvaln
377 rom correction function (romc) chapter 9 user?s manual u17566ee5v1um00 9.2.2 ?data replacement? rom correction operation the ?data replacement? rom correction unit compares the address on the v850 fetch bus (vfb) with the contents of the programmable correction address registers coradrn. if an address matches, a programmable value (instructions or data) is put on the v850 fetch bus instead of the rom contents. if no address matches, the rom contents is passed on the fetch bus as normal. the v850e architecture supports 16-bit as well as 32-bit instructions/data with support of aligned and unaligned instruction/data placement. figure 9-2 shows the different alignments of code/data inside the rom. figure 9-2 alignment of instructions and data in the internal rom/flash (a) 32-bit word aligned data replacement the 32-bit wide code/data is aligned to a word boundary. upper and lower halfword are replaced directly by the 32-bit correction value. figure 9-3 32-bit word aligned data replacement 0 0 0 0 22 4 4 4 4 8 8 8 8 addr addr ( a ) (c) ( b ) (d) addr addr in s tr 3 2_hi in s tr16 in s tr16 in s tr 3 2_lo in s tr 3 2_hi in s tr 3 2_lo 22 0 4 8 addr corvaln coradrn 0x00 1000 0x00 1000 0xdddd 0xdddd 0xbbbb 0xcccc 0xcccc d a t a on vfb addre ss on vfb addre ss m a tch ! rom content 0xaaaa intern a l a ddre ss c a lc u l a tor 0x00 1000 coradrn &0x 3 f fffc coradrn + 0x00 0002 0x00 1002 hwn corenn 1 0
378 chapter 9 rom correction function (romc) user?s manual u17566ee5v1um00 (b) 32-bit word unaligned data replacement the 32-bit wide code/data is not aligned to a word boundary. for the first vfb access the upper half word is replaced by the lower 16-bit of the correction value (refer to figure 9-4 (a)). for the second vfb access the lower halfword is replaced by the upper 16-bit of the correction value (refer to figure 9-4 (b)). figure 9-4 32-bit word unaligned data replacement 0 0 2 2 4 4 8 8 ( a ) ( b ) addr addr corvaln corvaln coradrn coradrn intern a l a ddre ss c a lc u l a tor intern a l a ddre ss c a lc u l a tor 0x00 1002 0x00 1002 0x00 1000 0x00 1000 coradrn &0x 3 f fffc coradrn &0x 3 f fffc coradrn + 0x00 0002 coradrn + 0x00 0002 0x00 1004 0x00 1004 0x00 1004 0x00 1000 0xdddd 0xdddd 0xcccc 0xbbbb 0xbbbb 0xcccc 0xcccc 0xdddd d a t a on vfb d a t a on vfb addre ss on vfb addre ss on vfb addre ss m a tch ! addre ss m a tch ! rom content rom content 0xaaaa 0xaaaa hwn hwn corenn corenn 1 1 0 0
379 rom correction function (romc) chapter 9 user?s manual u17566ee5v1um00 (c) 16-bit halfword aligned data replacement the 16-bit wide code/data can be replaced directly by the 16-bit correction value. the upper halfword is not replaced but the original rom contents is put on the fetch bus. figure 9-5 16-bit halfword aligned data replacement (d) 16-bit halfword unaligned data replacement the 16-bit wide code/data can be replaced directly by the 16-bit correction value. the lower halfword is not replaced but the original rom contents is put on the fetch bus. figure 9-6 16-bit halfword unaligned data replacement 0 2 4 8 addr corvaln coradrn hwn corenn 1 1 intern a l a ddre ss c a lc u l a tor 0x00 1000 0x00 1000 coradrn &0x 3 f fffc coradrn + 0x00 0002 0x00 1002 0x00 1000 0xcccc 0xcccc d a t a on vfb addre ss on vfb addre ss m a tch ! rom content 0xaaaa 0 2 4 8 addr corvaln coradrn intern a l a ddre ss c a lc u l a tor 0x00 1002 0x00 1000 coradrn &0x 3 f fffc coradrn + 0x00 0002 0x00 1004 0x00 1000 0xdddd 0xbbbb 0xdddd d a t a on vfb addre ss on vfb addre ss m a tch ! rom content hwn corenn 1 1
380 chapter 9 rom correction function (romc) user?s manual u17566ee5v1um00 9.2.3 setting of rom correction addresses the cpu supports access to (32-bit) word and (16-bit) half word aligned and unaligned instructions and data. aligned words have an address with the lowest two address bits equal 00 b , i.e. address modulo 4 = 00 b . any access to the rom is always performed on word aligned addresses. as a consequence access to an unaligned word yields two accesses. the word in figure 9-7 is accessed in two cycles via address 0x00 and 0x04. figure 9-7 unaligned word addressing consequently a rom correction of an unaligned word is also split into two steps (refer to ?32-bit word unaligned data replacement? on page 378 ). caution any (32-bit) aligned word must not contain correction targets of more than one rom correction channel. in case of an unaligned word correction (corctl1.hwn=0), i.e. coradrn mod 4 = 10 b , any part (word or half word) of the following two aligned words must not be specified as any other correction address: ? coradrn div 4 ? (coradrn div 4) + 4 following consequence applies: the correction address of an unaligned word must have a distance of at least 6 byte to all other correction addresses, i.e. coradrn  coradrm + 6. one exception consists in the following case. if an unaligned halfword correction address coradrm (corctl1.hwn = 1) precedes in terms of the addresses an unaligned word correction coradrn (corctl1.hwn = 0), a distance of 4 byte is sufficient: coradrn  coradrm + 4. if the setting of rom correction addresses conflicts with the above, an unaligned word correction shall be split into two halfword corrections. thus also halfwords of different correction words can be combined in order to correct them in a single aligned access cycle. ta b l e 9 - 1 illustrates different combinations and advises how to avoid above conflicts. word_l word_h 0x00 0x04 0x08
381 rom correction function (romc) chapter 9 user?s manual u17566ee5v1um00 table 9-1 rom correction address settings unaligned word and halfword correction hword1 word0_h x100 b word0_l hword0 x000 b combine for 2 aligned corrections coradrn = x000 b coradrm = x100 b corvaln = word0_l << 16 + hword0 corvalm = hword1 << 16 + word0_h halfwords correction hword3 hword2 xx00 b combine for 1 aligned access coradrn = x000 b corvaln = hword3 << 16 + hword2 unaligned words correction no correction target word1_h x100 b word1_l word2_h x100 b word2_l no correction target x000 b combine for 3 aligned corrections coradrn = 0000 b coradrm = 0100 b coradrl = 1000 b corvaln = word1_h corvalm = word1_l << 16 + word2_h corvall = word2_l << 16 isolated unaligned word correction no correction target word0_h x100 b word0_l no correction target x000 b single unaligned correction coradrn = x010 b corvaln = word3_l << 16 + word3_h
382 chapter 9 rom correction function (romc) user?s manual u17566ee5v1um00 9.2.4 ?data replacement? rom correction registers (1) corctl0 - vfb flash/rom ?data replacement? rom correction control register 0 this register enables or disables the ?data replacement? vfb flash/rom rom correction of each channel. access this register can be read/written in 8- and 1-bit units. address ffff f900 h initial value 00 h rom correction of channel n should only be enabled after the correction address (coradrn), the correction value (corvaln) and the word/halfword selection (corctl1) have been set. (2) corctl1 - vfb flash/rom ?data replacement? rom correction control register 1 this register determines whether the word (32-bit) or halfword (16-bit) value of corvaln replaces the vfb flash/rom contents. access this register can be read/written in 8- and 1-bit units. address ffff f901 h initial value 00 h note corctl1.hwn shall only be changed when the corresponding channel is disabled (corctl0.corcenn = 0). 76543210 0 0 corcen5 corcen4 corcen3 corcen2 corcen1 corcen0 r r r/w r/w r/w r/w r/w r/w table 9-2 corctl0 register contents bit position bit name function 5 to 0 corcenn rom correction channel 0: rom correction for channel n disabled 1: rom correction for channel n enabled 76543210 0 0 hw5 hw4 hw3 hw2 hw1 hw0 r r r/w r/w r/w r/w r/w r/w table 9-3 corctl1 register contents bit position bit name function 5 to 0 hwn word - halfword 0: word value of corvaln replaces the flash/ rom contents 1: halfword value of corvaln replaces the flash/ rom contents
383 rom correction function (romc) chapter 9 user?s manual u17566ee5v1um00 (3) coradrnl - vfb flash/rom ?data replacement? rom correction low address register these registers hold the lower 16 bit of the address where the vfb flash/rom rom correction should be performed. access these registers can be read/written in 16- and 8-bit units. address coradr0l, coradr0ll: ffff f910 h coradr0lh: ffff f911 h coradr1l, coradr1ll: ffff f914 h coradr1lh: ffff f915 h coradr2l, coradr2ll: ffff f918 h coradr2lh: ffff f919 h coradr3l, coradr3ll: ffff f91c h coradr3lh: ffff f91d h coradr4l, coradr4ll: ffff f920 h coradr4lh: ffff f921 h coradr5l, coradr5ll: ffff f924 h coradr5lh: ffff f925 h initial value 0000 h note coradrnl shall only be changed when the corresponding channel is disabled (corctl0.corcenn = 0). 1514131211109876543210 coradrn[15:0] 0 r/w table 9-4 coradrnl register contents bit position bit name function 15 to 0 coradrn [15:0] lower 16 bit of the rom correction address of channel n. bit 0 is fixed to 0, writing to this bit is ignored.
384 chapter 9 rom correction function (romc) user?s manual u17566ee5v1um00 (4) coradrnh - vfb flash/rom ?data replacement? rom correction high address register these registers hold the upper 6 bit of the address where the vfb flash/rom rom correction should be performed. access these registers can be read/written in 16- and 8-bit units. address coradr0h, coradr0hl: ffff f912 h coradr0hh: ffff f913 h coradr1h, coradr1hl: ffff f916 h coradr1hh: ffff f917 h coradr2h, coradr2hl: ffff f91a h coradr2hh: ffff f91b h coradr3h, coradr3hl: ffff f91e h coradr3hh: ffff f91f h coradr4h, coradr4hl: ffff f922 h coradr4hh: ffff f923 h coradr5h, coradr5hl: ffff f926 h coradr5hh: ffff f927 h initial value 0000 h caution the rom correction address coradrn[21:0] must not exceed the upper address of the internal vsb rom respectively vsb flash memory. if the internal vsb rom/flash memory size is less than 4 mb the appropriate number of upper address bits of coradrn[21:0] must be set to 0. example: if the internal vsb rom/flash memory size is 1 mb, coradrn[21:20], i.e. bit 5 and 4 of the coradrnh, must be set to 00 b . the allowed address range is 0000 0000 h to 000f ffff h . note coradrnh shall only be changed when the corresponding channel is disabled (corctl0.corcenn = 0). 1514131211109876543210 0000000000 coradrn[21:16] r/w table 9-5 coradrnh register contents bit position bit name function 5 to 0 coradrn [21:16] lower 16 bit of the rom correction address of channel n. bits 15 to 6are fixed to 0, writing to these bits is ignored.
385 rom correction function (romc) chapter 9 user?s manual u17566ee5v1um00 (5) corvalnl - vfb flash/rom ?data replacement? rom correction value register these registers hold the lower 16 bit of the value that shall replace the original value from the vfb flash/rom. access these registers can be read/written in 16-bit units. address corval0l: ffff f930 h corval1l: ffff f934 h corval2l: ffff f938 h corval3l: ffff f93c h corval4l: ffff f940 h corval5l: ffff f944 h initial value 0000 h note corvalnl shall only be changed when the corresponding channel is disabled (corctl0.corcenn = 0). 1514131211109876543210 corvaln[15:0] r/w table 9-6 corvalnl register contents bit position bit name function 15 to 0 corvaln [15:0] lower 16 bit of the correction value to replace the rom contents.
386 chapter 9 rom correction function (romc) user?s manual u17566ee5v1um00 (6) corvalnh - vfb flash/rom ?data replacement? rom correction value register these registers hold the upper 16 bit of the value that shall replace the original value from the vfb flash/rom. access these registers can be read/written in 16-bit units. address corval0h: ffff f932 h corval1h: ffff f936 h corval2h: ffff f93a h corval3h: ffff f93e h corval4h: ffff f942 h corval5h: ffff f946 h initial value 0000 h note corvalnh shall only be changed when the corresponding channel is disabled (corctl0.corcenn = 0). 1514131211109876543210 corvaln[31:16] r/w table 9-7 corvalnh register contents bit position bit name function 15 to 0 corvaln [31:16] upper 16 bit of the correction value to replace the rom contents.
387 rom correction function (romc) chapter 9 user?s manual u17566ee5v1um00 9.3 ?dbtrap? rom correction unit ? 1x 8 channels for vfb flash memory and rom ? 1 x 8 channels for vsb flash memory (for pd70f3426a only) ? the individual channels of eachthe ?dbtrap? rom correction unit are identified by ?m? (m = 0 to 7) ? programmable correction address for each channel ? ?dbtrap? exception processing upon correction address match ? enable/disable of each channel individually by software caution the ?dbtrap? rom correction unit is also used by the n-wire on-chip debug unit. thus rom correction will not be performed on these correction channels when the microcontroller is operating in n-wire debug mode. note in the following only the register names of the ?dbtrap? rom correction unit for the vfb flash/rom is used for both ?dbtrap? rom correction units, for vfb flash/rom and pd70f3426a vsb flash memory. ? corcn (vfb flash/rom) stands also for pd70f3426a?s cor2cn (vsb flash memory) ? coradn (vfb flash/rom) stands also for pd70f3426a?s cor2adn (vsb flash memory) figure 9-8 ?dbtrap? rom correction block diagram vfb a ddre ss bus vfb d a t a bus correction a ddre ss regi s ter coradm corcn.corenm comp a r a tor rom/fl as h dbtrap - rom/fl as h d a t a repl a cement rom/fl as h d a t a dbtrap opcode
388 chapter 9 rom correction function (romc) user?s manual u17566ee5v1um00 9.3.1 ?dbtrap? rom correction operation the ?dbtrap? rom correction unit compares the address on the v850 fetch bus (vfb) with the contents of the programmable correction address registers coradm. if an address matches, the dbtrap instruction opcode is put on the v850 fetch bus instead of the rom contents. if no address matches, the rom contents is passed on the fetch bus as normal. the dbtrap exception branches to the dbtrap/ilgop exception handler address 0000 0060 h , which comprises the user?s rom correction instructions. since the rom correction routines for all correction channels are invoked at the dbtrap exception handler address 0000 0060 h , the exception handler has to evaluate first the right correction routine to be executed. this is done by reading the dbpc register, which holds the address next to the correction address of coradm, which has caused the dbtrap exception. if non of coradm matches dbpc - 2, dbtrap was generated by an illegal opcode detection event ilgop. for further details concerning dbtrap/ilgop handling refer to ?exception trap? on page 261 . figure 9-9 outlines a typical program flow for using the ?dbtrap? rom correction. 1. if the address coradm to be corrected and the fetch address of the internal rom memory match, the instruction code fetched from rom is replaced by the dbtrap instruction. 2. when the dbtrap instruction is executed, execution branches to address 0000 0060 h . 3. the dbtrap evaluation routine identifies the cause of the dbtrap exception and launches either the appropriate rom correction routine or the ilgop handler. 4. in case several consecutive rom instruction are replaced by rom correction code the return address in dbpc must be corrected. it may also be required to correct some flags in the dbpsw register. 5. return processing is started by the dbret instruction.
389 rom correction function (romc) chapter 9 user?s manual u17566ee5v1um00 figure 9-9 rom correction operation and program flow reset & start fetch address = coradm? coradm = dbpc-2? corenm bit = 1? initialize microcontroller set coradm register change fetch code to dbtrap instruction branch to dbtrap evaluation routine branch to correction code address of corresponding channel m execute fetch code read data for setting rom correction from external execute dbtrap instruction jump to address 0000 0060 h execute correction code set corcn register yes yes yes no no notes: : processing by user program (software) : processing by rom correction (hardware) load dbtrap exception handler and rom correction code execute fetch code ilgop processing no execute dbret instruction if necessary, correct: - return address in dbpc - flags in dbpsw
390 chapter 9 rom correction function (romc) user?s manual u17566ee5v1um00 9.3.2 ?dbtrap? rom correction registers (1) corcn - vfb flash/rom ?dbtrap? rom correction control register this register enables or disables the vfb flash/rom rom correction of each channel. access this register can be read/written in 8- and 1-bit units. address ffff f880 h initial value 0000 h note rom correction of channel n should only be enabled after the correction address coradm has been set. (2) cor2cn - vsb flash ?dbtrap? rom correction control register (pd70f3426a only) this register enables or disables vsb flash memory rom correction of each channel. access this register can be read/written in 8- and 1-bit units. address ffff f9d0 h initial value 0000 h note rom correction of channel n should only be enabled after the correction address cor2adm has been set. 76543210 coren7 coren6 coren5 coren4 coren3 coren2 coren1 coren0 r/w r/w r/w r/w r/w r/w r/w r/w table 9-8 corcn register contents bit position bit name function 7 to 0 corenm rom correction channel 0: rom correction for channel m disabled 1: rom correction for channel m enabled 76543210 cor2en7 cor2en6 cor2en5 cor2en4 cor2en3 cor2en2 cor2en1 cor2en0 r/w r/w r/w r/w r/w r/w r/w r/w table 9-9 cor2cn register contents bit position bit name function 7 to 0 cor2enm rom correction channel 0: rom correction for channel m disabled 1: rom correction for channel m enabled
391 rom correction function (romc) chapter 9 user?s manual u17566ee5v1um00 (3) coradm - vfb flash/rom ?dbtrap? rom correction address register these registers hold the address where the vfb flash/rom correction should be performed. access these registers can be read/written in 32-bit (coradm) and 16-bit units (coradml for bits 15 to 0, coradmh for bits 31 to 16). address corad0, corad0l: ffff f840 h corad0h: ffff f842 h corad1, corad1l: ffff f844 h corad1h: ffff f846 h corad2, corad2l: ffff f848 h corad2h: ffff f84a h corad3, corad3l: ffff f84c h corad3h: ffff f84e h corad4, corad4l: ffff f850 h corad4h: ffff f852 h corad5, corad5l: ffff f854 h corad5h: ffff f856 h corad6, corad6l: ffff f858 h corad6h: ffff f85a h corad7, corad7l: ffff f85c h corad7h: ffff f85e h initial value 0000 0000 h caution the rom correction address coradm[19:0] must not exceed the upper address of the internal rom respectively flash memory. if the internal rom/flash memory size is less than 1 mb the appropriate number of upper address bits of coradm[19:0] must be set to 0. note coradm shall only be changed when the corresponding channel is disabled (corcn.corenm = 0). 1514131211109876543210 coradm[15:0] 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 000000000000 coradm[19:16] r/w table 9-10 coradm register contents bit position bit name function 19 to 0 coradm [19:0] lower 16 bit of the rom correction address of channel m. bit 0 and bits 31 to 20 are fixed to 0, writing to these bits is ignored.
392 chapter 9 rom correction function (romc) user?s manual u17566ee5v1um00 (4) cor2adm - vsb flash ?dbtrap? rom correction address register (pd70f3426a only) these registers hold the address where the vsb flash memory correction should be performed. access these registers can be read/written in 32-bit (cor2adm) and 16-bit units (cor2adml for bits 15 to 0, cor2admh for bits 31 to 16). address cor2ad0, cor2ad0l: ffff f8a0 h cor2ad0h: ffff f8a2 h cor2ad1, cor2ad1l: ffff f8a4 h cor2ad1h: ffff f8a6 h cor2ad2, cor2ad2l: ffff f8a8 h cor2ad2h: ffff f8aa h cor2ad3, cor2ad3l: ffff f8ac h cor2ad3h: ffff f8ae h cor2ad4, cor2ad4l: ffff f8b0 h cor2ad4h: ffff f8b2 h cor2ad5, cor2ad5l: ffff f8b4 h cor2ad5h: ffff f8b6 h cor2ad6, cor2ad6l: ffff f8b8 h cor2ad6h: ffff f8ba h cor2ad7, cor2ad7l: ffff f8bc h cor2ad7h: ffff f8be h initial value 0000 0000 h caution the rom correction address cor2adm[19:0] must not exceed the upper address of the internal vsb flash memory. note cor2adm shall only be changed when the corresponding channel is disabled (cor2cn.cor2enm = 0). 1514131211109876543210 cor2adm[15:0] 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 000000000000 cor2adm[19:16] r/w table 9-11 cor2adm register contents bit position bit name function 19 to 0 cor2adm [19:0] lower 16 bit of the rom correction address of channel m. bit 0 and bits 31 to 20 are fixed to 0, writing to these bits is ignored.
393 user?s manual u17566ee5v1um00 chapter 10 code prot ection and security 10.1 overview the microcontroller supports various methods for protecting the program code in the flash memory from undesired access, such as illegal read-out or illegal reprogramming. some interfaces offer in general access to the internal flash memory: n-wire debug interface, external flash programmer interface, self-programming facilities and test interfaces. in the following the security relevant items are listed. the features to protect the internal flash memory data from being read by unauthorized persons are described. for more information on the flash memory, see ?flash memory? on page 269 . the following sections give an overview about supported code protection methods. 10.2 boot rom undesired access to the flash memory via the boot rom is not possible. 10.3 n-wire debug interface in general, illegal read-out of the flash memory contents is possible via the n-wire debug interface. for protection of the flash memory, the usage of the debug interface can be protected and it can be disabled. the debug interface is protected via a 10-byte id code and an internal flag (n-wire use enable flag). when the debugger is started, the status of a flag is queried (n-wire use enable flag). set this flag to zero to disable the use of the n-wire in-circuit emulator. when debugging is enabled (n-wire use enable flag is set), you have to enter a 10-byte id code via the debugger. the code is compared with the id code stored in the internal flash memory. if the codes do not match, debugging is not possible. the n-wire use enable flag can be set or reset while reprogramming the flash by an external flash writer or with the self-programming feature. the flag is located at bit 7 at address 0000 0079 h . you can specify your own 10-byte id code and program it to the internal flash memory by an external flash writer or with the self-programming feature. the id code is located in the address range 0000 0070 h to 0000 0079 h . the protection levels are summarized in ta b l e 1 0 - 1
394 chapter 10 code protection and security user?s manual u17566ee5v1um00 note 1. after you have set protection levels 1 or 2, set the ?block erase disable flag? in the flash extra area. otherwise, an unauthorized person could erase the block that contains the id code or the ?n-wire use enable flag?, respectively, and thus suspend the protection. 2. if an unauthorized user tries to find out the 10-byte id by comparing all possible id codes, this will take up to 3.83 x 10 8 years at 100 mhz. for more details refer to ?security function? on page 971 . table 10-1 possible results of id code comparison n-wire use enable flag id code protection level 0x a a) codes are not compared level 2: full protection n-wire debug interface cannot be used. b b) once the n-wire debug interface has been set as ?use-prohibited?, it cannot be used until the flash memory is re-programmed. 1 user-specific id code level 1: id code protection n-wire debug interface can only be used if the user enters the correct id code. id code is all ones c c) this is the default state after the flash memory has been erased. level 0: no protection n-wire debug interface can be used.
395 code protection and security chapter 10 user?s manual u17566ee5v1um00 10.4 flash writer and self-programming protection in general, illegal read-out and re-programming of the flash memory contents is possible via the flash writer interface and the self-programming feature. for protection of the flash memory, the following flags provide various protection levels. the flags can be set by flash programmers. for a description of flash memory programming see ?flash memory? on page 269 . (1) program protection flag (program protection function) set this flag to disable the programming function via flash writer interface. this flag does not affect the self-programming interface. the flag is valid for the whole flash memory. (2) chip erase protection flag (chip erase protection function) set this flag to disable the chip erase function via flash writer interface. this flag does not affect the self-programming interface. (3) block erase protection flag (block erase protection function) set this flag to disable the feature to erase single blocks via flash writer interface. this flag does not affect the self-programming interface. this flag does not affect the chip erase function. the flag is valid for the whole flash memory. (4) read-out protection flag (read-out protection function) set this flag to disable the feature that allows reading back the flash memory via flash writer interface. this flag does not affect the self-programming interface. this flag is valid for the whole flash memory. (5) boot block cluster protection flag set this flag to disable erasure and rewrite of the boot block cluster. the boot block cluster can not be manipulated in any way (no erase/write). this applies in serial and self-programming mode. once this flag is set, it is impossible to reset this flag. thus the boot block cluster content can not be changed any more.
396 chapter 10 code protection and security user?s manual u17566ee5v1um00 10.5 additional firmware functions the internal firmware provides several additional features related to protection and security. these are listed above. 10.5.1 id-field a dedicated 64-byte id-field is provided to hold user defined information, like for instance s/w versions. the id-field is stored in the user space of the flash memory, starting at address 0000 0800 h . the firmware allows to read the id-field via an external flash programmer data even if the read-out protection flag (refer to 10.4 on page 395 ) is set. 10.5.2 checksum calculation a dedicated firmware function calculates a checksum over the flash memory contents. the algorithm to calculate the checksum is ?standard crc32?. the checksum calculation starts from address 0000 0000 h to the address stored at 0000 0840 h to 0000 0843 h . the bytes stored at 0000 0840 h to 0000 0843 h are subject to the checksum. the 64-byte id-field is not subject to this checksum. the firmware allows to read the checksum via an external flash programmer data even if the read-out protection flag (refer to 10.4 on page 395 ) is set. 10.5.3 variable reset vector the reset vector, determining the start of the user?s program is stored in an ?extra area? of the flash memory. this vector is configurable via an external flash programmer and by self-programming.
397 user?s manual u17566ee5v1um00 chapter 11 16-bit timer/ event counter p (tmp) timer p (tmp) is a 16-bit timer/event counter. the v850e/dx3 microcontrollers have following instances of the 16-bit timer/ event counter tmp: throughout this chapter, the individual instances of timer p are identified by ?n?, for example tmpn, or tpnctl0 for the tmpn control register 0. 11.1 overview an outline of tmpn is shown below. ? clock selection: 8 ways ? capture/trigger input pins: 2 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 2 ? capture/compare match interrupt request signals: 2 ? timer output pins: 2 tmp all devices instances 4 names tmp0 to tmp3
398 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 11.2 functions tmpn has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement ? tmp0 and tmp1 can be used for triggering the dma controller. ? all tmpn can be optionally stopped when a breakpoint is hit during debugging (refer to ?on-chip debug unit? on page 969 ). 11.3 configuration tmpn includes the following hardware. figure 11-1 block diagram of tmpn pclk0 (16 mhz) pclk01=pclk0/2 note ( 8 mhz) pclk02=pclk0/4 note (4 mhz) pclk4 (1 mhz) pclk5 (500 khz) pclk6 (250 khz) pclk7 (125 khz) tipn0 tipn1 s elector s elector tpncnt 16- b it co u nter ccr0 bu ffer regi s ter ccr1 bu ffer regi s ter tpnccr0 tpnccr1 o u tp u t controller inttpnov tpn0 tpn1 inttpncc0 inttpncc1 cle a r edge detector intern a l bus intern a l bus
399 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 the second (pclk01) and the third (pclk02) clock selector input is not supplied from the clock generator, but derived from the first selector input pclk0 inside the timer p. in case the pll is disabled the pclkx clocks are supplied from the main oscillator, i.e.: ?pclk0=4mhz ? pclk01= pclk0/2=2mhz ? pclk02= pclk0/4=1mhz for information about pclkx, please refer to ?clock generator? on page 139 . (1) 16-bit counter this 16-bit counter can count internal clocks or external events. the count value of this counter can be read by using the tpncnt register. when the tpnctl0.tpnce bit = 0, the value of the 16-bit counter is ffffh. if the tpncnt register is read at this time, 0000h is read. reset input clears the tpnce bit to 0. therefore, the 16-bit counter is set to ffffh. (2) ccr0 buffer register this is a 16-bit compare register that compares the count value of the 16-bit counter. when the tpnccr0 register is used as a compare register, the value written to the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttpncc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, as the tpnccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that compares the count value of the 16-bit counter. when the tpnccr1 register is used as a compare register, the value written to the tpnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttpncc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, as the tpnccr1 register is cleared to 0000h. (4) edge detector this circuit detects the valid edges input to the tipn0 and tipn1 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tpnioc1 and tpnioc2 registers. (5) output controller this circuit controls the output of the topn0 and topn1 pins. the output controller is controlled by the tpnioc0 register.
400 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (6) selector this selector selects the count clock for the 16-bit counter. eight types of internal clocks or an external event can be selected as the count clock.
401 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 11.4 tmp registers the tmpn are controlled and operated by means of the following registers: table 11-1 tmpn registers overview register name shortcut address tmpn control registers 0 tpnctl0 tmpn control registers 1 tpnctl1 + 1 h tmpn i/o control register 0 tpnioc0 + 2 h tmpn i/o control register 1 tpnioc1 + 3 h tmpn i/o control register 2 tpnioc2 + 4 h tmpn option registers 0 tpnopt0 + 5 h tmpn capture/compare registers 0 tpnccr0 + 6 h tmpn capture/compare registers 1 tpnccr1 + 8 h tmpn counter read buffer register tpncnt + a h table 11-2 tmpn register base address timer base address tmp0 ffff f660 h tmp1 ffff f670 h tmp2 ffff f680 h tmp3 ffff f690 h
402 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (1) tpnctl0 - tmpn control register 0 the tpnctl0 register is an 8-bit register that controls the operation of tmpn. access this register can be read/written in 8-bit or 1-bit units. address initial value 00 h . this register is initialized by any reset. the same value can always be written to the tpnctl0 register by software. caution 1. set the tpncks2 to tpncks0 bits when the tpnce bit = 0. 2. when the value of the tpnce bit is changed from 0 to 1, the tpncks2 to tpncks0 bits can be set simultaneously. 3. be sure to clear bits 3 to 6 to 0. note for information about pclkx, please refer to ?clock generator? on page 139 . 76543210 tpnce 0 0 0 0 tpncks2 tpncks1 tpncks0 r/w r/w r/w r/w r/w r/w r/w r/w table 11-3 tpnctl0 register contents bit position bit name function 7 tpnce tmpn operation disable/enable: 0: tmpn operation disabled (tmpn reset asynchronously: reset of tpn0pt0.tpnovf bit, 16-bit counter, timer output (topn0, topn1 pins) 1: tmpn operation enabled (tmpn operation starts) 2 to 0 tpncks[2:0] internal count clock selection: tpncks2 tpncks1 tpncks0 internal count clock 000pclk0 0 0 1 pclk01 = pclk0/2 0 1 0 pclk02 = pclk0/4 0 1 1 prohibited 100pclk4 101pclk5 110pclk6 111pclk7
403 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (2) tpnctl1 - tmpn control register 1 the tpnctl1 register is an 8-bit register that controls the operation of tmpn. access this register can be read/written in 8-bit or 1-bit units. address + 1 h initial value 00 h . this register is initialized by any reset. caution 1. the tpnest bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. in any other mode, writing 1 to this bit is ignored. 2. external event count input is selected in the external event count mode regardless of the value of the tpneee bit. 76543210 0 tpnest tpneee 0 0 tpnmd2 tpnmd1 tpnmd0 r/w r/w r/w r/w r/w r/w r/w r/w table 11-4 tpnctl1 register contents bit position bit name function 6 tpnest software trigger control. 0: ? 1: generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tpnest bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tpnest bit as the trigger. 5 tpneee count clock selection: 0: disable operation with external event count input. (perform counting with the count clock selected by the tpnctl0.tpnck0 to tpnck2 bits.) 1: enable operation with external event count input. (perform counting at the valid edge of the external event count input signal.) the tpneee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. 2 to 0 tpnmd[2:0] timer mode selection: tpnmd2 tpnmd1 tpnmd0 timer mode 0 0 0 interval timer 0 0 1 external event count 0 1 0 external trigger pulse output 0 1 1 one-shot pulse output 100pwm output 1 0 1 free-runnning timer 1 1 0 pulse width measurement 1 1 1 setting prohibited
404 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 3. set the tpneee and tpnmd2 to tpnmd0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) the operation is not guaranteed when rewriting is performed with the tpnce bit = 1. if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 4. be sure to clear bits 3, 4, and 7 to 0. (3) tpnioc0 - tmpn i/o control register 0 the tpnioc0 register is an 8-bit register that controls the timer output (topn0, topn1 pins). access this register can be read/written in 8-bit or 1-bit units. address + 2 h initial value 00 h . this register is initialized by any reset. caution 1. rewrite the tpnol1, tpnoe1, tpnol0, and tpnoe0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. even if the tpnolm bit is manipulated when the tpnce and tpnoem bits are 0, the topnm pin output level varies (m = 0, 1). 76543210 00 0 0 tpnol1 tpnoe1 tpnol0 tpnoe0 r/w r/w r/w r/w r/w r/w r/w r/w table 11-5 tpnioc0 register contents bit position bit name function 3 tpnol1 topn1 pin output level setting: 0: topn1 pin output inversion disabled 1: topn1 pin output inversion enabled 2 tpnoe1 topn1 pin output setting: 0: timer output disable ? when tpnol1 = 0: low level is output from topn1 pin ? when tpnol1 = 1: high level is output from topn1 pin 1: timer output enable (a square wave is output from topn1 pin.) 1 tpnol0 topn0 pin output level setting: 0: topn0 pin output inversion disabled 1: topn0 pin output inversion enabled 0 tpnoe0 topn0 pin output setting: 0: timer output disable ? when tpnol0 = 0: low level is output from topn0 pin ? when tpnol0 = 1: high level is output from topn0 pin 1: timer output enable (a square wave is output from topn0 pin.)
405 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (4) tpnioc1 - tmpn i/o control register 1 the tpnioc1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (tipn0, tipn1 pins). access this register can be read/written in 8-bit or 1-bit units. address + 3 h initial value 00 h . this register is initialized by any reset. caution 1. rewrite the tpnis3 to tpnis0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnis3 to tpnis0 bits are valid only in the free-running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible. 76543210 00 0 0 tpnis3 tpnis2 tpnis1 tpnis0 r/w r/w r/w r/w r/w r/w r/w r/w table 11-6 tpnioc1 register contents bit position bit name function 3 to 2 tpnis[3:2] capture trigger input signal (tipn1 pin) valied edge setting: tpnis3 tpnis2 capture trigger valid edge of tipn1 0 0 no edge detection (capture operation invalid) 0 1 detection of rising edge 1 0 detection of falling edge 1 1 detection of both edges 1 to 0 tpnis[1:0] capture trigger input signal (tipn0 pin) valied edge setting: tpnis1 tpnis0 capture trigger valid edge of tipn0 0 0 no edge detection (capture operation invalid) 0 1 detection of rising edge 1 0 detection of falling edge 1 1 detection of both edges
406 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (5) tpnioc2 - tmpn i/o control register 2 the tpnioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tipn0 pin) and external trigger input signal (tipn0 pin). access this register can be read/written in 8-bit or 1-bit units. address + 4 h initial value 00 h . this register is initialized by any reset. caution 1. rewrite the tpnees1, tpnees0, tpnets1, and tpnets0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnees1 and tpnees0 bits are valid only when the tpnctl1.tpneee bit = 1 or when the external event count mode (tpnctl1.tpnmd2 to tpnctl1.tpnmd0 bits = 001) has been set. 76543210 00 0 0 tpnees1 tpnees0 tpnets1 tpnets0 r/w r/w r/w r/w r/w r/w r/w r/w table 11-7 tpnioc2 register contents bit position bit name function 3 to 2 tpnees[1:0] external event count input signal (tipn0 pin) valid edge setting: tpnees1 tpnees0 external event count valid edge of tipn0 0 0 no edge detection (external event invalid) 0 1 detection of rising edge 1 0 detection of falling edge 1 1 detection of both edges 1 to 0 tpnets[1:0] capture trigger input signal (tipn0 pin) valid edge setting: tpnets1 tpnets0 external trigger input valid edge of tipn0 0 0 no edge detection (external trigger invalid) 0 1 detection of rising edge 1 0 detection of falling edge 1 1 detection of both edges
407 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (6) tpnopt0 - tmpn option register 0 the tpnopt0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. access this register can be read/written in 8-bit or 1-bit units. address + 5 h initial value 00 h . this register is initialized by any reset. caution 1. rewrite the tpnccs1 and tpnccs0 bits when the tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3, 6, and 7 to 0. 76543210 00 tpnccs1 tpnccs10 0 0 0 tpnovf r/w r/w r/w r/w r/w r/w r/w r/w table 11-8 tpnopt0 register contents bit position bit name function 5 tpnccs1 tpnccr1 register capture/compare selection: 0: compare register selected 1: capture register selected the tpnccs1 bit setting is valid only in the free-running timer mode. 4 tpnccs0 tpnccr0 register capture/compare selection: 0: compare register selected 1: capture register selected the tpnccs0 bit setting is valid only in the free-running timer mode. 0 tpnovf tmpn overflow detection flag: set (1): overflow occurred reset (0): tpnovf bit 0 written or tpnctl0.tpnce bit = 0 ? the tpnovf bit is reset when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an interrupt request signal (inttpnov) is generated at the same time that the tpnovf bit is set to 1. the inttpnov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the tpnovf bit is not cleared even when the tpnovf bit or the tpnopt0 register are read when the tpnovf bit = 1. ? the tpnovf bit can be both read and written, but the tpnovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmpn.
408 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (7) tpnccr0 - tmpn capture/compare register 0 the tpnccr0 register can be used as a capture register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tpnopt0.tpnccs0 bit. in the pulse width measurement mode, the tpnccr0 register can be used only as a capture register. in any other mode, this register can be used only as a compare register. the tpnccr0 register can be read or written during operation. access this register can be read/written in 16-bit units. address + 6 h initial value 0000 h . this register is initialized by any reset. (a) function as compare register the tpnccr0 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttpncc0) is generated. if topn0 pin output is enabled at this time, the output of the topn0 pin is inverted. when the tpnccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one- shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count value matches the value of the ccr0 buffer register. 1514131211109876543210 ccr0 value r/w
409 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (b) function as capture register when the tpnccr0 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the tpnccr0 register if the valid edge of the capture trigger input pin (tipn0 pin) is detected. in the pulse-width measurement mode, the count value of the 16-bit counter is stored in the tpnccr0 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tipn0) is detected. even if the capture operation and reading the tpnccr0 register conflict, the correct value of the tpnccr0 register can be read. the following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. table 11-9 function of capture/compare regi ster in each mode and how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register -
410 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (8) tpnccr1 - tmpn capture/compare register 1 the tpnccr1 register can be used as a capture register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tpnopt0.tpnccs1 bit. in the pulse width measurement mode, the tpnccr1 register can be used only as a capture register. in any other mode, this register can be used only as a compare register. the tpnccr1 register can be read or written during operation. access this register can be read/written in 16-bit units. address + 8 h initial value 0000 h . this register is initialized by any reset. (a) function as compare register the tpnccr1 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttpncc1) is generated. if topn1 pin output is enabled at this time, the output of the topn1 pin is inverted. 1514131211109876543210 ccr1 value r/w
411 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (b) function as capture register when the tpnccr1 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the tpnccr1 register if the valid edge of the capture trigger input pin (tipn1 pin) is detected. in the pulse-width measurement mode, the count value of the 16-bit counter is stored in the tpnccr1 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tipn1) is detected. even if the capture operation and reading the tpnccr1 register conflict, the correct value of the tpnccr1 register can be read. the following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. (9) tpncnt - tmpn counter read buffer register the tpncnt register is a read buffer register that can read the count value of the 16-bit counter. if this register is read when the tpnctl0.tpnce bit = 1, the count value of the 16-bit timer can be read. the value of the tpncnt register is cleared to 0000 h when the tpnce bit = 0. if the tpncnt register is read at this time, the value of the 16-bit counter (ffff h ) is not read, but 0000 h is read. access this register can be read only in 16-bit units. address + a h initial value 0000 h . this register is initialized by any reset, as the tpnce bit is cleared to 0. table 11-10 function of capture/compare regi ster in each mode and how to write compare register operationmode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register - 1514131211109876543210 tpncnt value r
412 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 11.5 operation tmpn can perform the following operations. note 1. to use the external event count mode, specify that the valid edge of the tipn0 pin capture trigger input is not detected (by clearing the tpnioc1.tpnis1 and tpnioc1.tpnis0 bits to ?00?). 2. when using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tpnctl1.tpneee bit to 0). 11.5.1 interval timer mode (tpnmd2 to tpnmd0 = 000) in the interval timer mode, an interrupt request signal (inttpncc0) is generated at the specified interval if the tpnctl0.tpnce bit is set to 1. a square wave whose half cycle is equal to the interval can be output from the topn0 pin. usually, the tpnccr1 register is not used in the interval timer mode. figure 11-2 configuration of interval timer operation tpnctl1.tpnest bit (software trigger bit) tipn0 pin (ext. trigger input) capture/ compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable 16- b it co u nter o u tp u t controller ccr0 bu ffer regi s ter tpnce b it tpnccr0 regi s ter co u nt clock s election cle a r m a tch s ign a l topn0 pin inttpncc0 s ign a l
413 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 figure 11-3 basic timing of operation in interval timer mode when the tpnce bit is set to 1, the value of the 16-bit counter is cleared from ffffh to 0000h in synchronization with the count clock, and the counter starts counting. at this time, the output of the topn0 pin is inverted. additionally, the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the topn0 pin is inverted, and a compare match interrupt request signal (inttpncc0) is generated. the interval can be calculated by the following expression. interval = (set value of tpnccr0 register + 1) count clock cycle (1) register setting for interval timer mode operation (a) tmpn control register 0 (tpnctl0) ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter topn0 pin o u tp u t inttpncc0 s ign a l d 0 d 0 d 0 d 0 d 0 interv a l (d 0 + 1) interv a l (d 0 + 1) interv a l (d 0 + 1) interv a l (d 0 + 1) 0/1 0 0 0 0 tpnctl0 s elect co u nt clock 0: s top co u nting 1: en ab le co u nting 0/1 0/1 0/1 tpnck s 2 tpnck s 1 tpnck s 0 tpnce
414 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (b) tmpn control register 1 (tpnctl1) (c) tmpn i/o control register 0 (tpnioc0) (d) tmpn counter read buffer register (tpncnt) by reading the tpncnt register, the count value of the 16-bit counter can be read. (e) tmpn capture/compare register 0 (tpnccr0) if the tpnccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle (f) tmpn capture/compare register 1 (tpnccr1) usually, the tpnccr1 register is not used in the interval timer mode. however, the set value of the tpnccr1 register is transferred to the ccr1 buffer register. a compare match interrupt request signal (inttpncc1) is generated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. therefore, mask the interrupt request by using the corresponding interrupt mask flag (tpnccmk1). note tmpn i/o control register 1 (tpnioc1), tmpn i/o control register 2 (tpnioc2), and tmpn option register 0 (tpnopt0) are not used in the interval timer mode. 00000 tpnctl1 0, 0, 0: interv a l timer mode 000 tpnmd2 tpnmd1 tpnmd0 tpneee tpne s t 0 0 0 0 0/1 tpnioc0 0: di sab le topn0 pin o u tp u t 1: en ab le topn0 pin o u tp u t s etting of o u tp u t level with oper a tion of topn0 pin di sab led 0: low level 1: high level 0: di sab le topn1 pin o u tp u t 1: en ab le topn1 pin o u tp u t s etting of o u tp u t level with oper a tion of topn1 pin di sab led 0: low level 1: high level 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1
415 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (2) interval timer mode operation flow figure 11-4 software processing flow in interval timer mode ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter topn0 pin o u tp u t inttpncc0 s ign a l d 0 d 0 d 0 d 0 <1> <2> tpnce b it = 1 tpnce b it = 0 regi s ter initi a l s etting tpnctl0 regi s ter (tpnck s 0 to tpnck s 2 b it s ) tpnctl1 regi s ter, tpnioc0 regi s ter, tpnccr0 regi s ter initi a l s etting of the s e regi s ter s i s performed b efore s etting the tpnce b it to 1. the tpnck s 0 to tpnck s 2 b it s c a n b e s et a t the sa me time when co u nting h as b een s t a rted (tpnce b it = 1). the co u nter i s initi a lized a nd co u nting i s s topped b y cle a ring the tpnce b it to 0. s ta rt s top <1> co u nt oper a tion s t a rt flow <2> co u nt oper a tion s top flow
416 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (3) interval timer mode operation timing (a) operation if tpnccr0 register is set to 0000h if the tpnccr0 register is set to 0000h, the inttpncc0 signal is generated at each count clock, and the output of the topn0 pin is inverted. the value of the 16-bit counter is always 0000h. (b) operation if tpnccr0 register is set to ffffh if the tpnccr0 register is set to ffffh, the 16-bit counter counts up to ffffh. the counter is cleared to 0000h in synchronization with the next count-up timing. the inttpncc0 signal is generated and the output of the topn0 pin is inverted. at this time, an overflow interrupt request signal (inttpnov) is not generated, nor is the overflow flag (tpnopt0.tpnovf bit) set to 1. co u nt clock 16- b it co u nter tpnce b it tpnccr0 regi s ter topn0 pin o u tp u t inttpncc0 s ign a l 0000h interv a l time co u nt clock cycle interv a l time co u nt clock cycle interv a l time co u nt clock cycle ffffh 0000h 0000h 0000h 0000h ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter topn0 pin o u tp u t inttpncc0 s ign a l ffffh interv a l time 10000h co u nt clock cycle interv a l time 10000h co u nt clock cycle interv a l time 10000h co u nt clock cycle
417 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (c) notes on rewriting tpnccr0 register to change the value of the tpnccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. note 1. interval time (1): (d 1 + 1) count clock cycle 2. interval time (ng): (10000h + d 2 + 1) count clock cycle 3. interval time (2): (d 2 + 1) count clock cycle if the value of the tpnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tpnccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit counter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttpncc0 signal is generated and the output of the topn0 pin is inverted. therefore, the inttpncc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 +1) count clock period?. ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter tpnol0 b it topn0 pin o u tp u t inttpncc0 s ign a l d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interv a l time (1) interv a l time (ng) interv a l time (2)
418 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (d) operation of tpnccr1 register figure 11-5 configuration of tpnccr1 register if the set value of the tpnccr1 register is less than the set value of the tpnccr0 register, the inttpncc1 signal is generated once per cycle. at the same time, the output of the topn1 pin is inverted. the topn1 pin outputs a square wave with the same cycle as that output by the topn0 pin. ccr0 bu ffer regi s ter tpnccr0 regi s ter tpnccr1 regi s ter ccr1 bu ffer regi s ter topn0 pin inttpncc0 s ign a l topn1 pin inttpncc1 s ign a l 16- b it co u nter o u tp u t controller tpnce b it co u nt clock s election cle a r m a tch s ign a l o u tp u t controller m a tch s ign a l
419 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 figure 11-6 timing chart when d 01  d 11 if the set value of the tpnccr1 register is greater than the set value of the tpnccr0 register, the count value of the 16-bit counter does not match the value of the tpnccr1 register. consequently, the inttpncc1 signal is not generated, nor is the output of the topn1 pin changed. ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter topn0 pin o u tp u t inttpncc0 s ign a l tpnccr1 regi s ter topn1 pin o u tp u t inttpncc1 s ign a l d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01
420 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 figure 11-7 timing chart when d 01 < d 11 ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter topn0 pin o u tp u t inttpncc0 s ign a l tpnccr1 regi s ter topn1 pin o u tp u t inttpncc1 s ign a l d 01 d 11 d 01 d 01 d 01 d 01 l
421 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 11.5.2 external event count m ode (tpnmd2 to tpnmd0 = 001) in the external event count mode, the valid edge of the external event count input is counted when the tpnctl0.tpnce bit is set to 1, and an interrupt request signal (inttpncc0) is generated each time the specified number of edges have been counted. the topn0 pin cannot be used. usually, the tpnccr1 register is not used in the external event count mode. figure 11-8 configuration in external event count mode figure 11-9 basic timing in external event count mode caution this figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. 16- b it co u nter ccr0 bu ffer regi s ter tpnce b it tpnccr0 regi s ter edge detector cle a r m a tch s ign a l inttpncc0 s ign a l tipn0 pin (extern a l event co u nt inp u t) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal d 0 d 0 d 0 d 0 16-bit counter tpnccr0 register inttpncc0 signal external event count input (tipn0 pin input) d 0 external event count interval (d0) d 0 ? 1d 0 0000 0001 external event count interval (d0 + 1) external event count interval (d0 + 1)
422 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 when the tpnce bit is set to 1, the value of the 16-bit counter is cleared from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detected. additionally, the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttpncc0) is generated. the inttpncc0 signal is generated each time the valid edge of the external event count input has been detected (set value of tpnccr0 register + 1) times. (1) register setting for operation in external event count mode (a) tmpn control register 0 (tpnctl0) (b) tmpn control register 1 (tpnctl1) 0/1 0 0 0 0 tpnctl0 0: s top co u nting 1: en ab le co u nting 000 tpnck s 2 tpnck s 1 tpnck s 0 tpnce 00100 tpnctl1 0, 0, 1: extern a l event co u nt mode 001 tpnmd2 tpnmd1 tpnmd0 tpneee tpne s t 1: co u nt with extern a l event inp u t s ign a l
423 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (c) tmpn i/o control register 0 (tpnioc0) (d) tmpn i/o control register 2 (tpnioc2) (e) tmpn counter read buffer register (tpncnt) the count value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register 0 (tpnccr0) if d 0 is set to the tpnccr0 register, the counter is cleared and a compare match interrupt request signal (inttpncc0) is generated when the number of external event counts reaches (d 0 + 1). (g) tmpn capture/compare register 1 (tpnccr1) usually, the tpnccr1 register is not used in the external event count mode. however, the set value of the tpnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttpncc1) is generated. therefore, mask the interrupt signal by using the interrupt mask flag (tpnccmk1). note tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the external event count mode. 0 0 0 0 0/1 tpnioc0 0: di sab le topn0 pin o u tp u t 0: di sab le topn1 pin o u tp u t 1: en ab le topn1 pin o u tp u t s etting of o u tp u t level with oper a tion of topn1 pin di sab led 0: low level 1: high level 0/1 0 0 tpnoe1 tpnol0 tpnoe0 tpnol1 0 0 0 0 0/1 tpnioc2 s elect v a lid edge of extern a l event co u nt inp u t 0/1 0 0 tpnee s 0 tpnet s 1 tpnet s 0 tpnee s 1
424 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 caution when the compare register tpnccr0 (tpnccr1) is set to 0000 h and the external event counter mode is started the first interrupt inttpncc0 (inttpncc1) occurs upon the first timer overflow (tpncnt: ffff h  0000 h ), but not with the first external count event. afterwards the following interrupts inttpncc0 (inttpncc1) are generated as specified, i.e. with each external count event.
425 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (2) external event count mode operation flow figure 11-10 flow of software processing in external event count mode ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter inttpncc0 s ign a l d 0 d 0 d 0 d 0 <1> <2> tpnce b it = 1 tpnce b it = 0 regi s ter initi a l s etting tpnctl0 regi s ter (tpnck s 0 to tpnck s 2 b it s ) tpnctl1 regi s ter, tpnioc0 regi s ter, tpnioc2 regi s ter, tpnccr0 regi s ter, initi a l s etting of the s e regi s ter s i s performed b efore s etting the tpnce b it to 1. the tpnck s 0 to tpnck s 2 b it s c a n b e s et a t the sa me time when co u nting h as b een s t a rted (tpnce b it = 1). the co u nter i s initi a lized a nd co u nting i s s topped b y cle a ring the tpnce b it to 0. s ta rt s top <1> co u nt oper a tion s t a rt flow <2> co u nt oper a tion s top flow
426 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (3) operation timing in external event count mode (a) operation if tpnccr0 register is set to 0000h if the tpnccr0 register is set to 0000h, the inttpncc0 signal is generated each time the valid signal of the external event count signal has been detected. the 16-bit counter is always 0000h. (b) operation if tpnccr0 register is set to ffffh if the tpnccr0 register is set to ffffh, the 16-bit counter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count- up timing, and the inttpncc0 signal is generated. at this time, the tpnopt0.tpnovf bit is not set. extern a l event co u nt s ign a l 16- b it co u nter tpnce b it tpnccr0 regi s ter inttpncc0 s ign a l 0000h extern a l event co u nt s ign a l interv a l extern a l event co u nt s ign a l interv a l extern a l event co u nt s ign a l interv a l ffffh 0000h 0000h 0000h 0000h ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter inttpncc0 s ign a l ffffh extern a l event co u nt s ign a l interv a l extern a l event co u nt s ign a l interv a l extern a l event co u nt s ign a l interv a l
427 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (c) notes on rewriting the tpnccr0 register to change the value of the tpnccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. if the value of the tpnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tpnccr0 register has been rewritten. consequently, the value that is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit counter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttpncc0 signal is generated. therefore, the inttpncc0 signal may not be generated at the valid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?. ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter inttpncc0 s ign a l d 1 d 2 d 1 d 1 d 2 d 2 d 2 extern a l event co u nt s ign a l interv a l (1) (d 1 + 1) extern a l event co u nt s ign a l interv a l (ng) (10000h + d 2 + 1) extern a l event co u nt s ign a l interv a l (2) (d 2 + 1)
428 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (d) operation of tpnccr1 register figure 11-11 configuration of tpnccr1 register if the set value of the tpnccr1 register is smaller than the set value of the tpnccr0 register, the inttpncc1 signal is generated once per cycle. at the same time, the output signal of the topn1 pin is inverted. figure 11-12 timing chart when d 01  d 11 ccr0 bu ffer regi s ter tpnce b it tpnccr0 regi s ter 16- b it co u nter tpnccr1 regi s ter ccr1 bu ffer regi s ter cle a r m a tch s ign a l m a tch s ign a l inttpncc0 s ign a l o u tp u t controller topn1 pin inttpncc1 s ign a l edge detector tipn0 pin ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter inttpncc0 s ign a l tpnccr1 regi s ter topn1 pin o u tp u t inttpncc1 s ign a l d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01
429 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 if the set value of the tpnccr1 register is greater than the set value of the tpnccr0 register, the inttpncc1 signal is not generated because the count value of the 16-bit counter and the value of the tpnccr1 register do not match. nor is the output signal of the topn1 pin changed. figure 11-13 timing chart when d 01 < d 11 ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter inttpncc0 s ign a l tpnccr1 regi s ter topn1 pin o u tp u t inttpncc1 s ign a l d 01 d 11 d 01 d 01 d 01 d 01 l
430 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 11.5.3 external trigger pulse output mode (tpnmd2 to tpnmd0 = 010) in the external trigger pulse output mode, 16-bit timer/event counter p waits for a trigger when the tpnctl0.tpnce bit is set to 1. when the valid edge of an external trigger input signal is detected, 16-bit timer/event counter p starts counting, and outputs a pwm waveform from the topn1 pin. pulses can also be output by generating a software trigger instead of using the external trigger. when using a software trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the topn0 pin. figure 11-14 configuration in external trigger pulse output mode ccr0 bu ffer regi s ter tpnce b it tpnccr0 regi s ter 16- b it co u nter tpnccr1 regi s ter ccr1 bu ffer regi s ter cle a r m a tch s ign a l m a tch s ign a l inttpncc0 s ign a l o u tp u t controller (r s -ff) o u tp u t controller topn1 pin inttpncc1 s ign a l topn0 pin co u nt clock s election co u nt s t a rt control edge detector s oftw a re trigger gener a tion tipn0 pin tr a n s fer tr a n s fer s r
431 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 figure 11-15 basic timing in external trigger pulse output mode 16-bit timer/event counter p waits for a trigger when the tpnce bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counting at the same time, and outputs a pwm waveform from the topn1 pin. if the trigger is generated again while the counter is operating, the counter is cleared to 0000h and restarted. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tpnccr1 register) count clock cycle cycle = (set value of tpnccr0 register + 1) count clock cycle duty factor = (set value of tpnccr1 register)/(set value of tpnccr0 register + 1) the compare match request signal inttpncc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttpncc1 is generated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tpnccrm register is transferred to the ccrm buffer register when the count value of the 16-bit counter matches the value of the ccrm buffer register and the 16-bi t counter is cleared to 0000h. the valid edge of an external trigger input signal, or setting the software trigger (tpnctl1.tpnest bit) to 1 is used as the trigger. ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter inttpncc0 s ign a l tpnccr1 regi s ter inttpncc1 s ign a l topn1 pin o u tp u t extern a l trigger inp u t (tipn0 pin inp u t) topn0 pin o u tp u t ( s oftw a re trigger) d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 d 0 w a it for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 )
432 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (1) setting of registers in external trigger pulse output mode (a) tmpn control register 0 (tpnctl0) note the setting is invalid when the tpnctl1.tpneee bit = 1. (b) tmpn control register 1 (tpnctl1) 0/1 0 0 0 0 tpnctl0 s elect co u nt clock note 0: s top co u nting 1: en ab le co u nting 0/1 0/1 0/1 tpnck s 2 tpnck s 1 tpnck s 0 tpnce 0 0/1 0/1 0 0 tpnctl1 0: oper a te on co u nt clock s elected b y tpnck s 0 to tpnck s 2 b it s 1: co u nt with extern a l event inp u t s ign a l gener a te s oftw a re trigger when 1 i s written 010 tpnmd2 tpnmd1 tpnmd0 tpneee tpne s t 0, 1, 0: extern a l trigger p u l s e o u tp u t mode
433 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (c) tmpn i/o control register 0 (tpnioc0) (d) tmpn i/o control register 2 (tpnioc2) (e) tmpn counter read buffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare registers 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle note tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the external trigger pulse output mode. 0 0 0 0 0/1 tpnioc0 0: di sab le topn0 pin o u tp u t 1: en ab le topn0 pin o u tp u t s etting s of o u tp u t level while oper a tion of topn0 pin i s di sab led 0: low level 1: high level 0: di sab le topn1 pin o u tp u t 1: en ab le topn1 pin o u tp u t s pecifie s a ctive level of topn1 pin o u tp u t 0: active-high 1: active-low 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin o u tp u t 16- b it co u nter ? when tpnol1 b it = 0 topn1 pin o u tp u t 16- b it co u nter ? when tpnol1 b it = 1 0 0 0 0 0/1 tpnioc2 s elect v a lid edge of extern a l trigger inp u t s elect v a lid edge of extern a l event co u nt inp u t 0/1 0/1 0/1 tpnee s 0 tpnet s 1 tpnet s 0 tpnee s 1
434 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (2) operation flow in external trigger pulse output mode figure 11-16 software processing flow in external trigger pulse output mode (1/2) ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter ccr0 bu ffer regi s ter inttpncc0 s ign a l tpnccr1 regi s ter ccr1 bu ffer regi s ter inttpncc1 s ign a l topn1 pin o u tp u t extern a l trigger inp u t (tipn0 pin inp u t) topn0 pin o u tp u t ( s oftw a re trigger) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> < 3 > <4> <5>
435 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 figure 11-17 software processing flow in external trigger pulse output mode (2/2) (3) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tpnccr1 register last. rewrite the tpnccrm register after writing the tpnccr1 register after the inttpncc0 signal is detected. tpnce b it = 1 s etting of tpnccr0 regi s ter regi s ter initi a l s etting tpnctl0 (tpnck s 0 to tpnck s 2 b it s ) tpnctl1, tpnioc0, tpnioc2, tpnccr0, tpnccr1 initi a l s etting of the s e regi s ter s i s performed b efore s etting the tpnce b it to 1. the tpnck s 0 to tpnck s 2 b it s c a n b e s et a t the sa me time when co u nting i s en ab led (tpnce b it = 1). trigger w a it s t a t us tpnccr1 regi s ter write proce ss ing i s nece ssa ry only when the s et cycle i s ch a nged. when the co u nter i s cle a red a fter s etting, the v a l u e of the tpnccrm regi s ter i s tr a n s ferred to the ccrm bu ffer regi s ter. s ta rt s etting of tpnccr1 regi s ter <1> co u nt oper a tion s t a rt flow <2> tpnccr0 a nd tpnccr1 regi s ter s etting ch a nge flow s etting of tpnccr0 regi s ter when the co u nter i s cle a red a fter s etting, the v a l u e of the tpnccrm regi s ter i s tr a n s ferred to the ccrm bu ffer regi s ter. s etting of tpnccr1 regi s ter <4> pnccr0, tpnccr1 regi s ter s etting ch a nge flow only writing of the tpnccr1 regi s ter m us t b e performed when the s et d u ty f a ctor i s ch a nged. when the co u nter i s cle a red a fter s etting, the v a l u e of the tpnccrm regi s ter i s tr a n s ferred to the ccrm bu ffer regi s ter. s etting of tpnccr1 regi s ter < 3 > pnccr0, tpnccr1 regi s ter s etting ch a nge flow tpnce b it = 0 co u nting i s s topped. s top <5> co u nt oper a tion s top flow
436 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 in order to transfer data from the tpnccrm register to the ccrm buffer register, the tpnccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the tpnccr0 register and then set the active level width to the tpnccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tpnccr0 register, and then write the same value to the tpnccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tpnccr1 register has to be set. after data is written to the tpnccr1 register, the value written to the tpnccrm register is transferred to the ccrm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the tpnccr0 or tpnccr1 register again after writing the tpnccr1 register once, do so after the inttpncc0 signal is generated. otherwise, the value of the ccrm buffer register may become undefined because the timing of transferring data from the tpnccrm register to the ccrm buffer register conflicts with writing the tpnccrm register. ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter ccr0 bu ffer regi s ter inttpncc0 s ign a l tpnccr1 regi s ter ccr1 bu ffer regi s ter inttpncc1 s ign a l topn1 pin o u tp u t extern a l trigger inp u t (tipn0 pin inp u t) topn0 pin o u tp u t ( s oftw a re trigger) d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01
437 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tpnccr1 register to 0000h. if the set value of the tpnccr0 register is ffffh, the inttpncc1 signal is generated periodically. to output a 100% waveform, set a value of (set value of tpnccr0 register + 1) to the tpnccr1 register. if the set value of the tpnccr0 register is ffffh, 100% output cannot be produced. co u nt clock 16- b it co u nter tpnce b it tpnccr0 regi s ter tpnccr1 regi s ter inttpncc0 s ign a l inttpncc1 s ign a l topn1 pin o u tp u t d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 co u nt clock 16- b it co u nter tpnce b it tpnccr0 regi s ter tpnccr1 regi s ter inttpncc0 s ign a l inttpncc1 s ign a l topn1 pin o u tp u t d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001
438 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (c) conflict between trigger detectio n and match with tpnccr1 register if the trigger is detected immediately after the inttpncc1 signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of the topn1 pin is asserted, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. if the trigger is detected immediately before the inttpncc1 signal is generated, the inttpncc1 signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. the output signal of the topn1 pin remains active. consequently, the active period of the pwm waveform is extended. 16- b it co u nter tpnccr1 regi s ter inttpncc1 s ign a l topn1 pin o u tp u t extern a l trigger inp u t (tipn0 pin inp u t) d 1 d 1 ? 1 0000 ffff 0000 s hortened 16- b it co u nter tpnccr1 regi s ter inttpncc1 s ign a l topn1 pin o u tp u t extern a l trigger inp u t (tipn0 pin inp u t) d 1 d 1 ? 2d 1 ? 1d 1 0000 ffff 0000 0001 extended
439 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (d) conflict between trigger detectio n and match with tpnccr0 register if the trigger is detected immediately after the inttpncc0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up. therefore, the active period of the topn1 pin is extended by time from generation of the inttpncc0 signal to trigger detection. if the trigger is detected immediately before the inttpncc0 signal is generated, the inttpncc0 signal is not generated. the 16-bit counter is cleared to 0000h, the topn1 pin is asserted, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. 16- b it co u nter tpnccr0 regi s ter inttpncc0 s ign a l topn1 pin o u tp u t extern a l trigger inp u t (tipn0 pin inp u t) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended 16- b it co u nter tpnccr0 regi s ter inttpncc0 s ign a l topn1 pin o u tp u t extern a l trigger inp u t (tipn0 pin inp u t) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 s hortened
440 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (e) generation timing of compare match interrupt request signal (inttpncc1) the timing of generation of the inttpncc1 signal in the external trigger pulse output mode differs from the timing of other inttpncc1 signals; the inttpncc1 signal is generated when the count value of the 16-bit counter matches the value of the tpnccr1 register. usually, the inttpncc1 signal is generated in synchronization with the next count up, after the count value of the 16-bit counter matches the value of the tpnccr1 register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of changing the output signal of the topn1 pin. co u nt clock 16- b it co u nter tpnccr1 regi s ter topn1 pin o u tp u t inttpncc1 s ign a l d 1 d 1 ? 1d 1 ? 1d 1 d 1 + 1 d 1 + 2
441 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 11.5.4 one-shot pulse output m ode (tpnmd2 to tpnmd0 = 011) in the one-shot pulse output mode, 16-bit timer/event counter p waits for a trigger when the tpnctl0.tpnce bit is set to 1. when the valid edge of an external trigger input is detected, 16-bit timer/event counter p starts counting, and outputs a one-shot pulse from the topn1 pin. instead of the external trigger, a software trigger can also be generated to output the pulse. when the software trigger is used, the topn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 11-18 configuration in one-shot pulse output mode ccr0 bu ffer regi s ter tpnce b it tpnccr0 regi s ter tpnccr1 regi s ter ccr1 bu ffer regi s ter cle a r m a tch s ign a l m a tch s ign a l inttpncc0 s ign a l o u tp u t controller (r s -ff) topn1 pin inttpncc1 s ign a l topn0 pin co u nt clock s election co u nt s t a rt control edge detector s oftw a re trigger gener a tion tipn0 pin tr a n s fer tr a n s fer s r o u tp u t controller (r s -ff) s r 16- b it co u nter
442 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 figure 11-19 basic timing in one-shot pulse output mode when the tpnce bit is set to 1, 16-bit timer/event counter p waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counting, and outputs a one-shot pulse from the topn1 pin. after the one-shot pulse is output, the 16-bit counter is set to ffffh, stops counting, and waits for a trigger. if a trigger is generated again while the one- shot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tpnccr1 register) count clock cycle active level width = (set value of tpnccr0 register ? set value of tpnccr1 register + 1) count clock cycle the compare match interrupt request signal inttpncc0 is generated when the 16-bit counter counts after its count value matches the value of the ccr0 buffer register. the compare match interrupt request signal inttpncc1 is generated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the valid edge of an external trigger input or setting the software trigger (tpnctl1.tpnest bit) to 1 is used as the trigger. ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter inttpncc0 s ign a l topn0 pin o u tp u t tpnccr1 regi s ter inttpncc1 s ign a l topn1 pin o u tp u t extern a l trigger inp u t (tipn0 pin inp u t) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 del a y (d 1 ) active level width (d 0 ? d 1 + 1) del a y (d 0 ) active level width (d 0 ? d 1 + 1) del a y (d 1 ) active level width (d 0 ? d 1 + 1)
443 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (1) setting of registers in one-shot pulse output mode (a) tmpn control register 0 (tpnctl0) note the setting is invalid when the tpnctl1.tpneee bit = 1. (b) tmpn control register 1 (tpnctl1) 0/1 0 0 0 0 tpnctl0 s elect co u nt clock note 0: s top co u nting 1: en ab le co u nting 0/1 0/1 0/1 tpnck s 2 tpnck s 1 tpnck s 0 tpnce 0 0/1 0/1 0 0 tpnctl1 0: oper a te on co u nt clock s elected b y tpnck s 0 to tpnck s 2 b it s 1: co u nt extern a l event inp u t s ign a l gener a te s oftw a re trigger when 1 i s written 011 tpnmd2 tpnmd1 tpnmd0 tpneee tpne s t 0, 1, 1: one- s hot p u l s e o u tp u t mode
444 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (c) tmpn i/o control register 0 (tpnioc0) (d) tmpn i/o control register 2 (tpnioc2) (e) tmpn counter read buffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare registers 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 1 - d 0 + 1) count clock cycle output delay period = d 1 count clock cycle note tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the one-shot pulse output mode. 0 0 0 0 0/1 tpnioc0 0: di sab le topn0 pin o u tp u t 1: en ab le topn0 pin o u tp u t s etting of o u tp u t level while oper a tion of topn0 pin i s di sab led 0: low level 1: high level 0: di sab le topn1 pin o u tp u t 1: en ab le topn1 pin o u tp u t s pecifie s a ctive level of topn1 pin o u tp u t 0: active-high 1: active-low 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin o u tp u t 16- b it co u nter ? when tpnol1 b it = 0 topn1 pin o u tp u t 16- b it co u nter ? when tpnol1 b it = 1 0 0 0 0 0/1 tpnioc2 s elect v a lid edge of extern a l trigger inp u t s elect v a lid edge of extern a l event co u nt inp u t 0/1 0/1 0/1 tpnee s 0 tpnet s 1 tpnet s 0 tpnee s 1
445 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (2) operation flow in one-shot pulse output mode figure 11-20 software processing flow in one-shot pulse output mode <1> <2> tpnce b it = 1 tpnce b it = 0 regi s ter initi a l s etting tpnctl0 (tpnck s 0 to tpnck s 2 b it s ) tpnctl1, tpnioc0, tpnioc2, tpnccr0, tpnccr1 initi a l s etting of the s e regi s ter s i s performed b efore s etting the tpnce b it to 1. the tpnck s 0 to tpnck s 2 b it s c a n b e s et a t the sa me time when co u nting h as b een s t a rted (tpnce b it = 1). trigger w a it s t a t us co u nt oper a tion i s s topped s ta rt s top <1> co u nt oper a tion s t a rt flow <2> co u nt oper a tion s top flow ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter inttpncc0 s ign a l tpnccr1 regi s ter inttpncc1 s ign a l topn1 pin o u tp u t extern a l trigger inp u t (tipn0 pin inp u t) d 1 d 0 d 0 d 1 d 1 d 0
446 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (3) operation timing in one-shot pulse output mode (a) note on rewriting tpnccrm register to change the set value of the tpnccrm register to a smaller value, stop counting once, and then change the set value. if the value of the tpnccrm register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when the tpnccr0 register is rewritten from d 00 to d 01 and the tpnccr1 register from d 10 to d 11 where d 00 > d 01 and d 10 > d 11 , if the tpnccr1 register is rewritten when the count value of the 16-bit counter is greater than d 11 and less than d 10 and if the tpnccr0 register is rewritten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter counts up to ffffh and then counts up again from 0000h. when the count value matches d 11 , the counter generates the inttpncc1 signal and asserts the topn1 pin. when the count value matches d 01 , the counter generates the inttpncc0 signal, deasserts the topn1 pin, and stops counting. therefore, the counter may output a pulse with a delay period or active period different from that of the one-shot pulse that is originally expected. ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter inttpncc0 s ign a l topn0 pin o u tp u t tpnccr1 regi s ter inttpncc1 s ign a l topn1 pin o u tp u t extern a l trigger inp u t (tipn0 pin inp u t) d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 del a y (d 10 ) active level width (d 00 ? d 10 + 1) del a y (d 10 ) active level width (d 00 ? d 10 + 1) del a y (10000h + d 11 ) active level width (d 01 ? d 11 + 1)
447 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (b) generation timing of compare match interrupt request signal (inttpncc1) the generation timing of the inttpncc1 signal in the one-shot pulse output mode is different from other inttpncc1 signals; the inttpncc1 signal is generated when the count value of the 16-bit counter matches the value of the tpnccr1 register. usually, the inttpncc1 signal is generated when the 16-bit counter counts up next time after its count value matches the value of the tpnccr1 register. in the one-shot pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the topn1 pin. co u nt clock 16- b it co u nter tpnccr1 regi s ter topn1 pin o u tp u t inttpncc1 s ign a l d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2
448 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 11.5.5 pwm output mode (tpnmd2 to tpnmd0 = 100) in the pwm output mode, a pwm waveform is output from the topn1 pin when the tpnctl0.tpnce bit is set to 1. in addition, a pulse with one cycle of the pwm waveform as half its cycle is output from the topn0 pin. figure 11-21 configuration in pwm output mode ccr0 bu ffer regi s ter tpnce b it tpnccr0 regi s ter 16- b it co u nter tpnccr1 regi s ter ccr1 bu ffer regi s ter cle a r m a tch s ign a l m a tch s ign a l inttpncc0 s ign a l o u tp u t controller (r s -ff) o u tp u t controller topn1 pin inttpncc1 s ign a l topn0 pin co u nt clock s election co u nt s t a rt control tr a n s fer tr a n s fer s r
449 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 figure 11-22 basic timing in pwm output mode when the tpnce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, starts counting, and outputs a pwm waveform from the topn1 pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tpnccr1 register) count clock cycle cycle = (set value of tpnccr0 register + 1) count clock cycle duty factor = (set value of tpnccr1 register)/(set value of tpnccr0 register + 1) the pwm waveform can be changed by rewriting the tpnccrm register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttpncc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bi t counter is cleared to 0000h. the compare match interrupt request signal inttpncc1 is generated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tpnccrm register is transferred to the ccrm buffer register when the count value of the 16-bit counter matches the value of the ccrm buffer register and the 16-bi t counter is cleared to 0000h. ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter ccr0 bu ffer regi s ter nttpncc0 s ign a l topn0 pin o u tp u t tpnccr1 regi s ter ccr1 bu ffer regi s ter inttpncc1 s ign a l topn1 pin o u tp u t d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) in a ctive period (d 00 ? d 10 + 1)
450 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (1) setting of registers in pwm output mode (a) tmpn control register 0 (tpnctl0) note the setting is invalid when the tpnctl1.tpneee bit = 1. (b) tmpn control register 1 (tpnctl1) (c) tmpn i/o control register 0 (tpnioc0) 0/1 0 0 0 0 tpnctl0 s elect co u nt clock note 0: s top co u nting 1: en ab le co u nting 0/1 0/1 0/1 tpnck s 2 tpnck s 1 tpnck s 0 tpnce 00000 tpnctl1 100 tpnmd2 tpnmd1 tpnmd0 tpneee tpne s t 1, 0, 0: pwm o u tp u t mode 0 0 0 0 0/1 tpnioc0 0: di sab le topn0 pin o u tp u t 1: en ab le topn0 pin o u tp u t s etting of o u tp u t level while oper a tion of topn0 pin i s di sab led 0: low level 1: high level 0: di sab le topn1 pin o u tp u t 1: en ab le topn1 pin o u tp u t s pecifie s a ctive level of topn1 pin o u tp u t 0: active-high 1: active-low 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin o u tp u t 16- b it co u nter ? when tpnol1 b it = 0 topn1 pin o u tp u t 16- b it co u nter ? when tpnol1 b it = 1
451 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (d) tmpn i/o control register 2 (tpnioc2) (e) tmpn counter read buffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare registers 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle note tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the pwm output mode. 0 0 0 0 0/1 tpnioc2 s elect v a lid edge of extern a l event co u nt inp u t. 0/1 0 0 tpnee s 0 tpnet s 1 tpnet s 0 tpnee s 1
452 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (2) operation flow in pwm output mode figure 11-23 software processing flow in pwm output mode (1/2) ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter ccr0 bu ffer regi s ter inttpncc0 s ign a l topn0 pin o u tp u t tpnccr1 regi s ter ccr1 bu ffer regi s ter inttpncc1 s ign a l topn1 pin o u tp u t d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <2> < 3 > <4> <5> <1>
453 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 figure 11-24 software processing flow in pwm output mode (1/2) tpnce b it = 1 s etting of tpnccr0 regi s ter regi s ter initi a l s etting tpnctl0 (tpnck s 0 to tpnck s 2 b it s ) tpnctl1, tpnioc0, tpnioc2, tpnccr0, tpnccr1 initi a l s etting of the s e regi s ter s i s performed b efore s etting the tpnce b it to 1. the tpnck s 0 to tpnck s 2 b it s c a n b e s et a t the sa me time when co u nting i s en ab led (tpnce b it = 1). tpnccr1 write proce ss ing i s nece ssa ry only when the s et cycle i s ch a nged. when the co u nter i s cle a red a fter s etting, the v a l u e of the tpnccrm regi s ter i s tr a n s ferred to the ccrm bu ffer regi s ter. s ta rt s etting of tpnccr1 regi s ter <1> co u nt oper a tion s t a rt flow <2> tpnccr0, tpnccr1 regi s ter s etting ch a nge flow s etting of tpnccr0 regi s ter when the co u nter i s cle a red a fter s etting, the v a l u e of the tpnccrm regi s ter i s tr a n s ferred to the ccrm bu ffer regi s ter. s etting of tpnccr1 regi s ter <4> tpnccr0, tpnccr1 regi s ter s etting ch a nge flow only writing of the tpnccr1 regi s ter m us t b e performed when the s et d u ty f a ctor i s ch a nged. when the co u nter i s cle a red a fter s etting, the v a l u e of comp a re regi s ter m i s tr a n s ferred to the ccrm bu ffer regi s ter. s etting of tpnccr1 regi s ter < 3 > tpnccr0, tpnccr1 regi s ter s etting ch a nge flow tpnce b it = 0 co u nting i s s topped. s top <5> co u nt oper a tion s top flow
454 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (3) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tpnccr1 register last. rewrite the tpnccrm register after writing the tpnccr1 register after the inttpncc1 signal is detected. to transfer data from the tpnccrm register to the ccrm buffer register, the tpnccr1 register must be written. to change both the cycle and active level of the pwm waveform at this time, first set the cycle to the tpnccr0 register and then set the active level to the tpnccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tpnccr0 register, and then write the same value to the tpnccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tpnccr1 register has to be set. after data is written to the tpnccr1 register, the value written to the tpnccrm register is transferred to the ccrm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the tpnccr0 or tpnccr1 register again after writing the tpnccr1 register once, do so after the inttpncc0 signal is generated. otherwise, the value of the ccrm buffer register may become undefined because the timing of transferring data from the tpnccrm register to the ccrm buffer register conflicts with writing the tpnccrm register. ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter ccr0 bu ffer regi s ter tpnccr1 regi s ter ccr1 bu ffer regi s ter topn1 pin o u tp u t inttpncc0 s ign a l d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01
455 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tpnccr1 register to 0000h. if the set value of the tpnccr0 register is ffffh, the inttpncc1 signal is generated periodically. to output a 100% waveform, set a value of (set value of tpnccr0 register + 1) to the tpnccr1 register. if the set value of the tpnccr0 register is ffffh, 100% output cannot be produced. co u nt clock 16- b it co u nter tpnce b it tpnccr0 regi s ter tpnccr1 regi s ter inttpncc0 s ign a l inttpncc1 s ign a l topn1 pin o u tp u t d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 co u nt clock 16- b it co u nter tpnce b it tpnccr0 regi s ter tpnccr1 regi s ter inttpncc0 s ign a l inttpncc1 s ign a l topn1 pin o u tp u t d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001
456 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (c) generation timing of compare match interrupt request signal (inttpncc1) the timing of generation of the inttpncc1 signal in the pwm output mode differs from the timing of other inttpncc1 signals; the inttpncc1 signal is generated when the count value of the 16-bit counter matches the value of the tpnccr1 register. usually, the inttpncc1 signal is generated in synchronization with the next counting up after the count value of the 16-bit counter matches the value of the tpnccr1 register. in the pwm output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the output signal of the topn1 pin. co u nt clock 16- b it co u nter tpnccr1 regi s ter topn1 pin o u tp u t inttpncc1 s ign a l d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2
457 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 11.5.6 free-running timer mode (tpnmd2 to tpnmd0 = 101) in the free-running timer mode, 16-bit timer/event counter p starts counting when the tpnctl0.tpnce bit is set to 1. at this time, the tpnccrm register can be used as a compare register or a capture register, depending on the setting of the tpnopt0.tpnccs0 and tpnopt0.tpnccs1 bits. figure 11-25 configuration in free-running timer mode tpnccr0 regi s ter (c a pt u re) tpnce b it tpnccr1 regi s ter (comp a re) 16- b it co u nter tpnccr1 regi s ter (comp a re) tpnccr0 regi s ter (c a pt u re) o u tp u t controller tpncc s 0, tpncc s 1 b it s (c a pt u re/comp a re s election) topn0 pin o u tp u t o u tp u t controller topn1 pin o u tp u t edge detector co u nt clock s election edge detector edge detector tipn0 pin (extern a l event co u nt inp u t/ c a pt u re trigger inp u t) tipn1 pin (c a pt u re trigger inp u t) intern a l co u nt clock 0 1 0 1 inttpnov s ign a l inttpncc1 s ign a l inttpncc0 s ign a l
458 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 when the tpnce bit is set to 1, 16-bit timer/event counter p starts counting, and the output signals of the topn0 and topn1 pins are inverted. when the count value of the 16-bit counter later matches the set value of the tpnccrm register, a compare match interrupt request signal (inttpnccm) is generated, and the output signal of the topnm pin is inverted. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh , it generates an overflow interrupt request signal (inttpnov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tpnopt0.tpnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. the tpnccrm register can be rewritten while the counter is operating. if it is rewritten, the new value is reflected at that time, and compared with the count value. figure 11-26 basic timing in free-runni ng timer mode (compare function) ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter inttpncc0 s ign a l topn0 pin o u tp u t tpnccr1 regi s ter inttpncc1 s ign a l topn1 pin o u tp u t inttpnov s ign a l tpnovf b it d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cle a red to 0 b y clr in s tr u ction cle a red to 0 b y clr in s tr u ction cle a red to 0 b y clr in s tr u ction cle a red to 0 b y clr in s tr u ction
459 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 when the tpnce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tipnm pin is detected, the count value of the 16-bit counter is stored in the tpnccrm register, and a capture interrupt request signal (inttpnccm) is generated. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh , it generates an overflow interrupt request signal (inttpnov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tpnopt0.tpnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. figure 11-27 basic timing in free-runni ng timer mode (capture function) ffffh 16- b it co u nter 0000h tpnce b it tipn0 pin inp u t tpnccr0 regi s ter inttpncc0 s ign a l tipn1 pin inp u t tpnccr1 regi s ter inttpncc1 s ign a l inttpnov s ign a l tpnovf b it d 00 d 01 d 02 d 0 3 d 10 d 00 d 01 d 02 d 0 3 d 11 d 12 d 1 3 d 10 d 11 d 12 d 1 3 cle a red to 0 b y clr in s tr u ction cle a red to 0 b y clr in s tr u ction cle a red to 0 b y clr in s tr u ction
460 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (1) register setting in free-running timer mode (a) tmpn control register 0 (tpnctl0) note the setting is invalid when the tpnctl1.tpneee bit = 1 (b) tmpn control register 1 (tpnctl1) (c) tmpn i/o control register 0 (tpnioc0) 0/1 0 0 0 0 tpnctl0 s elect co u nt clock note 0: s top co u nting 1: en ab le co u nting 0/1 0/1 0/1 tpnck s 2 tpnck s 1 tpnck s 0 tpnce 0 0 0/1 0 0 tpnctl1 101 tpnmd2 tpnmd1 tpnmd0 tpneee tpne s t 1, 0, 1: free-r u nning mode 0: oper a te with co u nt clock s elected b y tpnck s 0 to tpnck s 2 b it s 1: co u nt on extern a l event co u nt inp u t s ign a l 0 0 0 0 0/1 tpnioc0 0: di sab le topn0 pin o u tp u t 1: en ab le topn0 pin o u tp u t s etting of o u tp u t level with oper a tion of topn0 pin di sab led 0: low level 1: high level 0: di sab le topn1 pin o u tp u t 1: en ab le topn1 pin o u tp u t s etting of o u tp u t level with oper a tion of topn1 pin di sab led 0: low level 1: high level 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1
461 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (d) tmpn i/o control register 1 (tpnioc1) (e) tmpn i/o control register 2 (tpnioc2) (f) tmpn option register 0 (tpnopt0) (g) tmpn counter read buffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (h) tmpn capture/compare registers 0 and 1 (tpnccr0 and tpnccr1) these registers function as capture registers or compare registers depending on the setting of the tpnopt0.tpnccsm bit. when the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the tipnm pin is detected. when the registers function as compare registers and when d m is set to the tpnccrm register, the inttpnccm signal is generated when the counter reaches (d m + 1), and the output signal of the topnm pin is inverted. 0 0 0 0 0/1 tpnioc1 s elect v a lid edge of tipn0 pin inp u t s elect v a lid edge of tipn1 pin inp u t 0/1 0/1 0/1 tpni s 2 tpni s 1 tpni s 0 tpni s3 0 0 0 0 0/1 tpnioc2 s elect v a lid edge of extern a l event co u nt inp u t 0/1 0 0 tpnee s 0 tpnet s 1 tpnet s 0 tpnee s 1 0 0 0/1 0/1 0 tpnopt0 overflow fl a g s pecifie s if tpnccr0 regi s ter f u nction s as c a pt u re or comp a re regi s ter s pecifie s if tpnccr1 regi s ter f u nction s as c a pt u re or comp a re regi s ter 0 0 0/1 tpncc s 0 tpnovf tpncc s 1
462 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (2) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 11-28 software processing flow in fr ee-running timer mode (compare function) (1/2) ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter inttpncc0 s ign a l topn0 pin o u tp u t tpnccr1 regi s ter inttpncc1 s ign a l topn1 pin o u tp u t inttpnov s ign a l tpnovf b it d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cle a red to 0 b y clr in s tr u ction cle a red to 0 b y clr in s tr u ction cle a red to 0 b y clr in s tr u ction <1> <2> <2> <2> < 3 >
463 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 figure 11-29 software processing flow in fr ee-running timer mode (compare function) (2/2) tpnce b it = 1 re a d tpnopt0 regi s ter (check overflow fl a g). regi s ter initi a l s etting tpnctl0 (tpnck s 0 to tpnck s 2 b it s ) tpnctl1, tpnioc0, tpnioc2, tpnopt0, tpnccr0, tpnccr1 initi a l s etting of the s e regi s ter s i s performed b efore s etting the tpnce b it to 1. the tpnck s 0 to tpnck s 2 b it s c a n b e s et a t the sa me time when co u nting h as b een s t a rted (tpnce b it = 1). s ta rt exec u te in s tr u ction to cle a r tpnovf b it (clr tpnovf). <1> co u nt oper a tion s t a rt flow <2> overflow fl a g cle a r flow tpnce b it = 0 co u nter i s initi a lized a nd co u nting i s s topped b y cle a ring tpnce b it to 0. s top < 3 > co u nt oper a tion s top flow tpnovf b it = 1 no ye s
464 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (b) when using capture/compare register as capture register figure 11-30 software processing flow in free-running timer mode (capture function) (1/2) ffffh 16- b it co u nter 0000h tpnce b it tipn0 pin inp u t tpnccr0 regi s ter inttpncc0 s ign a l tipn1 pin inp u t tpnccr1 regi s ter inttpncc1 s ign a l inttpnov s ign a l tpnovf b it d 00 0000 0000 d 01 d 02 d 0 3 d 10 d 00 d 01 d 02 d 0 3 d 11 d 12 d 10 0000 d 11 d 12 0000 cle a red to 0 b y clr in s tr u ction cle a red to 0 b y clr in s tr u ction < 3 > <1> <2> <2>
465 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 figure 11-31 software processing flow in free-running timer mode (capture function) (2/2) tpnce b it = 1 re a d tpnopt0 regi s ter (check overflow fl a g). regi s ter initi a l s etting tpnctl0 (tpnck s 0 to tpnck s 2 b it s ) tpnctl1, tpnioc1, tpnopt0 initi a l s etting of the s e regi s ter s i s performed b efore s etting the tpnce b it to 1. the tpnck s 0 to tpnck s 2 b it s c a n b e s et a t the sa me time when co u nting h as b een s t a rted (tpnce b it = 1). s ta rt exec u te in s tr u ction to cle a r tpnovf b it (clr tpnovf). <1> co u nt oper a tion s t a rt flow <2> overflow fl a g cle a r flow tpnce b it = 0 co u nter i s initi a lized a nd co u nting i s s topped b y cle a ring tpnce b it to 0. s top < 3 > co u nt oper a tion s top flow tpnovf b it = 1 no ye s
466 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (3) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter p is used as an interval timer with the tpnccrm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the inttpnccm signal has been detected. when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the corresponding tpnccrm register must be re-set in the interrupt servicing that is executed when the inttpnccm signal is detected. the set value for re-setting the tpnccrm register can be calculated by the following expression, where ?d m ? is the interval period. compare register default value: d m ? 1 value set to compare register second and subsequent time: previous set value + d m (if the calculation result is greater than ffffh, subtract 10000h from the result and set this value to the register.) ffffh 16- b it co u nter 0000h tpnce b it tpnccr0 regi s ter inttpncc0 s ign a l topn pin o u tp u t tpnccr1 regi s ter inttpncc1 s ign a l topn1 pin o u tp u t d 00 d 01 d 02 d 0 3 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 1 3 d 02 d 0 3 d 11 d 10 d 12 d 1 3 d 14 interv a l period (d 10 + 1) interv a l period (10000h + d 11 ? d 10 ) interv a l period (10000h + d 12 ? d 11 ) interv a l period (10000h + d 1 3 ? d 12 ) interv a l period (d 00 + 1) interv a l period (10000h + d 01 ? d 00 ) interv a l period (d 02 ? d 01 ) interv a l period (10000h + d 0 3 ? d 02 ) interv a l period (10000h + d 04 ? d 0 3 )
467 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (b) pulse width measurement with capture register when pulse width measurement is performed with the tpnccrm register used as a capture register, software processing is necessary for reading the capture register each time the inttpnccm signal has been detected and for calculating an interval. when executing pulse width measurement in the free-running timer mode, two pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be calculated by reading the value of the tpnccrm register in synchronization with the inttpnccm signal, and calculating the difference between the read value and the previously read value. ffffh 16- b it co u nter 0000h tpnce b it tipn0 pin inp u t tpnccr0 regi s ter inttpncc0 s ign a l tipn1 pin inp u t tpnccr1 regi s ter inttpncc1 s ign a l inttpnov s ign a l tpnovf b it 0000h d 00 d 01 d 02 d 0 3 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 1 3 d 02 d 0 3 d 10 0000h d 11 d 12 d 1 3 p u l s e interv a l (d 00 ) p u l s e interv a l (10000h + d 01 ? d 00 ) p u l s e interv a l (d 02 ? d 01 ) p u l s e interv a l (10000h + d 0 3 ? d 02 ) p u l s e interv a l (10000h + d 04 ? d 0 3 ) p u l s e interv a l (d 10 ) p u l s e interv a l (10000h + d 11 ? d 10 ) p u l s e interv a l (10000h + d 12 ? d 11 ) p u l s e interv a l (10000h + d 1 3 ? d 12 ) cle a red to 0 b y clr in s tr u ction cle a red to 0 b y clr in s tr u ction cle a red to 0 b y clr in s tr u ction
468 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. figure 11-32 example of incorrect processing when two capture registers are used the following problem may occur when two pulse widths are measured in the free-running timer mode. <1> read the tpnccr0 register (setting of the default value of the tipn0 pin input). <2> read the tpnccr1 register (setting of the default value of the tipn1 pin input). <3> read the tpnccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 - d 00 ). <4> read the tpnccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 - d 10 ) (incorrect). when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two capture registers. an example of how to use software is shown below. ffffh 16- b it co u nter 0000h tpnce b it tipn0 pin inp u t tpnccr0 regi s ter tipn1 pin inp u t tpnccr1 regi s ter inttpnov s ign a l tpnovf b it d 00 d 01 d 10 d 11 d 10 <1> <2> < 3 > <4> d 00 d 11 d 01
469 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 figure 11-33 example when two capture registers are used (using overflow interrupt) note the tpnovf0 and tpnovf1 flags are set on the internal ram by software. <1> read the tpnccr0 register (setting of the default value of the tipn0 pin input). <2> read the tpnccr1 register (setting of the default value of the tipn1 pin input). <3> an overflow occurs. set the tpnovf0 and tpnovf1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tpnccr0 register. read the tpnovf0 flag. if the tpnovf0 flag is 1, clear it to 0. because the tpnovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 - d 00 ). <5> read the tpnccr1 register. read the tpnovf1 flag. if the tpnovf1 flag is 1, clear it to 0 (the tpnovf0 flag is cleared in <4>, and the tpnovf1 flag remains 1). because the tpnovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 - d 10 ) (correct). <6> same as <3> ffffh 16- b it co u nter 0000h tpnce b it inttpnov s ign a l tpnovf b it tpnovf0 fl a g note tipn0 pin inp u t tpnccr0 regi s ter tpnovf1 fl a g note tipn1 pin inp u t tpnccr1 regi s ter d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> < 3 > <4> d 00 d 11 d 01
470 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 figure 11-34 example when two capture registers are used (without using overflow interrupt) note the tpnovf0 and tpnovf1 flags are set on the internal ram by software. <1> read the tpnccr0 register (setting of the default value of the tipn0 pin input). <2> read the tpnccr1 register (setting of the default value of the tipn1 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tpnccr0 register. read the overflow flag. if the overflow flag is 1, set only the tpnovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 - d 00 ). <5> read the tpnccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tpnovf1 flag. if the tpnovf1 flag is 1, clear it to 0. because the tpnovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 - d 10 ) (correct). <6> same as <3> ffffh 16- b it co u nter 0000h tpnce b it inttpnov s ign a l tpnovf b it tpnovf0 fl a g note tipn0 pin inp u t tpnccr0 regi s ter tpnovf1 fl a g note tipn1 pin inp u t tpnccr1 regi s ter d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> < 3 > <4> d 00 d 11 d 01
471 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. first, an example of incorrect processing is shown below. figure 11-35 example of incorrect processing when capture trigger interval is long the following problem may occur when long pulse width is measured in the free-running timer mode. <1> read the tpnccrm register (setting of the default value of the tipnm pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tpnccrm register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d m1 - d m0 ) (incorrect). actually, the pulse width must be (20000h + d m1 - d m0 ) because an overflow occurs twice. if an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next. ffffh 16- b it co u nter 0000h tpnce b it tipnm pin inp u t tpnccrm regi s ter inttpnov s ign a l tpnovf b it d m0 d m1 d m0 d m1 <1> <2> < 3 > <4> 1 cycle of 16- b it co u nter p u l s e width
472 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 figure 11-36 example when capture trigger interval is long note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tpnccrm register (setting of the default value of the tipnm pin input). <2> an overflow occurs. increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tpnccrm register. read the overflow counter. when the overflow counter is ?n?, the pulse width can be calculated by (n 10000h + d m1 ? d m0 ). in this example, the pulse width is (20000h + d m1 ? d m0 ) because an overflow occurs twice. clear the overflow counter (0h). ffffh 16- b it co u nter 0000h tpnce b it tipnm pin inp u t tpnccrm regi s ter inttpnov s ign a l tpnovf b it overflow co u nter note d m0 d m1 1h 0h 2h 0h d m0 d m1 <1> <2> < 3 > <4> 1 cycle of 16- b it co u nter p u l s e width
473 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tpnovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tpnopt0 register. to accurately detect an overflow, read the tpnovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction. (i) oper a tion to write 0 (witho u t conflict with s etting) (iii) oper a tion to cle a r to 0 (witho u t conflict with s etting) (ii) oper a tion to write 0 (conflict with s etting) (iv) oper a tion to cle a r to 0 (conflict with s etting) 0 write s ign a l overflow s et s ign a l regi s ter a cce ss s ign a l overflow fl a g (tpnovf b it) re a d write 0 write s ign a l overflow s et s ign a l regi s ter a cce ss s ign a l overflow fl a g (tpnovf b it) re a d write 0 write s ign a l overflow s et s ign a l 0 write s ign a l overflow s et s ign a l overflow fl a g (tpnovf b it) overflow fl a g (tpnovf b it) l h l
474 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 11.5.7 pulse width measurement mode (tpnmd2 to tpnmd0 = 110) in the pulse width measurement mode, 16-bit timer/event counter p starts counting when the tpnctl0.tpnce bit is set to 1. each time the valid edge input to the tipnm pin has been detected, the count value of the 16-bit counter is stored in the tpnccrm register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by reading the tpnccrm register after a capture interrupt request signal (inttpnccm) occurs. select either the tipn0 or tipn1 pin as the capture trigger input pin. specify ?no edge detected? by using the tpnioc1 register for the unused pins. when an external clock is used as the count clock, measure the pulse width of the tipn1 pin because the external clock is fixed to the tipn0 pin. at this time, clear the tpnioc1.tpnis1 and tpnioc1.tpnis0 bits to 00 (capture trigger input (tipn0 pin): no edge detected). figure 11-37 configuration in pulse width measurement mode tpnccr0 regi s ter (c a pt u re) tpnce b it tpnccr1 regi s ter (c a pt u re) edge detector co u nt clock s election edge detector edge detector tipn0 pin (extern a l event co u nt inp u t/c a pt u re trigger inp u t) tipn1 pin (c a pt u re trigger inp u t) intern a l co u nt clock cle a r inttpnov s ign a l inttpncc0 s ign a l inttpncc1 s ign a l 16- b it co u nter
475 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 figure 11-38 basic timing in pulse width measurement mode when the tpnce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tipnm pin is later detected, the count value of the 16-bit counter is stored in the tpnccrm register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttpnccm) is generated. the pulse width is calculated as follows. first pulse width = (d 0 + 1) count clock cycle second and subsequent pulse width = (d n - d n - 1 ) count clock cycle if the valid edge is not input to the tipnm pin even when the 16-bit counter counted up to ffffh, an overflow interrupt request signal (inttpnov) is generated at the next count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tpnopt0.tpnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pulse width can be calculated as follows. first pulse width = (d 0 + 10001h) count clock cycle second pulse width and on = (10000h + d n - d n - 1 ) count clock cycle ffffh 16- b it co u nter 0000h tpnce b it tipnm pin inp u t tpnccrm regi s ter inttpnccm s ign a l inttpnov s ign a l tpnovf b it d 0 0000h d 1 d 2 d 3 cle a red to 0 b y clr in s tr u ction
476 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (1) register setting in pulse width measurement mode (a) tmpn control register 0 (tpnctl0) note setting is invalid when the tpneee bit = 1. (b) tmpn control register 1 (tpnctl1) (c) tmpn i/o control register 1 (tpnioc1) 0/1 0 0 0 0 tpnctl0 s elect co u nt clock note 0: s top co u nting 1: en ab le co u nting 0/1 0/1 0/1 tpnck s 2 tpnck s 1 tpnck s 0 tpnce 0 0 0/1 0 0 tpnctl1 110 tpnmd2 tpnmd1 tpnmd0 tpneee tpne s t 1, 1, 0: p u l s e width me asu rement mode 0: oper a te with co u nt clock s elected b y tpnck s 0 to tpnck s 2 b it s 1: co u nt extern a l event co u nt inp u t s ign a l 0 0 0 0 0/1 tpnioc1 s elect v a lid edge of tipn0 pin inp u t s elect v a lid edge of tipn1 pin inp u t 0/1 0/1 0/1 tpni s 2 tpni s 1 tpni s 0 tpni s3
477 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (d) tmpn i/o control register 2 (tpnioc2) (e) tmpn option register 0 (tpnopt0) (f) tmpn counter read buffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (g) tmpn capture/compare registers 0 and 1 (tpnccr0 and tpnccr1) these registers store the count value of the 16-bit counter when the valid edge input to the tipnm pin is detected. note tmpn i/o control register 0 (tpnioc0) is not used in the pulse width measurement mode. 0 0 0 0 0/1 tpnioc2 s elect v a lid edge of extern a l event co u nt inp u t 0/1 0 0 tpnee s 0 tpnet s 1 tpnet s 0 tpnee s 1 00000 tpnopt0 overflow fl a g 0 0 0/1 tpncc s 0 tpnovf tpncc s 1
478 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 (2) operation flow in pulse width measurement mode figure 11-39 software processing flow in pulse width measurement mode <1> <2> s et tpnctl0 regi s ter (tpnce b it = 1) tpnce b it = 0 regi s ter initi a l s etting tpnctl0 (tpnck s 0 to tpnck s 2 b it s ), tpnctl1, tpnioc1, tpnioc2, tpnopt0 initi a l s etting of the s e regi s ter s i s performed b efore s etting the tpnce b it to 1. the tpnck s 0 to tpnck s 2 b it s c a n b e s et a t the sa me time when co u nting h as b een s t a rted (tpnce b it = 1). the co u nter i s initi a lized a nd co u nting i s s topped b y cle a ring the tpnce b it to 0. s ta rt s top <1> co u nt oper a tion s t a rt flow <2> co u nt oper a tion s top flow ffffh 16- b it co u nter 0000h tpnce b it tipn0 pin inp u t tpnccr0 regi s ter inttpncc0 s ign a l d 0 0000h 0000h d 1 d 2
479 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 (3) operation timing in pulse width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tpnovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tpnopt0 register. to accurately detect an overflow, read the tpnovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction. (i) oper a tion to write 0 (witho u t conflict with s etting) (iii) oper a tion to cle a r to 0 (witho u t conflict with s etting) (ii) oper a tion to write 0 (conflict with s etting) (iv) oper a tion to cle a r to 0 (conflict with s etting) 0 write s ign a l overflow s et s ign a l regi s ter a cce ss s ign a l overflow fl a g (tpnovf b it) re a d write 0 write s ign a l overflow s et s ign a l regi s ter a cce ss s ign a l overflow fl a g (tpnovf b it) re a d write 0 write s ign a l overflow s et s ign a l 0 write s ign a l overflow s et s ign a l overflow fl a g (tpnovf b it) overflow fl a g (tpnovf b it) l h l
480 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00 11.5.8 timer output operations the following table shows the operations and output levels of the topn0 and topn1 pins. table 11-11 timer output control in each mode operation mode topn1 pin topn0 pin interval timer mode square wave output external event count mode square wave output ? external trigger pulse output mode external trigger pulse output square wave output one-shot pulse output mode one-shot pulse output pwm output mode pwm output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode ? table 11-12 truth table of topn0 and topn1 pins under control of timer output control bits tpnioc0.tpnolm bit tpnioc0.tpnoem bit tpnctl0.tpnce bit level of topnm pin 00 low-level output 1 0 low-level output 1 low level immediately before counting, high level after counting is started 10 high-level output 1 0 high-level output 1 high level immediately before counting, low level after counting is started
481 16-bit timer/event counter p (tmp) chapter 11 user?s manual u17566ee5v1um00 11.6 operating precautions 11.6.1 capture operation in pulse width measurement and free- running mode when the capture operation is used in pulse width measurement or free-run- ning mode the first captured counter value of the capture registers tpnccr0/ tpnccr, i.e. after the timer is enabled (tpnctl0.tpnce = 1), may be ffff h instead of 0000 h if the chosen count clock of the tmp is not the maximum, i.e. if tpnctl0.tpncks[2:0] 0. 11.6.2 count jitter for pclk4 to pclk7 count clocks when specifying pclk4 to pclk7 as the count clock, a jitter of maximum 1 period of pclk0 may be applied to the counter?s count clock input.
482 chapter 11 16-bit timer/event counter p (tmp) user?s manual u17566ee5v1um00
483 user?s manual u17566ee5v1um00 chapter 12 16-bit inte rval timer z (tmz) timer z (tmz) is a general purpose 16-bit timer/counter. the v850e/dx3 microcontrollers have following instances of the general purpose timer z: throughout this chapter, the individual instances of timer z are identified by ?n?, for example tmzn, or tznctl for the tmzn control register. 12.1 overview each timer z has one down-counter. when the counter reaches zero, the timer generates the maskable interrupt inttznuv. the tmz can be used as: ? interval timer ? free running timer features summary special features of the tmz are: ? one of six peripheral clocks can be selected ? one reload register ? two readable counter registers ? when the device is in debug mode, the timer can be stopped at breakpoint ? tmz0, tmz1, and tmz2 can be used for triggering the dma controller. ? tmz5 can be used for triggering the a/d converter. ? all tmzn can be optionally stopped when a breakpoint is hit during debugging (refer to ?on-chip debug unit? on page 969 ). tmz pd70f3427, pd70f3426a pd70f3425, pd70f3424 pd70f3423, pd70f3422 pd70f3421 instances 10 6 names tmz0 to tmz9 tmz0 to tmz5
484 chapter 12 16-bit interval timer z (tmz) user?s manual u17566ee5v1um00 12.1.1 description the tmz has no external connections. it is built up as illustrated in the following figure. figure 12-1 block diagram of timer z (tmzn) the control register tznctl allows you to choose the count clock cntclk and to enable the timer. the latter is done by setting tznctl.tzce to 1. as soon as the timer is enabled, it is possible to write a start value to the reload register tznr. 12.1.2 principle of operation when it is enabled, the counter starts as soon as a non-zero value is written to the reload register tznr and copied to the reload buffer. when the counter reaches zero, it generates an inttznuv interrupt, reloads its start value from the reload buffer, and continues counting. two read-only registers (tzncnt0 and tzncnt1) provide the updated counter value. for details about these registers please refer to ?tzncnt0 - tmzn synchronized counter register? on page 487 and ?tzncnt1 - tmzn non-synchronized counter register? on page 488 . s elector 16- b it down co u nter tzncnt tznr relo a d bu ffer tznctl.tzce cntclk pclk4 (1 mhz) pclk7 (125 khz) pclk9 ( 3 1.250 khz) pclk2 (4 mhz) pclk5 (0.5 mhz) tzck s 2 tznctl tzck s 1 tzck s 0 intern a l bus inttznuv tzncnt0 tzncnt1
485 16-bit interval timer z (tmz) chapter 12 user?s manual u17566ee5v1um00 12.2 tmz registers each timer z is controlled and operated by means of the following four registers: table 12-2 base addresses of timer z table 12-1 timer z registers overview register name shortcut address timer z synchronized read register tzncnt0 timer z non-synchronized read register tzncnt1 + 2 h timer z reload register tznr + 4 h timer z control register tznctl + 6 h timer base address tmz0 ffff f600 h tmz1 ffff f608 h tmz2 ffff f610 h tmz3 ffff f618 h tmz4 ffff f620 h tmz5 ffff f628 h tmz6 ffff f630 h tmz7 ffff f638 h tmz8 ffff f640 h tmz9 ffff f648 h
486 chapter 12 16-bit interval timer z (tmz) user?s manual u17566ee5v1um00 (1) tznctl - tmzn timer control register the 8-bit tznctl register controls the operation of the timer z. access this register can be read/written in 8-bit or 1-bit units. address + 6 h initial value 00 h . this register is cleared by any reset. note change bits tznctl.tzcks[2:0] only when tznctl.tzce = 0. when tznctl.tzce = 0, it is possible to select the clock and enable the counter with one write operation. 76543 2 1 0 tzce 0 0 0 0 tzcks2 tzcks1 tzcks0 r/wrrrrr/wr/wr/w table 12-3 tznctl register contents bit position bit name function 7 tzce timer z counter enable: 0: disable count operation (the timer stops immediately with the count value 0000 h and does not operate). 1: enable count operation (the timer starts when a non-zero start value is written to the register tznr after tznctl.tzce=1). 2 to 0 tzcks[2:0] selects the counter clock cntclk: tzcks2 tzcks1 tzcks0 counter clock selection 000 pclk2 (4 mhz) 010 pclk4 (1 mhz) 011 pclk5 (0.5 mhz) 100 pclk7 (0.125 mhz) 1 0 1 pclk9 (31.250 khz) others than above setting prohibited
487 16-bit interval timer z (tmz) chapter 12 user?s manual u17566ee5v1um00 (2) tzncnt0 - tmzn synchronized counter register the tzncnt0 register is the synchronized register that can be used to read the present value of the 16-bit counter. ?synchronized? means that the read access via the internal bus is synchronized with the maximum counter clock (pclk2). the synchronization process may cause a delay, but the resulting value is reliable. access this register is read-only, in 16-bit units. address of tmzn initial value 0000 h . this register is cleared by any reset and when tznctl.tzce = 0. caution reading tzncnt0 immediately after start of the counter by setting tznr > 0 may return 0000 h instead of the correct counter value. refer to (4) ?tznr - reload register? for details. 1514131211109876543210 updated counter value (synchronized) r
488 chapter 12 16-bit interval timer z (tmz) user?s manual u17566ee5v1um00 (3) tzncnt1 - tmzn non-synchronized counter register the tzncnt1 register is the non-synchronized register that can be used to read the present value of the corresponding 16-bit counter. ?non-synchronized? means that the read access via the internal bus is not synchronized with the counter clock. it returns the instantaneous value immediately, with the risk that this value is just being updated by the counter and therefore in doubt. access this register is read-only, in 16-bit units. address + 2 h initial value 0000 h . this register is cleared by any reset and when tznctl.tzce = 0. note the value read from this register can be incorrect, because the read access is not synchronized with the counter clock. therefore, this register shall be read multiple times within one period of the counter clock cycle. if the difference between the first and the second value is not greater than one, you can consider the second value to be correct. if the difference between the two values is greater than one, you have to read the register a third time and compare the third value with the second. again, the difference must not be greater than one. if the read accesses do not happen within one period of the counter clock cycle, the difference between the last two values will usually be greater than one. in this case, you can only repeat the procedure or estimate the updated counter value. caution reading tzncnt1 immediately after start of the counter by setting tznr > 0 may return 0000 h instead of the correct counter value. refer to (4) ?tznr - reload register? for details. 1514131211109876543210 instantaneous counter value (non-synchronized) r
489 16-bit interval timer z (tmz) chapter 12 user?s manual u17566ee5v1um00 (4) tznr - reload register the tznr register is a dedicated register for setting the reload value of the corresponding counter. access this register can be read/written in 16-bit units. address + 4 h initial value 0000 h . this register is cleared by any reset and when tznctl.tzce = 0. note 1. tznr can only be written when tznctl.tzce = 1. 2. the load value must be non-zero (0001 h ? ffff h ). 3. to operate the timer in free running mode, set tznr to ffff h . 4. the first interval after starting the counter can require additional clock cycles. for details refer to ?timer start and stop? on page 491 . 5. transfer of the tznr content after writing to tznr requires additional clock cycles, until the value is set to the counter register tzncnt. thus during that transfer time t trans reading of tzncnt0 respectively tzncnt1 returns 0000 h instead of the correct value. the transfer time t trans depends on the chosen count clock and are given in ta b l e 1 2 - 4 . 1514131211109876543210 down-counter load value r/w table 12-4 transfer times t trans of tznr to tzncnt tznctl.tzcks t cntclk period tznr to tzncnt transfer time t trans minimum maximum 000 b t pclk2 t pclk2 t pclk2 010 b 4 x t pclk2 5 x t pclk2 9 x t pclk2 011 b 8 x t pclk2 9 x t pclk2 17 x t pclk2 100 b 32 x t pclk2 33 x t pclk2 65 x t pclk2 101 b 128 x t pclk2 128 x t pclk2 257 x t pclk2
490 chapter 12 16-bit interval timer z (tmz) user?s manual u17566ee5v1um00 12.3 timing the contents of the reload register tznr can be changed at any time, provided the timer is enabled. the contents is then copied to the reload buffer. however, the counter reloads its start value from the buffer when the counter reaches 0. caution when specifying pclk4, plck5, pclk7 or pclk9 as the count clock, a jitter of maximum 1 period of pclk2 may be applied to the tzncnt counter?s count clock input. 12.3.1 steady operation steady operation is illustrated in the following figure. figure 12-2 reload timing and interrupt generation d0 and d1 are two different reload values. note that there is a delay between writing to tznr and making the data available in the reload buffer, depending on the previous reload value and the chosen count clock. d 0 d 0 d 1 d 1 d 0 d 0 d 0 d 1 d 0 d 1 d 0 0000 h 16 - bit down counter value reload buffer tznr inttznuv
491 16-bit interval timer z (tmz) chapter 12 user?s manual u17566ee5v1um00 12.3.2 timer start and stop (1) timer z start the timer tzn is enabled by setting tznctl.tzce to 1. the subsequent write access to register tznr with non-zero data starts the timer. after that, it is prepared to load the value written to register tznr into the reload buffer and the counter. the interval time, i.e. the time between the inttznuv interrupts, depends on the chosen count clock t cntclk (selected by tznctl.tzcks) and calculates to t interval = ([tznr] + 1) t cntclk however the time of the first interval after starting the counter by setting tznr > 0 may be longer than the steady intervals afterwards. the length of the first interval also depends on whether the counter has already been enabled a certain time before it?s started. in the following the interval times for both cases are given as a multiple of t pclk2 , the period of the pclk2 input clock. t acmin , t acmax since the access time to the tznr register adds also to the uncertainty of the first interval duration, the below tables contain two values, which are calculated as follows: ?t acmin = (suwl + vswl + 3) x 1/f vbclk ?t acmax = [2 x (suwl + vswl) + 4.5] x 1/f vbclk the values suwl and vswl depend on the chosen cpu system clock vbclk and are set up in the vswc register (refer to ?bus and memory control (bcu, memc)? on page 255 ). note that the above access times assume that the npb bus is not occupied and the write access to tznr is immediately passed to the timer z.
492 chapter 12 16-bit interval timer z (tmz) user?s manual u17566ee5v1um00 timer enabled table 12-5 shows the interval times under following conditions: ? timer is enabled by tznctl.tzce = 1 ? timer is started by setting tznr > 0 after at least 2 pclk2 clock periods after timer enable timer disabled table 12-6 shows the interval times under following conditions: ? timer disabled: tznctl.tzce = 0 ? timer is enabled by tznctl.tzce = 1 ? timer is started by setting tznr > 0 immediately after enable, i.e. within 2 pclk2 clock periods after timer enable (2) timer z stop the timer stops when tznctl.tzce is cleared. this write access is not synchronized. the timer is immediately stopped, and its registers are reset. table 12-5 tmz interval times (timer enabled since minimum 2 pclk2 clocks) tznctl .tzcks t cntclk period 1st interval following intervals minimum maximum 000 b t pclk2 t acmin + ([tznr]+2) x t pclk2 t acmax + ([tznr]+3) x t pclk2 ([tznr]+1) x t pclk2 010 b 4 x t pclk2 t acmin + (4[tznr]+6) x t pclk2 t acmax + (4[tznr]+11) x t pclk2 4 x ([tznr]+1) x t pclk2 011 b 8 x t pclk2 t acmin + (8[tznr]+10) x t pclk2 t acmax + (8[tznr]+19) x t pclk2 8 x ([tznr]+1) x t pclk2 100 b 32 x t pclk2 t acmin + (32[tznr]+34) x t pclk2 t acmax + (32[tznr]+67) x t pclk2 32 x ([tznr]+1) x t pclk2 101 b 128 x t pclk2 t acmin + (128[tznr]+130) x t pclk2 t acmax + (128[tznr]+259) x t pclk2 128 x ([tznr]+1) x t pclk2 table 12-6 tmz interval times (timer started within 2 pclk2 clocks after enable) tznctl .tzcks t cntclk period 1st interval following intervals minimum maximum 000 b t pclk2 t acmin + ([tznr]+4.5) x t pclk2 t acmax + ([tznr]+6.5) x t pclk2 ([tznr]+1) x t pclk2 010 b 4 x t pclk2 t acmin + (4[tznr]+7.5) x t pclk2 t acmax + (4[tznr]+13.5) x t pclk2 4 x ([tznr]+1) x t pclk2 011 b 8 x t pclk2 t acmin + (8[tznr]+11.5) x t pclk2 t acmax + (8[tznr]+21.5) x t pclk2 8 x ([tznr]+1) x t pclk2 100 b 32 x t pclk2 t acmin + (32[tznr]+35.5) x t pclk2 t acmax + (32[tznr]+69.5) x t pclk2 32 x ([tznr]+1) x t pclk2 101 b 128 x t pclk2 t acmin + (128[tznr]+131.5) x t pclk2 t acmax + (128[tznr]+261.5) x t pclk2 128 x ([tznr]+1) x t pclk2
493 user?s manual u17566ee5v1um00 chapter 13 16-bit multi- purpose timer g (tmg) the v850e/dx3 microcontrollers have following instances of the 16-bit multi- purpose timer g: throughout this chapter, the individual instances of timer g are identified by ?n?, for example tmgn, or tmgmn for the tmgn mode register. note throughout this chapter, the following indexes are used: ? n: for each of the timer g instances ? m = 1 to 4: for the free assignable input/output-channels ? x = 0, 1: for bit-index, i.e. one of the 2 counters of each timer gn ? y = 0 to 5: for all of the 6 capture/compare-channels 13.1 features of timer g the timers gn operate as: ? pulse interval and frequency measurement counter ? interval timer ? programmable pulse output ? pwm output timer ? tmg0 can be used for triggering the dma controller. one capture input of timer g0 and one capture input of timer g1 are connected to the time stamp outputs of can0 and can1 modules and can therefore be used for can time stamp functions. tmg all devices instances 3 names tmg0 to tmg2
494 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 13.2 function overview of each timer gn ? 16-bit timer/counter (tmgn0, tmgn1): 2 channels ? bit length ? timer gn registers (tmgn0, tmgn1): 16 bits ? capture/compare register (gccny): 6 ? 16-bit ? 2 registers are assigned fix to the corresponding one of the 2 counters ? 4 free assignable registers to one of the 2 counters ? count clock division selectable by prescaler (frequency of peripheral clock: f spclk0 = 16 mhz) ? in 8 steps from f spclk0 /2 to f spclk0 /256 ? interrupt request sources ? edge detection circuit with noise elimination. ? compare-match interrupt requests: 6 types perform comparison of capture/compare register with one of the 2 counters (tmgn0, tmgn1) and generate the intccgny (y = 0 to 5) interrupt upon compare match. ? timer counter overflow interrupt requests: 2 types in free run mode the inttmgn0 (inttmgn1) interrupt is generated when the count value of tmgn0 (tmgn1) toggles from ffffh to 0000h. ? in match and clear mode the inttmgn0 (inttmgn1) interrupt is generated when the count value of tmgn0 (tmgn1) matches the gcc0 (gcc1) value. ? pwm output function ? control of the outputs of togn1 through togn4 pin in the compare mode. pwm output can be performed using the compare match timing of the gccn1 to gccn4 register and the corresponding timebase (tmgn0, tmgn1). ? output delay operation ? a clock-synchronized output delay can be added to the output signal of pins togn1 to togn4. ? this is effective as an emi counter measure. ? edge detection and noise elimination filter ? external signals shorter than 1 count clock (f countn , not f spclk0 ) are eliminated as noise. note the tign1 to tign4 and togn1 to togn4 are each alternative function pins. the following figure shows the block diagram of timer gn.
495 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 figure 13-1 block diagram of timer gn tmgn0 (16- b it) f s pclk0 (16 mhz) tign5 (note 3 ) noi s e elimin a tion edge detection f count0 f s pclk0 (16mhz) f s cplk0 /1 f s cplk0 /2 f s cplk0 /4 f s cplk0 / 8 f s cplk0 /16 f s cplk0 / 3 2 f s cplk0 /64 f s cplk0 /12 8 tign0 (note 2) tign1 tign2 tign 3 tign4 f s cplk0 /1 f s cplk0 /2 f s cplk0 /4 f s cplk0 / 8 f s cplk0 /16 f s cplk0 / 3 2 f s cplk0 /64 f s cplk0 /12 8 f count1 noi s e elimin a tion edge detection noi s e elimin a tion edge detection noi s e elimin a tion edge detection noi s e elimin a tion edge detection noi s e elimin a tion edge detection gccn0 (16- b it) c a pt u re/comp a re gccn1 (16- b it) c a pt u re/comp a re gccn2 (16- b it) c a pt u re/comp a re gccn 3 (16- b it) c a pt u re/comp a re gccn4 (16- b it) c a pt u re/comp a re gccn5 (16- b it) c a pt u re/comp a re tmgn1 (16- b it) cle a r cle a r inttgncc5 inttgncc4 inttgncc 3 inttgncc2 inttgncc1 inttgncc0 to control to control to control to control togn4 togn 3 togn2 togn1 inttgnov0 inttgnov1 (note 1) (note 1)
496 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 note 1. tmgn0/tmgn1 are cleared by gccn0/gccn5 register compare match. 2. tign0 differs: ? n = 0: tig00 not connected ? n = 1: tig10 not connected ? n = 2: tig20 available as external capture input 3. tign5 differs: ? n = 0: can0 time stamp tsoutcan0 -> tig05 ? n = 1: can1 time stamp tsoutcan1 -> tig15 ? n = 2: tig25 available as external capture input 13.3 basic configuration the basic configuration is shown below. table 13-1 timer gn configuration list note f spclk0 : internal peripheral clock count clock register r/w generated interrupt signal capture trigger timer output pwm f spclk0 f spclk0 /2, f spclk0 /4, f spclk0 /8, f spclk0 /16, f spclk0 /32, f spclk0 /64, f spclk0 /128 tmgn0 r inttmgn0 - - tmgn1 r inttmgn1 - - gccn0 r/w intccgn0 tign0 - gccn1 r/w intccgn1 tign1 togn1 gccn2 r/w intccgn2 tign2 togn2 gccn3 r/w intccgn3 tign3 togn3 gccn4 r/w intccgn4 tign4 togn4 gccn5 r/w intccgn5 tign5 -
497 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 13.4 tmg registers the timers gn are controlled and operated by means of the following registers: table 13-2 tmgn registers overview register name shortcut address timer gn mode register tmgmn timer gn channel mode register tmgcmn + 2 h timer gn output control register octlgn + 4 h timer gn time base status register tmgstn + 6 h timer gn count register 0 tmg00 + 8 h timer gn count register 1 tmg01 + a h timer gn capture/compare register 0 gcc00 + c h timer gn capture/compare register 1 gcc01 + e h timer gn capture/compare register 2 gcc02 + 10 h timer gn capture/compare register 3 gcc03 + 12 h timer gn capture/compare register 4 gcc04 + 14 h timer gn capture/compare register 5 gcc05 + 16 h table 13-3 tmgn register base address timer base address tmg0 ffff f6a0 h tmg1 ffff f6c0 h tmg2 ffff f6e0 h
498 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 (1) tmgmn - timer gn mode register access this register can be read/written in 16-bit, 8-bit or 1-bit units. the low byte tmgmn.bit[7:0] is accessible separately under the name tmgmnl, the high byte tmgmn.bit[15:8] under the name tmgmnh. address tmgmn, tmgmnl: tmgmnh: + 1 h initial value 0000 h . this register is cleared by any reset. 15 14 13 12 11 10 9 8 powern olden csen12 csen11 csen10 cse002 csen01 csen00 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 ccsgn5 ccsgn0 0 0 clrgn1 tmgn1e clrgn0 tmgn0e r/w r/w r/w r/w r/w r/w r/w r/w table 13-4 tmgmn register contents (1/2) bit position bit name function 15 powern timer gn operation control. 0: operation stop the capture registers and tmgstn register are cleared the tognm pins are inactive all the time 1: operation enable note: at least 7 peripheral clocks ( f spclk0 ) are needed to start the timer function 14 olden set output delay operation. 0: don?t perform output delay operation 1: set output delay to n count-clocks caution: when the powern bit is set, the rewriting of this bit is prohibited! simultaneously writing with the powern bit is allowed. note: the delay operation is used for emi counter measures. 13 to 8 csenx[2:0] selects internal count clock of tmg csenx2 csenx1 csenx0 count clock 000f spclk0 001 f spclk0 /2 010 f spclk0 /4 011 f spclk0 /8 100 f spclk0 /16 101 f spclk0 /32 110 f spclk0 /64 111 f spclk0 /128 caution: when the powern bit is set, the rewriting of this bits are prohibited! simultaneously writing with the powern bit is allowed.
499 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 7, 6 ccsgn5 ccsgn0 specifies the mode of the tmgn0 (tmgn1)(ccsgn5 for tmgn1, ccsgn0 for tmgn0): 0: free-run mode for tmgn1 (tmgn0), gccn5 (gccn0) in capture mode (an detected edge at pin tign5 (tign0) stores the value of tmgn1 (tmgn0) in gccn5 (gccn0) and an interrupt intccgn5 (intccgn0) is output) 1: match and clear mode of the tmgn1 (tmgn0), gccn5 (gccn0) in compare mode (when the data of gccn5 (gccn0) match the count value of the tmgn1 (tmgn0), the counter is cleared and the interrupt intccgn5 (intccgn0) occurs) caution: when the powern bit is set, the rewriting of this bits are prohibited! simultaneously writing with the powern bit is allowed. 3, 1 clrgnx specifies software clear for tmgnx 0: continue tmgnx operation 1: clears (0) the count value of tmgnx, the corresponding tognx is deactivated. note: tmgnx starts 1 peripheral-clock after this bit is set this bit is not readable (always read 0) 2, 0 tmgnxe specifies tmgnx count operation enable/disable 0: stop count operation the counter holds the immediate preceding value the corresponding tognx is deactivated 1: enable count operation note: 1. the counter needs at least 1 peripheral-clock ( f spclk0 ) to stop 2. the counter needs at least 4 peripheral-clocks ( f spclk0 ) to start table 13-4 tmgmn register contents (2/2) bit position bit name function
500 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 (2) tmgcmn - timer gn channel mode register this register specifies the assigned counter (tmgn0 or tmgn1) for the gccnm register. furthermore it specifies the edge detection for the tigny input pins. access this register can be read/written in 16-bit, 8-bit or 1-bit units. the low byte tmgcmn.bit[7:0] is accessible separately under the name tmgcmnl, the high byte tmgcmn.bit[15:8] under the name tmgcmnh. address tmgcmn, tmgcmnl: + 2 h tmgcmnh: + 3 h initial value 0000 h . this register is cleared by any reset. 15 14 13 12 11 10 9 8 tbgn4 tbgn3 tbgn2 tbgn1 iegn51 iegn50 iegn41 iegn40 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 iegn31 iegn30 iegn21 iegn20 iegn11 iegn10 iegn01 iegn00 r/w r/w r/w r/w r/w r/w r/w r/w table 13-5 tmgcmn register contents bit position bit name function 15 to 12 tbgnm assigns capture/compare registers gccn1 to gccn4 to one of the 2 counters tmgn0 or tmgn1: 0: set tmgn0 as the corresponding counter to gccnm register and tignm/ tognm pin 1: set tmgn1 as the corresponding counter to gccnm register and tignm/ tognm pin 11 to 0 iegny1, iegny0 specifies the valid edge of external capture signal input pin (tignm) for the capture register performing capture-match with the assigned counter tmgn0 or tmgn1: iegny1 iegny0 valid edge 0 0 falling edge 0 1 rising edge 1 0 no edge detection performed 1 1 both rising and falling edges
501 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 (3) octlgn - timer gn output control register this register controls the timer output from the tognm pin and the capture or compare modus for the gccnm register. access this register can be read/written in 16-bit, 8-bit or 1-bit units. the low byte octlgn.bit[7:0] is accessible separately under the name octlgnl, the high byte octlgn.bit[15:8] under the name octlgnh. address octlgn, octlgnl: + 4 h octlgnh: + 5 h initial value 4444 h . this register is cleared by any reset. caution 1. when the powern bit is set, the rewriting of ccsgnm is prohibited 2. when the powern bit and tmgn0e bit (tmgn1e bit) are set at the same time, the rewriting of the alvgnm bits is prohibited. 15 14 13 12 11 10 9 8 swfgn4 alvgn4 ccsgn4 0 swfgn3 alvgn3 ccsgn3 0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 swfgn2 alvgn2 ccsgn2 0 swfgn1 alvgn1 ccsgn1 0 r/w r/w r/w r/w r/w r/w r/w r/w table 13-6 octlgn register contents bit position bit name function 15, 11, 7, 3 swfgnm fixes the tognm pin output level according to the setting of alvgnm bit. 0: disable tognm to inactive level 1: enable tognm 14, 10, 6, 2 alvgnm specifies the active level of the tgonm pin output. 0: active level is 0 1: active level is 1 caution: don?t write this bit, before enfgn0 or enfgn1 of tmgstn is 0, so first clear tmgn0e or tmgn1e bit of the tmgmn register and check enfgn0 or enfgn1 bit before writing. 13, 9, 5, 1 ccsgnm specifies capture/compare mode selection: 0: capture mode: if external edge is detected the intccgnm interrupt occurs, the corresponding counter value is written to gccnm 1: compare mode: if gccnm matches with corresponding timebase the intccgnm interrupt occurs, if swfgm is set the pwm output mode is set caution: don?t write this bit, before powern bit of tmgmnh is 0.
502 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 (4) tmgstn - time base status register the tmgstn register indicates the status of tmgn0 and tmgn1. for the ccfgny bit see ?operation in free-run mode? on page 507 . access this register can be read in 8-bit or 1-bit units. address + 6 h initial value 00 h . this register is cleared by any reset. (5) tmgn0, tmgn1 - timer gn 16-bit counter registers the features of the counters tmgn0 and tmgn1 are listed below: ? free-running counter that enables counter clearing by compare match of registers gccn0/gccn5 ? counter clear can be set by software. ? counter stop can be set by software. access these registers can be read in 16-bit units. address tmgn0: + 8 h tmgn1: + a h initial value 0000 h . this register is cleared by any reset. 76543210 enfgn1 enfgn0 ccfgn5 ccfgn4 c cfgn3 ccfgn2 ccfgn1 ccfgn0 rrrrrrrr table 13-7 tmgstn register contents bit position bit name function 5 to 0 ccfgny indicates tmgn0 or tmgn1 overflow status. 0: no overflow 1: overflow caution: the ccfgny bit is set if a tmgnx overflow has occurred between two capture input signals. this flag is only updated if the corresponding gccny register was read, so first read the gccny register and then read this flag if necessary 7 to 6 enfgnx indicates tmgnx operation. 0: indicates operation stopped 1: indicates operation 1514131211109876543210 tmgn0/tmgn1 value r
503 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 (6) gccn0, gccn5 - timer gn capture/compare registers of the 2 counters the gccn0, gccn5 registers are 16-bit capture/compare registers of timer gn. these registers are fixed assigned to the counter registers: ? gccn0 is fixed assigned to timebase tmgn0 ? gccn5 is fixed assigned to timebase tmgn1 capture mode in the capture register mode , gccn0 (gccn5) captures the tmgn0 (tmgn1) count value if an edge is detected at pin tign0 (tign5). compare mode in the compare register mode , gccn0 (gccn5) detects match with tmgn0 (tmgn1) and clears the assigned timebase. so this ?match and clear mode? is used to reduce the number of valid bits of the counter tmgn0 (tmgn1). caution if in compare mode write to this registers before powern and enfgnx bit are "1" at the same time. access in capture mode, these registers can be read in 16-bit units. in compare mode, these registers can be read/written in 16-bit units. address gccn0: + c h gccn5: + 16 h initial value 0000 h . these registers are cleared by any reset. 1514131211109876543210 ggcn0/ggcn5 value r/w
504 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 (7) gccn1 to gccn4 - timer g capture/compare registers with external pww-output function the gccn1 to gccn4 registers are 16-bit capture/compare registers of timer gn. they can be assigned to one of the two counters either tmgn0 or tmgn1. capture mode in the capture register mode, these registers capture the value of tmgn0 when the tbgnm bit (m = 1 to 4) of the tmgcmnh register = 0. when the tbgnm bit = 1, these registers hold the value of tmgn1. compare mode in compare mode, these registers represent the actual compare value and the tognm-output (m = 1 to 4) can generate a pww if they are activated. access in capture mode, these registers can be read in 16-bit units. in compare mode, these registers can be read/written in 16-bit units. address gccn1: + e h gccn2: + 10 h gccn3: + 12 h gccn4: + 14 h initial value 0000 h . these registers are cleared by any reset. 1514131211109876543210 ggcn1 to ggcn4 value r/w
505 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 13.5 output delay operation when the olden bit is set, different delays of count clock period are added to the tognm pins: the figure below shows the timing for the case where the count clock is set to f spclk0 /2. however, 0fffh is set in gccn0. similar delays are added also when a transition is made from the active to inactive level. so, a relative pulse width is guaranteed. figure 13-2 timing of output delay operation in this case the count clock is set to f spclk0 /2. output pin delay 1/f count togn1 0 togn2 1 togn3 2 togn4 3 fffeh 0002h 0003h 0001h 0000h ffffh 0004h tmgcn0 togn1 togn2 togn3 togn4 f count
506 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 13.6 explanation of basic operation (1) overview of the mode settings the timer gn includes 2 channels of 16-bit counters (tmgn0/tmgn1), which can operate as independently timebases. tmgn0 (tmgn1) can be set by ccsgn0 bit (ccsgn5 bit) in the following modes: ? free-run mode ? match and clear mode when a timer output (tognm) or intccgnm interrupt is used, one of the two counters can be selected by setting the tbgnm bit (m = 1 to 4) of the tmgcmhn register. the tables below indicate the interrupt output and timer output states dependent on the register setting values. table 13-8 interrupt output and timer output states dependent on the register setting values note 1. an interrupt is generated only when the value of the gccn0 register is ffffh. 2. an interrupt is generated only when the value of the gccn0 register is not ffffh. 3. the setting of the ccsgnm bit in combination with the swfgnm bit sets the mode for the timing of the actualization of new compare values. ? in compare mode the new compare value will be immediately active. ? in pwm mode the new compare value will be active first after the next overflow or match & clear of the assigned counter (tmgn0, tmgn1). register setting value state of each output pin ccsgn0 tbgnm swfgnm ccsgnm inttmgn0 intccgn0 intccgnm tognm 0 free-run mode 0 0 0 overflow interrupt ti0 edge detection tim edge detection tied to inactive level 1 gccnm match 1 0 tim edge detection 1cmpgm match pwm (free run) 1 match and clear mode 0 0 overflow interrupt note 1 gccn0 match note 2 tim edge detection tied to inactive level 1 gccnm match 1 0 tim edge detection 1cmpgm match pwm (match and clear)
507 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 table 13-9 interrupt output and timer output states dependent on the register setting values note 1. an interrupt is generated only when the value of the gccn5 register is ffffh. 2. an interrupt is generated only when the value of the gccn5 register is not ffffh. 3. the setting of the ccsgnm bit in combination with the swfgnm bit sets the mode for the timing of the actualization of new compare values. ? in compare mode the new compare value will be immediately active. ? in pwm mode the new compare value will be active first after the next overflow or match & clear of the assigned counter (tmgn0, tmgn1). 13.7 operation in free-run mode this operation mode is the standard mode for timer gn operations. in this mode the 2 counter tmgn0 and tmgn1 are counting up from 0000h to ffffh, generates an overflow and start again. in the match and clear mode, which is described in chapter 13.8 on page 518 the fixed assigned register gccn0 (gccn5) is used to reduce the bit-size of the counter tmgn0 (tmgn1). (1) capture operation (free run) basic settings: register setting value state of each output pin ccsgn5 tbgnm swfgnm ccsgnm inttmgn1 intccgn5 intccgnm tognm 0 free-run mode 1 0 0 overflow interrupt ti5 edge detection tim edge detection tied to inactive level 1 gccnm match 1 0 tim edge detection 1cmpgm match pwm (free run) 1 match and clear mode 0 0 overflow interrupt note 1 gccn5 match note 2 tim edge detection tied to inactive level 1 gccnm match 1 0 tim edge detection 1cmpgm match pwm (match and clear) bit value remark ccsgn0 0 free run mode ccsgn5 0 swfgnm 0 disable tognm tbgnm x assign counter for gccnm 0: tmgn0 1: tmgn1
508 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 (a) example: pulse width or period measurement of the tigny input signal (free run) capture setting method: (1) when using one of the togn1 to togn4 pins, select the corresponding counter with the tbgnm bit. when tign0 is used, the corresponding counter is tmgn0. when tign5 is used, the corresponding counter is tmgn1. (2) select a count clock cycle with the cse12 to cse10 bits (tmgn1) or cse02 to cse02 bits (tmgn0). (3) select a valid tigny edge with the iegny1 and iegny0 bits. a rising edge, falling edge, or both edges can be selected. (4) start timer operation by setting powern bit and tmgn0e bit for tmgn0 or tmgn1e bit for tmgn1. capture operation: (1) when a specified edge is detected, the value of the counter is stored in gccny and an edge detection interrupt (intccgny) is output. (2) when the counter overflows, an overflow interrupt (inttmgn0 or inttmgn1) is generated. (3) if an overflow has occurred between capture operations, the ccfgny flag is set when gccny is read. correct capture data by checking the value of ccfgny. using ccfgny: when using gccny as a capture register, use the procedure below. <1> after intccgny (edge detection interrupt) generation, read the corresponding gccny register. <2> check if the corresponding ccfgny bit of the tmgstn register is set. <3> if the ccfgny bit is set, the counter was cleared from the previous captured value. ccfgny is set when gccny is read. so, after gccny is read, the value of ccfgny should be read. using the procedure above, the value of ccfgny corresponding to gccny can be read normally. caution if two or more overflows occur between captures, a software-based measure needs to be taken to count overflow interrupts (inttmgn0, inttmgn1).
509 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 figure 13-3 timing when both edges of tign0 are valid (free run) note the figure above shows an image. in actual circuitry, 3 to 4 periods of the count-up signal are required from the input of a waveform to tign0 until a capture interrupt is output. 0000h 0001h d0 d1 tm g n0 d0 gccn0 c ount sta rt t fff fh 0000h d2 d3 ti gn0 d1 d2 d3 cl ear inttgncc0 intgnov0 n o overf low overf low ccfgn0 n o overf low f countx
510 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 (b) timing of capture trigger edge detection the tin inputs are fitted with an edge-detection and noise-elimination circuit. because of this circuit, 3 periods to less than 4 periods of the count clock are required from edge input until an interrupt signal is output and capture operation is performed. the timing chart is shown below. basic settings (x = 0, 1 and y = 0 to 5): figure 13-4 timing of capture trigger edge detection (free run) bit value remark csex2 0 count clock = f spclk0 /4 csex1 1 csex0 0 iegny1 1 detection of both edges iegny0 1 t+2 t+3 t+4 t+5 t+6 t+7 t+7 tt+1 t+4 t+8 tmgn0/tmgn1 tign0 inttgnccy gccny 3 count clock periods f countx
511 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 (c) timing of starting capture trigger edge detection a capture trigger input signal (tigny) is synchronized in the noise eliminator for internal use. edge detection starts when 1 count clock period (f count ) has been input after timer count operation starts. (this is because masking is performed to prevent the initial tigny level from being recognized as an edge by mistake.). the timing chart for starting edge detection is shown below. basic settings (x = 0, 1 and y = 0 to 5): figure 13-5 timing of starting capture trigger edge detection bit value remark csex2 0 count clock = f spclk0 /4 csex1 1 csex0 0 iegny1 1 detection of both edges iegny0 1 00 01h 00 02h 00 03h 00 04h 00 05h 00 06h 00 05 h inttgnccy gccny tm g0e (tm g1 e ) e nfg 0(e nfg1 ) count_up0(count_up1) invalid ed ge i nput e dge de tection s tart tigny f countx tmgn0/tmgn1
512 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 (2) compare operation (free run) basic settings (m = 1 to 4): (a) example: interval timer (free run) setting method interval timer: (1) an usable compare register is one of gccn1 to gccn4, and the corresponding counter (tmgn0 or tmgn1) must be selected with the tbgnm bit. (2) select a count clock cycle with the cse12 to cse10 bits (tmgn1 register) or cse02 to cse00 bits (tmgn0 register). (3) write data to gccnm. (4) start timer operation by setting powern and tmgn0e (or tmgn1e). compare operation: (1) when the value of the counter matches the value of gccnm (m = 0 to 4), a match interrupt (intccgnm) is output. (2) when the counter overflows, an overflow interrupt (inttmgn0/ inttmgn1) is generated. figure 13-6 timing of compare mode (free run) data n is set in gccn1, and the counter tmgn0 is selected. bit value remark ccsgn0 0 free run mode ccsgn5 0 swfgnm 0 disable tognm ccsgnm 1 compare mode for gccnm tbgnm x assign counter for gccnm 0: tmgn0 1: tmgn1 n enfg0 tm g n0 gccn1 inttgncc1 inttgnov0 ffffh ffffh ffffh ma tch
513 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 (b) when the value 0000h is set in gccnm intccgnm is activated when the value of the counter becomes 0001h. inttmgn0/inttmgn1 is activated when the value of the counter changes from ffffh to 0000h. note, however, that even if no data is set in gccnm, intccgnm is activated immediately after the counter starts. (c) when the value ffffh is set in gccnm intccgnm and inttmgn0/inttmgn1 are activated when the value of the counter changes from ffffh to 0000h. (d) when gccnm is rewritten during operation when gccn1 is rewritten from 5555h to aaaah. tmgn0 is selected as the counter. the following operation is performed: figure 13-7 timing when gccn1 is rewritten during operation (free run) caution to perform successive write access during operation, for rewriting the gccny register (n = 1 to 4), you have to wait for minimum 7 peripheral clocks periods (f spclk0 ). ma tch ma tch 5555h aaaah aaaah 5555h reload in 5 periods inttgncc1 tm g n0 enfg0 gccn1 slave register gccn1 master register
514 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 (3) pwm output (free run) basic settings (m = 1 to 4): note the pwm mode is activated by setting the swfgnm and the ccsgnm bit to "1". pwm setting method: (1) an usable compare register is one of gccn1 to gccn4, and the corresponding counter must be selected with the tbgnm bit. (2) select a count clock cycle with the cse12 to cse10 bits (tmgn1 register) or cse02 to cse00 bits (tmgn0 register). (3) specify the active level of a timer output (tognm pin) with the alvgnm bit. (4) when using multiple timer outputs, the user can prevent tognm from becoming active simultaneously by setting the olden bit of tmgmhn register to provide step-by-step delays for tognm. (this capability is useful for reducing noise and current.) (5) write data to gccnm. (6) start timer operation by setting powern bit and tmgn0e bit (or tmgn1e bit). pwm operation: (1) when the value of the counter matches the value of gccnm, a match interrupt (intccgnm) is output. (2) when the counter overflows, an overflow interrupt (inttmgn0 or inttmgn1) is generated. (3) tognm does not make a transition until the first overflow occurs. (even if the counter is cleared by software, tognm does not make a transition until the next overflow occurs. after the first overflow occurs, tognm is activated. (4) when the value of the counter matches the value of gccnm, tognm is deactivated, and a match interrupt (intccgnm) is output. the counter is not cleared, but continues count-up operation. (5) the counter overflows, and inttmgn0 or inttmgn1 is output to activate tognm. the counter resumes count-up operation starting with 0000h. bit value remark ccsgn0 0 free run mode ccsgn5 0 swfgnm 1 note enable tognm ccsgnm 1 note compare mode for gccnm tbgnm x assign counter for gccnm 0: tmgn0 1: tmgn1
515 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 figure 13-8 timing of pwm operation (free run) data n is set in gccn1, counter tmgn0 is selected. (a) when 0000h is set in gccnm (m = 1 to 4) when 0000h is set in gccnm, tognm is tied to the inactive level. the figure below shows the state of togn1 when 0000h is set in gccn1, and tmgn0 is selected. figure 13-9 timing when 0000h is set in gccnm (free run) gccn1 and tmgn0 are selected. n enfg0 tm g n0 gccn1 inttgncc1 inttgnov0 ffffh ffffh ffffh ma tch togn1 (alvg1=1) togn1 (alvg1=0) 0000h enfg0 tm g n0 gccn1 inttgncc1 inttgnov0 togn1(al vg 1=1) togn1(al vg 1=0) ffffh ffffh ffffh ma tch low high
516 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 (b) when ffffh is set in gccnm (m = 1 to 4) when ffffh is set in gccnm, tognm outputs the inactive level for one clock period immediately after each counter overflow (except the first overflow). the figure shows the state of togn1 when ffffh is set in gccn1, and tmgn0 is selected. figure 13-10 timing when ffffh is set in gccnm (free run) gccn1 and tmgn0 are selected. ma tch ffffh enfg0 tm g n0 gccn1 inttgncc1 inttgnov0 togn1(al vg 1=1) togn1(al vg 1=0) ffffh ffffh ffffh
517 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 (c) when gccnm is rewritten during operation (m = 1 to 4) when gccn1 is rewritten from 5555h to aaaah, the operation shown below is performed. the figure below shows a case where tmgn0 is selected for gccn1. figure 13-11 timing when gccnm is rewritten during operation (free run) gccn1 and tmgn0 are selected. if gccn1 is rewritten to aaaah after the second intccgn1 is generated as shown in the figure above, aaaah is reloaded to the gccn1 register when the next overflow occurs. the next match interrupt (intccgn1) is generated when the value of the counter is aaaah. the pulse width also matches accordingly. 5555h aaaah aaaah 5555h ma tch ma tch ma tch ffffh enfg0 tm g n0 inttgncc1 inttgnov0 togn1(al vg 1=1) togn1(al vg 1=0) aaaah 5555h ffffh ffffh gccn1 slave register gccn1 master register
518 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 13.8 match and clear mode the match and clear mode is mainly used reduce the number of valid bits of the counters (tmgn0, tmgn1). therefore the fixed assigned register gccn0 (gccn1) is used to compare its value with the counter tmgn0 (tmgn1). if the values match, than an interrupt is generated and the counter is cleared. than the counter starts up counting again. (1) capture operation (match and clear) basic settings (m = 1 to 4): (a) example: pulse width measurement or period measurement of the tignm input signal setting method: (1) when using one of togn1 to togn4 pin, select the corresponding counter with the tbgnm bit. when ccsgn0 = 1, ti0 cannot be used. when ccsgn5 = 1, tign5 cannot be used. (2) select a count clock cycle with the cse12 to cse10 (tmgn1) bits or cse02 to cse00 (tmgn0) bits. (3) select a valid tignm edge with the iegnm1 and iegnm0 bit. a rising edge, falling edge, or both edges can be selected. (4) set an upper limit on the value of the counter in gccn0 or gccn5. (5) start timer operation by setting powern bit and tmgn0e bit (or tmgn1e bit). operation: (1) when a specified edge is detected, the value of the counter is stored in gccnm, and an edge detection interrupt (intccgnm) is output. (2) when the value of gccn0 or gccn5 matches the value of the counter, intccgn0 (intccgn5) is output, and the counter is cleared. this operation is referred to as "match and clear". (3) if a match and clear event has occurred between capture operations, the ccfgny flag is set when gccny is read. correct capture data by checking the value of ccfgny. bit value remark ccsgn0 1 match and clear mode ccsgn5 1 swfgnm 0 disable tognm ccsgnm 0 capture mode for gccnm tbgnm x assign counter for gccnm 0: tmgn0 1: tmgn1
519 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 (b) example: capture where both edges of tignm are valid (match and clear) for the timing chart tmgn0 is selected as the counter corresponding to togn1, and 0fffh is set in gccn0. figure 13-12 timing when both edges of tignm are valid (match and clear) note the figure above shows an image. in actual circuitry, 3 to 4 periods of the count-up signal (f count ) are required from the input of a waveform to togn1 until a capture interrupt is output. (see figure 13-4 on page 510 .) caution if two or more match and clear events occur between captures, a software- based measure needs to be taken to count intccgn0 or intccgn5. (c) when 0000h is set in gccn0 or gccn5 (match and clear) when 0000h is set in gccn0 (gccn5), the value of the counter is fixed at 0000h, and does not operate. moreover, intccgn0 (intccgn5) continues to be active. (d) when ffffh is set in gccn0 or gccn5 (match and clear) when ffffh is set in gccn0 (gccn5), operation equivalent to the free-run mode is performed. when an overflow occurs, inttmgn0 (inttmgn1) is generated, but intccgn0 (intccgn5) is not generated. 0000h 0001h d0 d1 tmgn0 d0 gccn1 c ount start t 0ff f h 0000h d2 d3 tign1 d1 d2 d3 cl ear inttgncc1 inttgncc0 no "match and cl ea r" no "match and cl ea r" "match and c lea r" ccfg1 f countx
520 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 (2) compare operation (match and clear) basic settings (m = 1 to 4): (a) example: interval timer (match and clear) setting method (1) an usable compare register is one of gccn1 to gccn4, and the corresponding counter must be selected with the tbgnm bit. (2) select a count clock cycle with the cse12 to cse10 bits (tmgn1) or cse02 to cse00 bits (tmgn0). (3) set an upper limit on the value of the counter in gccn0 or gccn5. (4) write data to gccnm. (5) start timer operation by setting the powern bit and tmgxe bit (x = 0, 1). operation: (1) when the value of the counter matches the value of gccnm, a match interrupt (intccgnm) is output. (2) when the value of gccn0 or gccn5 matches the value of the counter, intccgn0 (or intccgn5) is output, and the counter is cleared. this operation is referred to as "match and clear". (3) the counter resumes count-up operation starting with 0000h. bit value remark ccsgn0 1 match and clear mode ccsgn5 1 swfgnm 0 disable tognm ccsgnm 1 compare mode for gccnm tbgnm x assign counter for gccnm 0: tmgn0 1: tmgn1
521 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 figure 13-13 timing of compare operation (match and clear) in this example, the data n is set in gccn1, and tmgn0 is selected. 0fffh is set in gccn0. here, n < 0fffh. (b) when 0000h is set in gccn0 or gccn5 (match and clear) when 0000h is set in gccn0 or gccn5, the value of the counter is fixed at 0000h, and does not operate. moreover, intccgn0 (or intccgn5) continues to be active. (c) when ffffh is set in gccn0 or gccn5 (match and clear) when ffffh is set in gccn0 or gccn5, operation equivalent to the free-run mode is performed. when an overflow occurs, inttmgn0 (or inttmgn1) is generated, but intccgn0 (or intccgn5) is not generated. (d) when 0000h is set in gccnm (m = 1 to 4) (match and clear) intccgnm is activated when the value of the counter becomes 0001h. note, however, that even if no data is set in gccnm, intccgnm is activated immediately after the counter starts. (e) when a value exceeding the value of gccn0 or gccn5 is set in gccnm (m = 1 to 4) (match and clear) intccgnm is not generated. n enfg0 tm g n0 gccn1 inttgncc1 inttgncc0 0fffh 0fffh 0fffh ma tch
522 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 (f) when gccnm (m = 1 to 4) is rewritten during operation (match and clear) when the value of gccn1 is changed from 0555h to 0aaah, the operation described below is performed. tmgn0 is selected as the counter, and 0fffh is set in gccn0. figure 13-14 timing when gccnm is rewritten during operation (match and clear) caution to perform successive write access during operation, for rewriting the gccny register, you have to wait for minimum 7 peripheral clocks periods (f spclk0 ). (3) pmw output (match and clear) basic settings (m = 1 to 4): note the pwm mode is activated by setting the swfgnm and the ccsgnm bit to "1". ma tch ma tch 0555h 0aaah 0aaah 0555h inttgncc1 tm g n0 enfg0 reload in 5 clock periods gccn1 slave register gccn1 master register bit value remark ccsgn0 1 match and clear mode ccsgn5 1 swfgnm 1 note enable tognm ccsgnm 1 note compare mode for gccnm tbgnm x assign counter for gccnm 0: tmgn0 1: tmgn1
523 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 setting method: (1) an usable compare register is one of gccn1 to gccn4, and the corresponding counters tmgn0 or tmgn1 must be selected with the tbgnm bit (m = 1 to 4). (2) select a count clock cycle with the cse12 to cse10 (tmgn1) bits or cse02 to cse00 (tmgn0) bits. (3) specify the active level of a timer output (tognm) with the alvgnm bit. (4) when using multiple timer outputs, the user can prevent tognm from making transitions simultaneously by setting the olden bit of tmgmhn register. (this capability is useful for reducing noise and current.) (5) set an upper limit on the value of the counter in gccn0 or gccn5. (timer dn 0000h is forbidden) (6) write data to gccnm. (7) start count operation by setting powern bit and tmgn0e bit (or tmgn1e bit). operation of pwm (match and clear): (1) when the value of the counter matches the value of gccnm, a match interrupt (intccgnm) is output. caution do not set 0000h in gccn0 or gccn5 in match and clear modus. (2) when the value of gccn0 (gccn5) matches the value of the counter, intccgn0 (intccgn5) is output, and the counter is cleared. this operation is referred to as "match and clear". (3) tognm does not make a transition until the first match and clear event. (4) tognm makes a transition to the active level after the first match and clear event. (5) when the value of the counter matches the value of gccnm, tognm makes a transition to the inactive level, and a match interrupt (intccgnm) is output. (6) when the next match and clear event occurs, intccgn0 (intccgn5) is output, and the counter is cleared. the counter resumes count-up operation starting with 0000h.
524 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 example where the data n is set, and the counter tmgn0 is selected. 0fffh is set in gccn0 and n < 0fffh. figure 13-15 timing of pwm operation (match and clear) when 0000h is set in gccn0 (gccn5), the value of the counter is fixed at 0000h, and the counter does not operate. the waveform of intccgn0 (intccgn5) varies, depending on whether the count clock is the reference clock or the sampling clock. (a) when ffffh is set in gccn0 or gccn5 (match and clear) when ffffh is set in gccn0 (gccn5), operation equivalent to the free-run mode is performed. when an overflow occurs, inttmgn0 (inttmgn1) is generated, but intccgn0 (intccgn5) is not generated. n enfg0 tm g n0 gccn1 inttgncc1 inttgncc0 togn1(alvg1=0) 0fffh 0fffh 0fffh ma tch togn1(alvg1=1)
525 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 (b) when 0000h is set in gccnm (match and clear) when 0000h is set in gccnm, tognm is tied to the inactive level. the figure below shows the state of togn1 when 0000h is set in gccn1, and tmgn0 is selected. note, however, that 0fffh is set in gccn0. figure 13-16 timing when 0000h is set in gccnm (match and clear) 0000h enfg0 tm g n0 gccn1 inttgncc1 intgncc0 low high 0fffh 0fffh 0fffh ma tch togn1(alvg1=0) togn1(alvg1=1)
526 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 (c) when the same value as set in gccn0 or gccn5 is set in gccnm (match and clear) when the same value as set in gccn0 (gccn5) is set in gccnm, tognm outputs the inactive level for only one clock period immediately after each match and clear event (excluding the first match and clear event). the figure below shows the state of togn1 when 0fffh is set in gccn0 and gccn1, and tmgn0 is selected. figure 13-17 timing when the same value as set in gccn0/gccn5 is set in gccnm (match and clear) ma tch enfg0 tm g n0 gccn1 inttgncc1 inttgncc0 0fffh 0fffh 0fffh 0fffh togn1(alvg1=0) togn1(alvg1=1)
527 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 (d) when a value exceeding the value set in gccn0 or gccn5 is set in gccnm (match and clear) when a value exceeding the value set in gccn0 (gccn5) is set in gccnm, tognm starts and continues outputting the active level immediately after the first match and clear event (until count operation stops.) the figure shows the state of togn1 when 0fffh is set in gccn0, 1fffh is set in gccn1, and tmgn0 is selected. figure 13-18 timing when the value of gccnm exceeding gccn0 or gccn5 (match and clear) low enfg0 tmgn0 gccn1 inttgncc1 inttgncc0 0fffh 0fffh 0fffh 1fffh togn1(alvg1=0) togn1(alvg1=1)
528 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 (e) when gccnm is rewritten during operation (match and clear) when gccn1 is rewritten from 0555h to 0aaah, the operation shown below is performed. the figure below shows a case where 0fffh is set in gccn0, and tmgn0 is selected for gccn1. figure 13-19 timing when gccnm is rewritten during operation (match and clear) if gccn1 is rewritten to 0aaah after the second intccgn1 is generated as shown in the figure above, 0aaah is reloaded to the gccn1 register when the next overflow occurs. the next match interrupt (intccgn1) is generated when the value of the counter is 0aaah. the pulse width also matches accordingly. 0555h 0aaah 0aaah 0555h ma tch ma tch 0fffh tm g n0 enfg0 inttgncc1 inttgncc0 0aaah 0555h 0fffh 0fffh ma tch togn1(alvg1=0) togn1(alvg1=1) gccn1 slave register gccn1 master register
529 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 13.9 edge noise elimination the edge detection circuit has a noise elimination function. this function regards: ? a pulse not wider than 1 count clock period as a noise , and does not detect it as an edge. ?a pulse not shorter than 2 count clock periods is detected normally as an edge . ? a pulse wider than 1 count clock period but shorter than 2 count clock periods may be detected as an edge or may be eliminated as noise , depending on the timing. (this is because the count-up signal of the counter is used for sampling timing.) the upper figure below shows the timing chart for performing edge detection. the lower figure below shows the timing chart for not performing edge detection. basic settings (x = 0, 1 and y = 0 to 5): figure 13-20 timing of edge detection noise elimination bit value remark csex2 0 count clock = f spclk0 /4 csex1 1 csex0 0 iegny1 1 detection of both edges iegny0 1 t+2 t+3 t+4 t+5 t+6 t+7 t+6 tt+1 t+4 t+2 t+4 t+5 t t+1 t+3 t+6 t+7 tmgn0/tmgn1 tigny inttgnccy gccny f countx tmgn0/tmgn1 tigny inttgnccy gccny f countx
530 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00 13.10 precautions timer gn (1) when powern bit of tmgmhn register is set the rewriting of the csen2 to csen0 bits of tmgmhn register is prohibited. these bits set the prescaler for the timer gn counter. the rewriting of the ccsgny bits (y = 0 to 5) is prohibited. this bits (octlgnl and octlgnh registers) set the capture mode or the compare mode to the gccy register. for the gccn0 register and the gccn5 register these bits (tmgmln register) set the ?free run? or ?match and clear? mode of the tmgn0 and tmgn1 counter. the rewriting of the tmgcmnl and the tmgcmhn register is prohibited. these registers configure the counter (tmgn0 or tmgn1) for the gccnm register (m = 1 to 4) and define the edge detection for the tignm input pins (falling, rising, both). even when powern bit is set, tognm output is switched by switching the alvgnm bit of octlgnl and octlgnh registers. these bits configure the active level of the tognm pins (m = 1 to 4). (2) when powern bit and tmgxe bit are set (x = 0, 1) the rewriting of alvgnm is prohibited (m = 1 to 4). these bits configure the active level of the tognm pins (m = 1 to 4). when in compare-mode the rewriting of the gccn0 or gccn5 register is prohibited. in compare mode these registers set the value for the ?match and clear? mode of the tmgn0 and tmgn1 counter. (3) functionality when the powern bit is set to ?0?, regardless of the swfgnm bit (octlgnl and octlgnh registers), the tognm pins are tied to the inactive level. the swfgnm bit enables or disables the output of the tognm pins. this bit can be rewritten during timer operation. the clrgx bit (x = 0, 1) is a flag. if this bit is read, a "0" is read at all times. this bit clears the corresponding counter (tmgn0 or tmgn1) when gccnm register (m = 1 to 4) are used in capture operation: if two or more overflows of tmgn0 or tmgn1 occur between captures, a software-based measure needs to be taken to count overflow interrupts (inttmgn0 or inttmgn1).
531 16-bit multi-purpose timer g (tmg) chapter 13 user?s manual u17566ee5v1um00 if only one overflow is necessary, the ccfgny bits (y = 0 to 5) can be used for overflow detection. only the overflow of the tmgn0 or tmgn1counter clears the ccfgny bit (tmgstn register). the software-based clearing via clrgn0 or clrgn1 bit (tmgmln register) doesn?t affect these bits. the ccfgny bit is set if a tmgn0 (tmgn1) overflow occurs. this flag is only updated if the corresponding gccny register was read, so first read the gccny register and then read this flag if necessary. (4) timing the delay of each timer output tognm (m = 1 to 4) varies according to the setting of the count clock with the csex2 to csex0 bits (x = 0, 1). in capture operation 3 to 4 periods of the count-clock (f count ) signal are required from the tigny pin (y = 0 to 5) until a capture interrupt is output. when tmgxe (x = 0, 1) is set earlier or simultaneously with powern bit, than the timer gn needs 7 peripheral clock periods (f spclk0 ) to start counting. when tmgxe (x = 0, 1) is set later than powern bit, than the timer gn needs 4 peripheral clock periods (f spclk0 ) to start counting. when a capture register (gccny) is read, the capturing is disable during read operation. this is intended to prevent undefined data during reading. so, if a contention occurs between an external trigger signal and the read operation, capture operation may be cancelled, and old data may be read. gccnm register (m = 1 to 4) in compare mode: after setting the powern bit you have to wait for 10 peripheral clock periods (f spclk0 ) to perform write access to the gccnm register (m = 1 to 4). to perform successive write access during operation, for rewriting the gccnm register, you have to wait for minimum 7 peripheral clock periods (f spclk0 ).
532 chapter 13 16-bit multi-purpose timer g (tmg) user?s manual u17566ee5v1um00
533 user?s manual u17566ee5v1um00 chapter 14 16-bit timer y (tmy) timer y (tmy) is a two-stage 16-bit timer/counter. the v850e/dx3 microcontrollers have following instances of the two-stage 16- bit timer/counter tmy: throughout this chapter, the individual instances of tmy are identified by ?n?, for example, tmyn, or tynctl for the tmyn control register. 14.1 overview each timer y has two down-counters. they are named counter 0 and counter 1 and operate alternately. when counter 0 reaches zero, it starts counter 1 and waits until counter 1 expires. when counter 1 reaches zero, it restarts counter 0. the tmy can be used as: ? generator of a pulse width modulated (pwm) signal ? generator of a pulse and frequency modulated (pfm) signal ? interval timer ? free running timer features summary special features of the tmy are: ? one of six clocks can be selected, individually for each of the two counters ? two reload registers, one for each counter ? four readable counter registers, two for each counter ? one timer output pin ? when the device is in debug mode, the timer can be stopped at breakpoint tmy all devices instances 1 names tmy0
534 chapter 14 16-bit timer y (tmy) user?s manual u17566ee5v1um00 14.1.1 description the tmy is built up as illustrated below. figure 14-1 block diagram of timer y (tmyn) the control register tynctl is used to choose the clock sources for the two counters and to enable the timer. the latter is done by setting bit tynctl.tynce to 1. the output pin toyn provides the generated pwm or pfm signal. by default, the high-level time of that signal is determined by counter 1, the low-level time is determined by counter 0. however, the signal polarity can be inverted. selector 16-bit down counter tyncnt0 tynr0 clear 16-bit down counter tyncnt1 clear output control s r tynctl.tyce tynr1 selector q q toyn tynctl.tyce ce ce spclk3 (2 mhz) spclk5 (500 khz) spclk6 (250 khz) spclk1 (8 mhz) spclk4 (1 mhz) tycks02 tynctl tycks01 tycks00 internal bus internal bus tycks12 tycks11 tycks10 inttynuv0 tyol tynioc tyncnt00 tyncnt01 tyncnt10 tyncnt11 inttynuv1 reload reload tynctl.tyce tynctl.tyce tynctl.tyce reload buffer reload buffer
535 16-bit timer y (tmy) chapter 14 user?s manual u17566ee5v1um00 14.1.2 principle of operation when tmyn is enabled, the down-counter 0 starts counting as soon as a non- zero value is written to the reload register tynr0 and copied to the associated reload buffer. when counter 0 reaches zero, it generates the maskable interrupt inttynuv0, reloads its start value from its reload buffer, and starts counter 1. in the figure above, this is indicated by the ce (count enable) feedback connection. after that, counter 0 waits for counter 1 to finish. note in order to avoid unintended timing of the output signal during the start-up phase, counter 1 needs a non-zero start value before counter 0 expires (underflows). when counter 1 expires, it generates the maskable interrupt inttynuv1, reloads its start value from the reload buffer of register tynr1, and restarts counter 0. four read-only registers provide the updated counter values. for details about these registers refer to ?tyncntm0 - tmyn synchronized counter registers? on page 537 and ?tyncntm1 - tmyn non-synchronized counter registers? on page 538 the output pin generates a rectangular signal that reflects the running times of both counters. the signal polarity can be chosen. 14.2 registers the timers y are controlled and operated by means of the following registers: table 14-1 tmyn registers overview register name shortcut address timer y synchronized counter 0 read register tyncnt00 timer y non-synchronized counter 0 read register tyncnt01 + 2 h timer y synchronized counter 1 read register tyncnt10 + 4 h timer y non-synchronized counter 1 read register tyncnt11 + 6 h timer y counter 0 reload register tynr0 + 8 h timer y counter 1 reload register tynr1 + a h timer y i/o control register tynioc + c h timer y control register tynctl + d h table 14-2 tmyn register base address timer base address tmy0 ffff f580 h
536 chapter 14 16-bit timer y (tmy) user?s manual u17566ee5v1um00 (1) tynctl - tmyn timer control register the 8-bit tynctl register controls the operation of the timer y. access this register can be read/written in 8-bit or 1-bit units. address + d h initial value 00 h . this register is cleared by any reset. note 1. m = 0 identifies counter 0; m = 1 identifies counter 1. 2. change bits tynctl.tyncksm[2:0] only when tynctl.tynce = 0. 76543210 tynce 0 tyncks12 tyncks11 tyncks10 tyncks02 tyncks01 tyncks00 r/w r r/w r/w r/w r/w r/w r/w table 14-3 tynctl register contents bit position bit name function 7 tynce timer y counter enable: 0: disable count operation (the timer stops immediately with the count values 0000 h and does not operate). 1: enable count operation (the timer starts when a non-zero start value is written to the register tynr0 after tynctl.tynce = 1). 5 to 0 tyncksm[2:0] selects the clock of counter 0 and 1 tyncksm2 tyncksm1 tyncksm0 counter clock selection 000 spclk1 (8 mhz) 010 spclk3 (2 mhz) 011 spclk4 (1 mhz) 100 spclk5 (500 khz) 1 0 1 spclk6 (250 khz) others than above setting prohibited
537 16-bit timer y (tmy) chapter 14 user?s manual u17566ee5v1um00 (2) tynioc - tmyn i/o control register the tynioc register is an 8-bit register that controls the polarity of the timer output signal. access this register can be read/written in 8-bit or 1-bit units. address + c h initial value 00 h . this register is cleared by any reset and by tynctl.tynce = 0. note change tynioc.tynol only when the timer is enabled (tynctl.tynce = 1). (3) tyncntm0 - tmyn synchronized counter registers the tyncntm0 register is the synchronized register that can be used to read the value of the corresponding 16-bit counter m. note m = 0 identifies counter 0; m = 1 identifies counter 1. ?synchronized? means that the read access via the internal bus is synchronized with the maximum counter clock (spclk1). the synchronization process may cause a delay, but the resulting value is reliable. access this register is read-only, in 16-bit units. address tyncnt00: of tmyn tyncnt10: + 4 h initial value 0000 h . this register is cleared by any reset and when tynctl.tynce = 0. 76543210 0000tynol000 rrrrr/wrrr table 14-4 tynioc register contents bit position bit name function 3 tynol timer y output level control: 0: normal: counter 0 generates a rising edge upon underflow, counter 1 a falling edge. 1: inverted: counter 0 generates a falling edge upon underflow, counter 1 a rising edge. 1514131211109876543210 updated counter value (synchronized) r
538 chapter 14 16-bit timer y (tmy) user?s manual u17566ee5v1um00 (4) tyncntm1 - tmyn non-synchronized counter registers the tyncntm1 register is the non-synchronized read register that can be used to read the present value of the concerned 16-bit counter m. note m = 0 identifies counter 0; m = 1 identifies counter 1. ?non-synchronized? means that the read access via the internal bus is not synchronized with the counter clock. the read operation returns the instantaneous value immediately, with the risk that this value is just being updated by the counter and therefore in doubt. access this register is read-only, in 16-bit units. address tyncnt01: + 2 h tyncnt11: + 6 h initial value 0000 h . this register is cleared by any reset and when tynctl.tynce = 0. note the value read from this register can be incorrect, because the read access is not synchronized with the counter clock. therefore, this register shall be read multiple times within one period of the counter clock cycle. if the difference between the first and the second value is not greater than one, you can consider the second value to be reliable. if the difference between the two values is greater than one, you have to read the register a third time and compare the third value with the second. again, the difference must not be greater than one. if the read accesses do not happen within one period of the counter clock cycle, the difference between the last two values will usually be greater than one. in this case, you can only repeat the procedure or estimate the updated counter value. 1514131211109876543210 instantaneous counter value (non-synchronized) r
539 16-bit timer y (tmy) chapter 14 user?s manual u17566ee5v1um00 (5) tynrm - tmyn reload registers the tynrm registers are two 16-bit registers for setting the reload value of the corresponding counters. note m = 0 identifies counter 0; m = 1 identifies counter 1. access these registers can be read/written in 16-bit units. address tynr0: tmyn + 8 h tynr1: tmyn + a h initial value 0000 h . this register is cleared by any reset and when bit tynctl.tynce = 0. note 1. tynrm can only be written when bit tynctl.tynce = 1. 2. to start the counters, the reload values for tynr0 and tynr1 must be greater than 1 (0002 h ? ffff h ). 3. to operate the timers in free running mode, set tynrm to ffff h . 4. if the registers have been cleared, it is recommended to set tynr1 first and then tynr0. 5. once tmyn is enabled, its counter 0 starts as soon as a non-zero start value is written to register tynr0. if this value is small (or the counter frequency high), counter 0 may quickly expire and start counter 1. if counter 1 has no start value at this point of time, it will simply wait until it gets one. this may lead to an unexpected initial delay of the output signal. 1514131211109876543210 down-counter load value r/w
540 chapter 14 16-bit timer y (tmy) user?s manual u17566ee5v1um00 14.3 timing you can change the contents of the reload registers tynrm at any time, provided tynctl.tynce is 1. however, the counters reload their start values when it reaches 0. the following figure illustrates the timer operation. figure 14-2 timer y timing d00, d01, and d02 are the load values for counter 0. d10, d11, and d12 are the load values for counter 1. the figure shows at which point in time the counters load their start values and how they alternate. the output signal at pin toyn is shown in normal mode (bit tynioc.tynol = 0). tyncnt0 tyncnt1 q q d00 d01 tynr0 d10 d11 d02 d12 tyon 0000h 0000h d00 d00 d01 d01 d01 d02 d10 d10 d11 d11 d11 intynuv0 intynuv1 underflow underflow tynr1
541 16-bit timer y (tmy) chapter 14 user?s manual u17566ee5v1um00 14.4 output timing calculations this section provides information on how to calculate the output pulse duration under various conditions. caution when specifying spclk3, splck4, spclk5 or spclk6 as the count clock, a jitter of maximum 1 period of spclk1 may be applied to the tyncnt0 and tyncnt1 counter?s count clock input. the first interval, that means the time until the first underflow, after starting the counters can vary by one count clock period. therefore, different equations are given for the first and all other intervals, where applicable. the following symbols are used: t c0 (t c1 ) : running time of counter 0 (1) t pwm : total pwm interval duration t pwm01 (t pwm10 ) : pwm pulse length between inttznuv0 and inttznuv1 (inttznuv1 and inttznuv0) [tynr0], [tynr1] : contents of tynr0 (tynr1), legal range 0001 h to ffff h (1 to 65535) [tyncks0], [tyncks1] : contents of tynctl[2:0] (tynctl[5:3]), legal range 0 to 5 (1) counter running times running time of counter 0 (t c0 ) and counter 1 (t c1 ): ? first interval: ([tynr0] 2 [tyncks0] ) x 1/f spclk1  t c0  (([tynr0] + 1) 2 [tyncks0] ) x 1/f spclk1 ([tynr1] 2 [tyncks1] ) x 1/f spclk1  t c1  (([tynr1] + 1) 2 [tyncks1] ) x 1/f spclk1 ? all following intervals: t c0 = (([tynr0] + 1) 2 [tyncks0] ) x 1/f spclk1 t c1 = (([tynr1] + 1) 2 [tyncks1] ) x 1/f spclk1 example if [tynr0] = 255 and [tyncks0] = 5, it takes 8192 periods of spclk1 until counter 0 expires, i.e. 1024 ms with f spclk1 =8mhz
542 chapter 14 16-bit timer y (tmy) user?s manual u17566ee5v1um00 (2) total pwm interval length t pwm is the time between two interrupts inttznuv0 (or inttznuv1). if both counters use the same clock ([tyncks0] = [tyncks1]): ? first interval: (([tynr0] + [tynr1]) 2 [tyncks0] ) x 1/f spclk1  t pwm  (([tynr0] + [tynr1] + 2) 2 [tyncks0] ) x 1/f spclk1 ? all following intervals: t pwm = (([tynr0] + [tynr1] + 2) 2 [tyncks0] ) x 1/f spclk1 = (t c0 + t c1 ) x 1/f spclk1
f both counters use different clocks : ([tynr0] 2 [tyncks0] + [tynr1]) 2 [tyncks1] + 2) x 1/f spclk1  t pwm  (([tynr0] + 1) 2 [tyncks0] + ([tynr1] + 1) 2 [tyncks1] + 4) x 1/ f spclk1 (3) pulse width t pwm01 between inttynuv0 and inttynuv1 if both counters use the same clock ([tyncks0] = [tyncks1]): ? first interval: ([tynr1] 2 [tyncks1] ) x 1/f spclk1  t pwm01  (([tynr1] + 1) 2 [tyncks1] ) x 1/f spclk1 ? all following intervals: t pwm01 = ([tynr1] + 1) 2 [tyncks1] if both counters use different clocks : ([tynr1] 2 [tyncks1] + 1) x 1/f spclk1  t pwm01  (([tynr1] + 1) 2 [tyncks1] + 2) x 1/f spclk1 example if [tynr1] = 255 and [tyncks1] = 2, then ? [tynr1] 2 [tyncks1] = 1020 ? ([tynr1] + 1) 2 [tyncks1] = 1024 ?t pwm01 is between 1021 and 1026 periods of spclk1, i.e. between 127,625 s and 128,5 s with f spclk1 =8mhz (4) pulse width t pwm10 between inttynuv1 and inttynuv0 if both counters use the same clock ([tyncks0] = [tyncks1]): ? first interval: ([tynr0] 2 [tyncks0] ) x 1/f spclk1  t pwm10  (([tynr0] + 1) 2 [tyncks0] ) x 1/f spclk1
543 16-bit timer y (tmy) chapter 14 user?s manual u17566ee5v1um00 ? all following intervals: t pwm10 = (([tynr0] + 1) 2 [tyncks0] ) x 1/f spclk1 if both counters use different clocks : ([tynr0] 2 [tyncks0] + 1) x 1/f spclk1  t pwm10  (([tynr0] + 1) 2 [tyncks0] + 2) x 1/f spclk1
544 chapter 14 16-bit timer y (tmy) user?s manual u17566ee5v1um00
545 user?s manual u17566ee5v1um00 chapter 15 watch timer (wt) the watch timer (wt) generates interrupts at regular time intervals. these interrupts are generally used as ticks for updating the internal daytime and calendar. the watch timer includes two identical counters. throughout this chapter, the counters are identified as wtn, where n = 0 to 1. 15.1 overview the watch timer consists of two 16-bit down-counters, wt0 and wt1, and includes the watch calibration timer wct. wt0 the load value that must be set for wt0 depends on the chosen clock frequency and the desired time interval between two interrupts. for example, wt0 can be set up to generate an interrupt every second (intwt0uv). during normal operation, the clock of wt0 (wtclk) is directly derived from the precision main oscillator. it bypasses the pll and sscg. however, the wtclk can also be derived from the sub or internal oscillator. this is useful if the main oscillator is switched off in order to save power. wt1 wt1 is clocked by the interrupts generated by wt0. it can, for example, generate an interrupt every hour (or whatever wake-up time is required). this interrupt (intwt1uv) can be used to escape from sub-watch mode and hence to revive the main oscillator if necessary. wct the sub or internal oscillators used in sub_watch mode are not as stable as the main oscillator. the time between two wt0 interrupts may be slightly shorter or longer than desired. therefore a third timer - the watch calibration timer (wct) - can be used occasionally to measure the time between two interrupts intwt0uv. wct requires the main oscillator clock for this measurement. its clock, wctclk, always stops if the main oscillator stops, that means if stop mode or sub-watch mode are entered. based on the measurement result, a new load value for wt0 can be calculated. this is the solution to regain precise intervals between wt0 interrupts. after the adjustment of wt0, the system can return to sub-watch mode where the main oscillator is stopped.
546 chapter 15 watch timer (wt) user?s manual u17566ee5v1um00 features summary special features of the watch timer are: ? periodic interrupts (clock ticks) generated by two down-counters ? two reload registers, one for each counter ? choice of oscillators to reduce power consumption in stand-by mode ? can operate in all power save modes ? clock correction in stand-by mode by means of the watch calibration timer ? in debug mode, the counters wt0 and wt1 can be stopped at breakpoint special features of the watch calibration timer are: ? 16-bit counter register tm00 ? 16-bit capture / compare register cr001 ? capture / trigger input for intwt0uv with edge specification for intwt0uv interval measurement ? capture / match interrupt request signal inttm01
547 watch timer (wt) chapter 15 user?s manual u17566ee5v1um00 15.1.1 description the following figure shows the structure of the watch timer and its connection to the watch calibration timer. figure 15-1 watch timer configuration as shown in the figure, wt0 is clocked by wtclk, a clock generated by the clock generator. when wt0 counts down to zero, it generates the intwt0uv interrupt. wt1 is clocked by the interrupts intwt0uv. when wt1 reaches zero, it generates the interrupt intwt1uv. two control registers wtnctl are used to enable the counters. this is done by setting wtnctl.wtce to 1. as soon as the counters are enabled, it is possible to write a start value to the reload registers wt0r and wt1r. wct is a capture/compare timer. in this application, it measures the time between two intwt0uv interrupts. it is clocked by wctclk, another clock generated by the clock generator. wt0cnt1 cr001 watch calibration timer watch timer 16-bit up-counter tm00 edge detector 16-bit down-counter wt0 16-bit down-counter wt1 prm00.es00[1:0] wt0cnt0 wt0r reload buffer internal bus internal bus wt1cnt1 wt1cnt0 wt1r reload buffer wt0ctl.ce wtclk wctclk wt1ctl.ce tmc00.tmc00[3:2] mode selector intwt0u (short interval) intwt0u inttm01 intwt1u (long interval) reload reload on match
548 chapter 15 watch timer (wt) user?s manual u17566ee5v1um00 15.1.2 principle of operation in order to generate an interrupt every one or two seconds, wtclk is usually set to a frequency around 30 khz. then, a load value around 2 15 will yield a running time of about 1 s. (1) operation control of wt0 the source and frequency of wtclk are specified in the clock generator register tcc. the clock generator contains a programmable frequency divider that makes it possible to scale down the selected clock source. note wtclk uses the same clock source and clock divider as the lcd controller/ driver clock lcdclk. the frequency f wtclk can be the same as f lcdclk or f lcdclk / 2. for details refer to ?clock generator? on page 139 . typical settings and the resulting maximum time interval between two interrupts are listed in the table below. note that you can double the maximum period by setting tcc.wtsel1 to 1. the clock input can be disabled (wt0ctl.wtce = 0). this stops the watch timer. after reset, the timer is also stopped. when wt0 is enabled and a non-zero reload value is specified, the counter decreases with every rising edge of wtclk. when the counter reaches zero, the interrupt intwt0uv is active high for one clock cycle. upon undeflow, i.e. with the next clock, the timer reloads its start value and resumes down- counting. the load value can be freely chosen (2) operation of wt1 once wt1 is enabled and a non-zero reload value is specified, its counter decreases with every interrupt intwt0uv. when wt1 reaches zero, it generates the interrupt intwt1uv. upon undeflow, i.e. with the next clock, the timer reloads its load value and restarts down-counting. the load value can be freely chosen. starting wt1 requires some attention. for further details refer to ?watch timer start-up? on page 555 . table 15-1 typical settings of wtclk clock source clock divider setting wtclk frequency max. period of intwt0uv a 4 mhz main osc. 1 / 128 31.25 khz 2.097 s 32 khz sub osc. 1 32.768 khz (typ.) 2.0 s 240 khz internal osc. 1 / 8 30 khz (typ.) 2.184533 s a) the maximum period corresponds to a counter load value of 2 16 ? 1.
549 watch timer (wt) chapter 15 user?s manual u17566ee5v1um00 (3) operation of wct the third counter wct is used for clock correction. this counter is connected to pclk1 (8 mhz) or directly to the 4 mhz main oscillator. it is used to measure the time between two intwt0uv requests. for this measurement, wct is configured as a capture timer. once it is enabled, the wct counter is increased with every rising edge of its clock. when the value ffff h is reached, the counter sets a flag and restarts with 0000 h . the interrupt intwt0uv from counter wt0 triggers the capture operation. at every intwt0uv, the count value is captured, and the interrupt inttm01 is generated. from the counter difference between two consecutive capture events, the accuracy of the wtclk can be measured, and wt0 or wt1, respectively, can be corrected. the wct can be programmed to restart counting after the capture operation. note the wct detects the valid edge of intwt0uv by sampling its input signal (the intwt0uv interrupt line) with wctclk. the capture operation is only performed if the same level after a valid edge is detected two times in series. as a consequence, the time interval measurement will only work correctly if f wtclk < f wctclk / 2.
550 chapter 15 watch timer (wt) user?s manual u17566ee5v1um00 15.2 watch timer registers the watch timer counters wt0 and wt1 are controlled and operated by means of the following registers: (1) wtnctl - wtn timer control register the 8-bit wtnctl register controls the operation of the timer wtn. access this register can be read/written in 8-bit or 1-bit units. address + 6 h initial value 00 h . this register is cleared by any reset. note 1. if wtnctl.wtce is 1, the counter starts after the counter's load value has been written to the reload register wtnr. as long as wtnr is zero, no counting is performed, and no interrupts intwtnuv are generated. 2. the first interval from counter start to the first underflow takes at least four clock cycles more than the following intervals. for details refer to ?watch timer start-up? on page 555 . table 15-2 wtn registers overview register name shortcut address watch timer synchronized read register wtncnt0 watch timer non-synchronized read register wtncnt1 + 2 h watch timer reload register wtnr + 4 h watch timer control register wtnctl + 6 h table 15-3 wtn register base addresses timer base address wt0 ffff f560 h wt1 ffff f570 h 76543 2 1 0 wtce0000 0 0 0 r/wrrrr r r r table 15-4 wtnctl register contents bit position bit name function 7 wtce watch timer counter enable: 0: disable count operation (the timer stops immediately with the count value 0000 h and does not operate). 1: enable count operation.
551 watch timer (wt) chapter 15 user?s manual u17566ee5v1um00 (2) wtncnt0 - wtn synchronized counter register the wtncnt0 register is the synchronized register that can be used to read the present value of the 16-bit counter. ?synchronized? means that the read access via the internal bus is synchronized with the counter clock. the synchronization process causes a delay, but the resulting value is reliable. access this register is read-only, in 16-bit units. address of wtn initial value 0000 h . this register is cleared by any reset and if wtnctl.wtce = 0. note due to the low frequencies of the counter clocks, the synchronization can take about up to two wtclk. for a quick response, it is recommended to read the non-synchronized counter register wtncnt1. 1514131211109876543210 updated counter value (synchronized) r
552 chapter 15 watch timer (wt) user?s manual u17566ee5v1um00 (3) wtncnt1 - wtn non-synchronized counter read register the wtncnt1 register is the non-synchronized register that can be used to read the present value of the corresponding 16-bit counter. ?non-synchronized? means that the read access via the internal bus is not synchronized with the counter clock. it returns the instantaneous value immediately, with the risk that this value is just being updated by the counter and therefore in doubt. access this register is read-only, in 16-bit units. address + 2 h initial value 0000 h . this register is cleared by any reset and if wtnctl.wtce = 0. note the value read from this register can be incorrect, because the read access is not synchronized with the counter clock. therefore, this register shall be read multiple times within one period of the counter clock cycle. if the difference between the first and the second value is not greater than one, you can consider the second value to be correct. if the difference between the two values is greater than one, you have to read the register a third time and compare the third value with the second. again, the difference must not be greater than one. if the read accesses do not happen within one period of the counter clock cycle, the difference between the last two values will be greater than one. in this case, you can only repeat the procedure or estimate the updated counter value. reading the counter value via wtncnt1 instead of wtncnt0 is only reasonable if the cpu clock is remarkably higher than wtclk and the overhead of multiple reading wtncnt1 is justifiable. 1514131211109876543210 instantaneous counter value (non-synchronized) r
553 watch timer (wt) chapter 15 user?s manual u17566ee5v1um00 (4) wtnr - wtn reload register the wtnr register is a dedicated register for setting the reload value of the corresponding counter. access this register can be read/written in 16-bit units. address + 4 h initial value 0000 h . this register is cleared by any reset and if wtnctl.wtce = 0. note 1. wtnr can only be written if wtnctl.wtce = 1 (counter enabled). 2. the load value must be non-zero (0001 h ?ffff h ). 3. the contents of this register is automatically copied to the reload buffer. the counters load their values from the respective buffers at underflow. to ensure correct operation, this register shall not be written twice within three cycles of the counter clock. a second write attempt within that time span is ignored. this time span of three cycles of the counter clock is stalled and not cleared if wtnctl.wtce is cleared to 0. after restarting the counter by setting wtnctl.wtce back to 1, the time span will continue to elapse, but the counter will not be started automatically. 4. the value read from wtnr is the target start value. it is not necessarily identical with the current start value that is stored in the reload buffer. the buffer may not yet be updated. 1514131211109876543210 down-counter load value r/w
554 chapter 15 watch timer (wt) user?s manual u17566ee5v1um00 15.3 watch timer operation this section describes the operation of the watch timer counters in detail. 15.3.1 timing of steady operation the contents of the reload registers wtnr can be changed at any time, provided the corresponding counter is enabled. the contents is then copied to the reload buffer. the counters wtn reload their start value from the buffer upon underflow. this is illustrated in the following figure. figure 15-2 reload timing and interrupt generation d0 and d1 are two different reload values. note also that there is a delay between writing to wtnr and making the data available in the reload buffer, depending on the previous reload value and the chosen count clock. d 0 d 0 d 1 d 1 d 0 d 0 d 0 d 1 d 0 d 1 d 0 0000 h 16 - bit down counter value reload buffer wtnr intwtnuv
555 watch timer (wt) chapter 15 user?s manual u17566ee5v1um00 15.3.2 watch timer start-up the first interval after starting wt0 and wt1 until their first underflow takes at least four additional input clock cycles. at this point in time, the values of the counter registers wtncnt are not correct. after the first automatic reload of the wtnr value, the counter registers wtncnt hold the correct number of clock cycles since the last underflow. in the following, the start-up procedure of wt1 is described, because of its higher relevance from an application point of view. however, all statements refer also to wt0. start-up timing starting wt1 correctly requires some attention in order to avoid wrong calculation of the watch time. if wt1 is used as an extended watch timer counter, two steps in the following order are required: ? the counter has to be enabled by setting wt1ctl.wtce = 1. ? the counter's reload register wt1r has to be set to a non-zero value. both actions consume a different amount of input clock cycles to become effective, as shown in the following diagram. figure 15-3 wt1 start-up timing to start the counter in a deterministic way, the above actions have to be synchronized to the wt1 input clock, which is intwt0uv. for that purpose it is recommended to maintain a software counter that is increased inside the intwt0uv interrupt service routine. by this means, it is ensured that the actions are performed at the correct point in time. setting wt1ctl.wtce to 1 enables wt1. the write access can happen at any time. due to internal clock synchronization, it takes at least five complete input clock cycles, that means four intwt0uv intervals (wtce validation time 0 ?> 1 ?> 2 ?> 3 ?> 4) to become effective. after that, wt1 is prepared to acknowledge the reload value. s/w counter state ?4? indicates that the reload value can be written now (wt1r > 0). this time, at least three complete input clock cycles (wtr1 validation time 5 ?> 6 ?> 7 ?>8) are required to take over the reload value from wt1r to the reload buffer and to start counting. at s/w counter state ?8? the counter wt1cnt is preloaded with the wt1r contents. intwt0uv wt1ctl.wtce=1 wt1r intwt0uv s/w counter 0 1 2 3 4 5 6 7 8 9 wt1r = 0 wt1r > 0 wt1 start stopped started wtce validation wt1r validation
556 chapter 15 watch timer (wt) user?s manual u17566ee5v1um00 as a consequence, register wt1cnt does not show the correct number of intwt0uv events after wt1r > 0, but a value of four less: ? 1 intwt0uv cycle 4 ?> 5 taken for the cycle wt1r is written ? 3 intwt0uv cycles 5 ?> 6 ?> 7 ?> 8 for wt1r validation time the above calculation assumes that wt1r is written within one intwt0uv cycle, which is highly probable, considering intwt0uv to be the "one second tick". however, it may happen that the write to wt1r is delayed because of other circumstances (nested interrupts, dma transfers, etc.) and may happen after s/w counter state 3. thus, wt1 would start later, since the 3 clock wtr1 validation time is maintained. in order to recognize that situation, read the wt1cnt1 register and compare its contents with the value written to wt1r. if both are equal, wtr1 has been written before s/w counter state 3, add four when reading wt1cnt. if they are not equal check again at next intwt0uv and add the proper number of correction cycles.
557 watch timer (wt) chapter 15 user?s manual u17566ee5v1um00 15.4 watch calibration timer registers the watch calibration timer is controlled by means of the following registers: table 15-5 wct registers overview register name shortcut address wct timer / counter read register tm00 wct capture / compare register cr001 + 4 h wct mode control register tmc00 + 6 h wct prescaler mode register prm00 + 7 h wct capture / compare control register crc00 + 8 h table 15-6 wct register base address timer base address wct ffff f5e0 h
558 chapter 15 watch timer (wt) user?s manual u17566ee5v1um00 (1) tmc00 - wct mode control register the 8-bit tmc00 register controls the operation of the wct. access this register can be read/written in 8-bit or 1-bit units. address + 6 h initial value 00 h . this register is cleared by any reset. note 1. if an attempt is made to change the setting of tmc00[3:2] while the timer is running, these bits are cleared and the timer is stopped. if the timer is stopped, you can change the operation mode. 2. the ovf00 bit is set if the counter reaches ffff h and once more if the counter continues with 0000 h . clearing ovf00 within that time has no effect. 7654 3 2 1 0 0000tmc003tmc0020ovf00 rrrrr/wr/w r r/w table 15-7 tmc00 register contents bit position bit name function 3 to 2 tmc00[3:2] operation mode selection: tmc003 tmc002 operating mode 00 stop mode 01 free-running mode. generates interrupt on match between tm00 and cr001. 1x setting prohibited. 0 ovf00 counter overflow indicator: 0: no overflow 1: overflow occurred
559 watch timer (wt) chapter 15 user?s manual u17566ee5v1um00 (2) prm00 - wct prescaler mode register the 8-bit prm00 register is used to select the ?valid edge? of intwt0uv for interval measurements. access this register can be read/written in 8-bit or 1-bit units. address + 7 h initial value 00 h . this register is cleared by any reset. all other bits are initialized as zero and must not be changed. note 1. if both edges of intwt0uv are specified as valid, intwt0uv interval measurement is not possible. 2. stop the timer before changing es00[1:0]. 7654 3 2 1 0 0 0 es001 es000 0 0 0 0 rrr/wr/wr r r r table 15-8 prm00 register contents bit position bit name function 5 to 4 es00[1:0] edge selection: es001 es000 valid edge 00 falling edge 01 rising edge 10 setting prohibited 11 both rising and falling edges
560 chapter 15 watch timer (wt) user?s manual u17566ee5v1um00 (3) crc00 - wct capture / compare control register the 8-bit crc00 register controls t he operation of the capture/compare register cr001. access this register can be read/written in 8-bit or 1-bit units. address + 8 h initial value 00 h . this register is cleared by any reset. note 1. stop the timer before changing the contents of this register. 2. if both the rising edge and falling edge are specified as valid for the intwt0uv signal, the interval measurement does not work. 3. be sure to set bits 7 to 3 and 1 to 0 to 0. 7654 3 2 1 0 0000 0 crc002 0 0 rrrr r r/wr/wr/w table 15-9 crc00 register contents bit position bit name function 2 crc002 selects the operation mode of cr001: 0: operates as a compare register. 1: operates as capture register.
561 watch timer (wt) chapter 15 user?s manual u17566ee5v1um00 (4) cr001 - wct capture / compare register 1 the 16-bit cr001 register can be used as a capture register or as a compare register. whether it is used as a capture register or compare register is specified in bit crc00.crc002. ? compare mode: in compare mode, the value written to cr001 is continually compared with the count value of tm00. if the two values match, the interrupt request inttm01 is generated. ? capture mode: in capture mode, the count value of tm00 is copied to cr001 upon a valid edge of intwt0uv. then, the interrupt inttm01 is generated. the valid edge of intwt0uv can be selected as a capture trigger. the valid edge is specified in prm00.es00[1:0]. in capture mode, a read access to register cr001 is not synchronized with the counter operation. read access and register update can occur simultaneously. if that happens, cr001 holds the correct value, but the value read is undefined. access in compare mode, this register can be read/written in 16-bit units. in capture mode, it cannot be written. address + 4 h initial value 0000 h . this register is cleared by any reset. note stop the timer before changing the contents of this register. (5) tm00 - wct timer / counter read register the tm00 register can be used to read the present value of the 16-bit up- counter. the counter is increased with every rising edge of the input clock. if the counter value is read while the counter is running, input of the count clock is temporarily stopped, and the counter value at this point is read. access this register is read-only, in 16-bit units. address initial value 0000 h . this register is cleared by any reset, if the counter is stopped (tmc00.tmc00[3:2] = 0), and if the counter is in intwt0uv interval measurement mode and a valid edge of intwt0uv is detected. if the counter overflows, it sets the flag tmc00.ovf00 to 1 and continues with 0000 h . 1514131211109876543210 compare or captured value (captured from tm00) r(w) 1514131211109876543210 counter value r
562 chapter 15 watch timer (wt) user?s manual u17566ee5v1um00 15.5 watch calibration timer operation the watch calibration timer wct is used to measure the time between two successive occurrences of the watch timer wt0 underflow interrupt intwt0uv. the wct is supplied with the stable clock wctclk: ? wctclk = 4 mhz main oscillator, if psm.cmode = 1 ? wctclk = 8 mhz pclk1, if psm.cmode = 0 for further details refer to ?clock generator? on page 139 . the measured intwt0uv interval time gives an indication about the accuracy of the sub or internal oscillator. a correction value can be calculated to calibrate wt0 and wt1 by changing their reload values. the interval measurement can be performed in the wct free-running operating mode. if a timer overflow can occur during the interval measurement, take care for regarding also the overflow flag tmc00.ovf00 for calculating the interval correctly. the timer operating as a free-running counter performs following actions upon detection of a the valid edge of intwt0uv: ? it copies the present counter value of register tm00 to cr001, ? it generates the interrupt request inttm01. the valid edge (rising edge, falling edge) is specified in register prm00. if both edges are specified, cr001 cannot perform a capture operation. setup example tmc00 = 0000 0100 b : free running mode crc00 = 0000 0100 b : cr001 as capture register with intwt0uv as capture signal prm00.es00[1:0] = 01 b : rising edge the following figure is not to scale but illustrates the operation.
563 watch timer (wt) chapter 15 user?s manual u17566ee5v1um00 figure 15-4 timing in free-running mode as shown in the figure, the interrupt inttm01 can be used as a trigger for reading the register cr001. the interval duration must be calculated from the difference between the present and the previous value of cr001. note if tm00 overflows between two occurrences of intwt0uv, that means between two capture triggers, the overflow flag tmc00.ovf00 is set. therefore, check also tmc00.ovf00 when reading the second capture value in order to calculate the interval correctly, because an overflow may happen during the measurement. consider the chosen periods for intwt0uv and of wctclk. t wctclk 0000 h 0000 h ffff h 0001 h d0 d0 + 1 d1 d0 d1 d2 d3 d2 d3 d1 + 1 (d1 ? d0) t wctclk (d3 ? d2) t wctclk (10000 h ? d1 + d2) t wctclk wctclk tm00 intwt0uv cr001 inttm01 ovf00
564 chapter 15 watch timer (wt) user?s manual u17566ee5v1um00
565 user?s manual u17566ee5v1um00 chapter 16 watchdog timer (wdt) the watchdog timer is used to escape from a system deadlock or program runaway. if it is not restarted within a certain time, the watchdog timer flows over and interrupts or even resets the microcontroller. 16.1 overview the watchdog timer contains an up-counter that is driven by the watchdog timer clock wdtclk. this clock can be derived from the main oscillator, the internal oscillator, or the sub oscillator. it?s frequency can be identical with the frequency of the source clock or a fraction thereof. features summary the watchdog timer ? can generate the non-maskable interrupt nmiwdt ? can generate a hardware reset by means of the internal signal reswdt ? has a programmable running time (set in terms of 2 n multiples of wdtclk periods) ? is specially protected against inadvertent setup changes
566 chapter 16 watchdog timer (wdt) user?s manual u17566ee5v1um00 16.1.1 description the following figure shows a simplified block diagram. figure 16-1 block diagram of the watchdog timer as shown in the figure, the wdcs register controls the running time and the wdtm register the operating mode. the running time can be chosen between 2 13 and 2 20 times the period of the watchdog timer clock wdtclk. the figure shows also, that the run and mode settings of the wdtm register are only cleared by sysreswdt. 16.1.2 principle of operation before the watchdog timer is started, its running time and mode have to be configured. the watchdog timer has two operating modes: ? mode 0 (generate non-maskable interrupt nmiwdt) ? mode 1 (generate reset request reswdt) the mode is defined by the bit wdtm.wdtmode. the mode can only be changed after sysreswdt, that means, after external reset or power-on clear. (1) watchdog timer mode 0 (generate non-maskable interrupt nmiwdt) if wdtm.wdtmode is 0, the watchdog timer is in interrupt-request mode. this is the default after initialization. setting bit wdtm.run to 1 starts the counter. without intervention, the timer will now run until the specified time has elapsed and then generate the non- maskable interrupt nmiwdt. after that, the counter is reset to zero and starts counting again. wdtclk clear counter/timer internal bus runtime select or 2 13 output control circuit reswdt nmiwdt wdcs2 wdcs1 wdcs0 wdcs run wdtmode wdtm / wdtclk 2 14 / wdtclk 2 15 / wdtclk 2 16 / wdtclk 2 17 / wdtclk 2 18 / wdtclk 2 19 / wdtclk 2 20 / wdtclk sysres sysreswdt reset sysreswdt reset overflow
567 watchdog timer (wdt) chapter 16 user?s manual u17566ee5v1um00 (2) watchdog timer mode 1 (generate reset request reswdt) if wdtm.wdtmode is 1, the watchdog timer is in reset-request mode. setting bit wdtm.run to 1 starts the counter. without intervention, the timer will now run until the specified time has elapsed and then generate the internal reswdt signal. after that, the counter operation is stopped until the system reset sysres or sysreswdt occurs. (3) watchdog timer running once it is running, the watchdog timer cannot be stopped by software. it can only be stopped by the reset signal sysreswdt. this signal is generated by the reset module at power-on and external reset . the way to prevent the timer from flowing over is writing to the register wdtm before the specified time has elapsed. the write access resets the counter to zero. 16.1.3 watchdog timer clock the watchdog timer clock wdtclk is generated by the clock generator. it can be derived from the main, internal or sub oscillator. the generation of wdtclk is controlled by the wcc register of the clock generator. in this register, it is possible to choose the main, sub, or internal oscillator as the clock source (wcc.soscw, wcc.wdtsel0). you can also choose a suitable frequency divider between 1 and 128 (wcc.wps[2:0]). wdtclk is subject to a stand-by mode control. wdtclk can optionally be stopped in idle, watch, sub-watch and stop mode (wcc.wdtsel1). please refer to ?clock generator? on page 139 for further details. note once the timer has been started, do not switch off the selected clock source of wdtclk. when the microcontroller is in halt mode, the watchdog timer remains active. the activity in the other power save modes can be specified by the wcc.wdtsel1 control bit. by default (wcc.wdtsel1 = 0), wdtclk stops during idle, watch, sub-watch and stop mode. with wcc.wdtsel1 = 1 wdtclk operates as long as the selected clock source operates. when the wdtclk resumes operation, the watchdog timer is not reset but continues counting. to prevent a quick and unexpected overflow, it is recommended to write to wdtm and thus clear the watchdog timer counter before entering one of these power save modes.
568 chapter 16 watchdog timer (wdt) user?s manual u17566ee5v1um00 16.1.4 reset behavior the reset of the watchdog timer is controlled by the two reset inputs sysres and sysreswdt. the respective signals are generated by the reset module. every reset sets the wdcs register to the longest possible running time. sysreswdt the watchdog reset sysreswdt is used to initialize the watchdog timer. this signal is generated at power-on and after external reset . after sysreswdt, all registers are set to their reset values, and the timer is stopped. you have to write the required settings to the wdcs register and may start the counter. once the counter has been started, it cannot be reprogrammed or stopped unless the next reset (sysres or sysreswdt) occurs. sysres sysres is generated by all reset sources. sysres does not reset the register wdtm. that means, the timer status (running or stopped) and mode (generate interrupt or reset request) remain unchanged. if the watchdog timer was running before sysres was released, the counter is automatically cleared and restarts with the new timing. note 1. every reset clears also the wcc register. that means, the wdtclk has the frequency of the 240 khz internal oscillator. in combination with the largest time factor (2 20 ), this yields a running time of 4.37 s. 2. after any reset, the write protection for wdcs is disabled. wdcs can be written once to specify a shorter time interval. after that, the wdcs register is write-protected.
569 watchdog timer (wdt) chapter 16 user?s manual u17566ee5v1um00 16.2 watchdog timer registers the watchdog timer is controlled by means of the following registers: the registers wdcs and wdtm are protected against accidental changes. a special write procedure, employing the wcmd register, ensures that these registers are not easily rewritten in case of a program hang-up. their contents can only be changed after a reset. in addition, the registers are write-protected when the timer is running. their protection status is indicated in the wdtm register. note only byte access is supported for the registers wdcs, wcmd and wdtm. the registers are allocated at even addresses. thus, they cannot be written by a consecutive byte write sequence or a consecutive half word or word write sequence. table 16-1 watchdog timer registers overview register name shortcut address watchdog timer clock selection register wdcs watchdog timer command protection register wcmd + 2 h watchdog timer mode register wdtm + 4 h watchdog timer command status register wphs + 6 h table 16-2 wdt register base address timer base address wdt ffff f590 h
570 chapter 16 watchdog timer (wdt) user?s manual u17566ee5v1um00 (1) wdcs - wdt clock selection register the 8-bit wdcs register is used to specify the running time of the watchdog timer. access this register can be read/written in 8-bit or 1-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?wcmd - wdt command protection register? on page 573 for details. address initial value 07 h . this register is initialized by sysreswdt and sysres. note the wdcs register must be considered in conjunction with the wcc register of the clock generator. the source and frequency of wdtclk are defined in the wcc register. 76543210 wdcs2 wdcs1 wdcs0 r r r r r r/w r/w r/w table 16-3 wdcs register contents bit position bit name function 2 to 0 wdcs[2:0] specifies the running time of the watchdog timer wdcs2 wdcs1 wdcs0 running time calculation 000 2 13 / f wdtclk 001 2 14 / f wdtclk 010 2 15 / f wdtclk 011 2 16 / f wdtclk 100 2 17 / f wdtclk 101 2 18 / f wdtclk 110 2 19 / f wdtclk 111 2 20 / f wdtclk
571 watchdog timer (wdt) chapter 16 user?s manual u17566ee5v1um00 the running time depends on the frequency of the chosen clock. the following table shows two examples for 4 mhz and 32 khz. these are just two examples for wdtclk. the actual clock signal depends on the clock divider settings and the external oscillator resonators. note every reset sets the wdcs register to 07 h , which means the longest time interval. after sysreswdt, the timer is always stopped and initialized. you can write a smaller value to the register. after sysres, the wdtm register is not cleared. if the watchdog timer was running before sysres occurred, it remains active. to specify a shorter interval: 1. write one byte to the wcmd register (the value is ignored) 2. immediately after that, write one byte with the desired value of wdcs[2:0] to the wdcs register the write operation resets the watchdog counter to zero, and it continues with the new timing. note when the timer is active, wdcs can only be written once after reset. then, the register is locked until the next reset occurs (wdtm.lock_cs = 1). table 16-4 running time examples wdcs2 wdcs1 wdcs0 calculation time until overflow f wdtclk = 4 mhz (main oscillator) f wdtclk = 32 khz (sub oscillator) 0002 13 / f wdtclk 2 ms 256 ms 0012 14 / f wdtclk 4.1 ms 512 ms 0102 15 / f wdtclk 8.2 ms 1.02 s 0112 16 / f wdtclk 16.4 ms 2.05 s 1002 17 / f wdtclk 32.8 ms 4.10 s 1012 18 / f wdtclk 65.5 ms 8.20 s 1102 19 / f wdtclk 131 ms 16.38 s 1112 20 / f wdtclk 262 ms 32.77 s
572 chapter 16 watchdog timer (wdt) user?s manual u17566ee5v1um00 (2) wdtm - wdt mode register this register sets the operating mode of the watchdog timer and enables or disables counting. when the watchdog timer is running and shall not overflow, it is necessary to write to wdtm before the specified running time has elapsed. access this register can be read/written in 8-bit units. once the watchdog timer is started (wdtm.run = 1), the contents of this register cannot be changed. writing to this register is protected by a special sequence of instructions. please refer to ?wcmd - wdt command protection register? on page 573 for details. address + 4 h initial value 00 h . this register is cleared by sysreswdt. this stops the timer and unlocks the registers. the register remains unchanged after sysres. note after sysreswdt, the timer is always stopped and initialized. you can change the register contents by writing. when the timer is running, you can also write to this register, but the write operation does not change the register contents (wdtm.lock_tm = 1). when the timer is running, the write access resets the counter. to write to the wdtm register: 1. write one byte to the wcmd register (the value is ignored). 2. immediately after that, write one byte to the wdtm register (the value is ignored). with this procedure, restarting the counter is always possible, regardless of the register?s write protection status. 76543210 run lock_tm lock_cs 0 wdtmode 000 r/w r r r r/w r r r table 16-5 wdtm register contents bit position bit name function 7 run watchdog timer running: 0: timer stopped 1: timer running (with the time interval specified in register wdcs) 6 lock_tm wdtm register protection status: 0: register unlocked 1: register locked (write-protected) 5 lock_cs wdcs register protection status: 0: register unlocked 1: register locked (write-protected) 3 wdtmode watchdog timer operation mode: 0: mode 0: generates the non-maskable interrupt nmiwdt upon overflow 1: mode 1: generates reswdt upon overflow
573 watchdog timer (wdt) chapter 16 user?s manual u17566ee5v1um00 (3) wcmd - wdt command protection register the 8-bit wcmd register is write-only. it is used to protect the wdtm and wdcs registers from unintended writing. access this register can be written in 8-bit units. address + 2 h initial value undefined any data written to this register is ignored. only the write action is monitored. after writing to the wcmd register, you are permitted to write once to one of the protected registers. this must be done immediately after writing to the wcmd register. if the second write action does not follow immediately, the protected registers are write-locked again. see also ?write protected registers? on page 135 . with this method, the protected registers can only be rewritten in a specific sequence. illegal write access to a protected register is inhibited. the following registers are protected: ? wdcs: watchdog clock selection register ? wdtm: watchdog mode control register an invalid write attempt to one of the above registers sets the error flag wphs.wprerr. wphs.wprerr is also set, if a write access to wcmd is not followed by an access to one of the protected registers. data read from the wcmd register is undefined. caution in case a high level programming language is used, make sure that the compiler translates the two write instructions to wcmd and the protected register into two consecutive assembler ?store? instructions. 76543210 xxxxxxxx wwwwwwww
574 chapter 16 watchdog timer (wdt) user?s manual u17566ee5v1um00 (4) wphs - wdt command status register the wphs register monitors the success of a write instruction to the wdtm and wdcs registers. if the write operation to wdtm or wdcs failed because wcmd was not written immediately before writing to wdtm or wdcs, the wprerr flag is set. access this register can be read/written in 8-bit or 1-bit units. after a write access, the register is cleared. address + 6 h initial value 00 h . this register is cleared by sysreswdt and any write access. 76543210 00 0 0 0 0 0 wprerr rrrrrrrr table 16-6 wphs register contents bit position bit name function 0 wprerr error flag: 0: no wdtm or wdcs register writing error has occurred 1: a wdtm or wdcs register writing error has occurred
575 user?s manual u17566ee5v1um00 chapter 17 asynchronous serial interface (uarta) the v850e/dx3 microcontrollers have following instances of the universal asynchronous serial interface uarta: throughout this chapter, the individual instances of uarta are identified by ?n?, for example, uartan, or uanctl0 for the uartan control register 0. 17.1 features ? transfer rate: 300 bps to 1000 kbps (using dedicated baud rate generator) ? full-duplex communication: ? internal uarta receive data register n (uanrx) ? internal uarta transmit data register n (uantx) ? 2-pin configuration: ? txdan: transmit data output pin ? rxdan: receive data input pin ? reception error output function ?parity error ? framing error ?overrun error ? interrupt sources: 3 ? reception complete interrupt (intuanr): this interrupt occurs upon transfer of receive data from the shift register to receive buffer register n after serial transfer completion, in the reception enabled status. ? transmission enable interrupt (intuant): this interrupt occurs upon transfer of transmit data from the transmit buffer register to the shift register in the transmission enabled status. ? receive error interrupt (intuanre): this interrupt occurs upon transfer of erroneous receive data. ? character length: 7, 8 bits ? parity function: odd, even, 0, none ? transmission stop bit: 1, 2 bits ? on-chip dedicated baud rate generator ? msb-/lsb-first transfer selectable ? transmit/receive data inverted input/output possible uarta all devices instances 2 names uarta0 to uarta1
576 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 ? 13 to 20 bits selectable for the sbf (sync break field) in the lin (local interconnect network) communication format ? recognition of 11 bits or more possible for sbf reception in lin communication format ? sbf reception flag provided ? dma support two different dma trigger events in transmission mode (refer to ?dma controller (dmac)? on page 349 ) 17.2 configuration the block diagram of the uartan is shown below. figure 17-1 block diagram of asynchronous serial interface uartan note for the configuration of the baud rate generator, see figure 17-11 on page 599 . uartan consists of the following hardware units. internal bus uanopt0 uanctl0 uanstr uanctl1 uanctl2 receive shift register uanrx filter selector uantx transmission controller reception controller baud rate generator intuanr intuanre intuant pclk1 (8mhz) pclk2 (4mhz) pclk8 (62.5khz) txdan rxdan reception unit transmission unit transmit shift register baud rate generator selector internal bus clock selector
577 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register used to specify the uartan operation. (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register used to select the input clock for the uartan. (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register used to control the baud rate for the uartan. (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit register used to control serial transfer for the uartan. (5) uartan status register (uanstr) the uanstrn register consists of flags indicating the error contents when a reception error occurs. each one of the reception error flags is set (to 1) upon occurrence of a reception error and is reset (to 0) by reading the uanstr register. (6) uartan receive shift register this is a shift register used to convert the serial data input to the rxdan pin into parallel data. upon reception of 1 byte of data and detection of the stop bit, the receive data is transferred to the uanrx register. this register cannot be manipulated directly. (7) uartan receive data register (uanrx) the uanrx register is an 8-bit register that holds receive data. when 7 characters are received, 0 is stored in the highest bit (when data is received lsb first). in the reception enabled status, receive data is transferred from the uartan receive shift register to the uanrx register in synchronization with the completion of shift-in processing of 1 frame. transfer to the uanrx register also causes the reception complete interrupt request signal (intuanr) to be output. (8) uartan transmit shift register the transmit shift register is a shift register used to convert the parallel data transferred from the uantx register into serial data. when 1 byte of data is transferred from the uantx register, the shift register data is output from the txdan pin. this register cannot be manipulated directly. (9) uartan transmit data register (uantx) the uantx register is an 8-bit transmit data buffer. transmission starts when transmit data is written to the uantx register. when data can be written to the uantx register (when data of one frame is transferred from the uantx register to the uartan transmit shift register), the transmission enable interrupt request signal (intuant) is generated.
578 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 17.3 uarta registers the asynchronous serial interfaces uartan are controlled and operated by means of the following registers: table 17-1 uartan registers overview register name shortcut address uartan control register 0 uanctl0 uartan control register 1 uanctl1 + 1 h uartan control register 2 uanctl2 + 2 h uartan option control register 0 uanopt0 + 3 h uartan status register uanstr + 4 h uartan receive data register uanrx + 6 h uartan transmit data register uantx + 7 h table 17-2 uartan register base address timer base address uarta0 ffff fa00 h uarta1 ffff fa10 h
579 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 (1) uanctl0 - uartan control register 0 the uanctl0 register is an 8-bit register that controls the uartan serial transfer operation. access this register can be read/written in 8-bit or 1-bit units. address initial value 10 h . this register is cleared by any reset. 76543210 uanpwr uantxe uanrxe uandir uanps1 uanps0 uancl uansl r/w r/w r/w r/w r/w r/w r/w r/w table 17-3 uanctl0 register contents (1/2) bit position bit name function 7 uanpwr uartan operation disable/enable: 0: disable uartan operation and reset the uartan asynchronously 1: enable uartan operation the uartan operation is controlled by the uanpwr bit. the txdan pin output is fixed to high level by clearing the uanpwr bit to 0 (fixed to low level if uanopt0.uantdl bit = 1). 6 uantxe transmit operation disable/enable: 0: disable transmit operation 1: enable transmit operation ? to start transmission, set the uanpwr bit to 1 and then set the uantxe bit to 1. ? to stop transmission, clear the uantxe bit to 0 and then the uanpwr bit to 0. ? to initialize the transmission unit, clear uantxe bit to 0, wait for two cycles of the base clock, and then set uantxe bit to 1 again. otherwise, initialization may not be executed. 5 uanrxe receive operation disable/enable: 0: disable receive operation 1: enable receive operation ? to start reception, set the uanpwr bit to 1 and then set the uanrxe bit to 1. ? to stop reception, clear the uanrxe bit to 0 and then the uanpwr bit to 0. ? to initialize the reception unit, clear uanrxe bit to 0, wait for two cycles of the base clock, and then set uanrxe bit to 1 again. otherwise, initialization may not be executed. 4 uandir transfer direction mode specification (msb/lsb): 0: msb first transfer 1: lsb first transfer
580 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 note for details of parity, see ?parity types and operations? on page 597 . (2) uanctl1 - uartan control register 1 the uanctl1 register is an 8-bit register used to select the input clock for the uartan. for details, see ?uanctl1 - uartan control register 1? on page 600 . (3) uanctl2 - uartan control register 2 the uanctl2 register is an 8-bit register used to control the baud rate for the uartan. for details, see ?uanctl2 - uartan control register 2? on page 601 . 3, 2 uanps[1:0] parity selection uanps1 uanps0 parity selection during transmission reception 0 0 no parity output reception with no parity 0 1 0 parity output reception with 0 parity 1 0 odd parity output odd parity check 1 1 even parity output even parity check ? this register is rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. ? if ?reception with 0 parity? is selected during reception, a parity check is not performed. therefore, since the uanstr.uanpe bit is not set, no error interrupt is output. ? when transmission and reception are performed in the lin format, clear the uanps1 and uanps0 bits to 00. 1 uancl specification of data character length of 1 frame of transmit/receive data 0: 7 bits 1: 8 bits this register can be rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. 0 uansl specification of length of stop bit for transmit data 0: 1 bit 1: 2 bits this register can be rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. table 17-3 uanctl0 register contents (2/2) bit position bit name function
581 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 (4) uanopt0 - uartan option control register 0 the uanopt0 register is an 8-bit register that controls the serial transfer operation of the uartan register. access this register can be read/written in 8-bit or 1-bit units. address + 3 h initial value 14 h . this register is cleared by any reset. 76543210 uansrf uansrt uanstt uansbl2 uansbl1 uansbl0 uantdl uanrdl r/w r/w r/w r/w r/w r/w r/w r/w table 17-4 uanopt0 register contents (1/2) bit position bit name function 7 uansrf sbf reception flag: 0: when the uanctl0.uanpwr bit = uanctl0.uanrxe bit = 0 are set. also upon normal end of sbf reception. 1: during sbf reception ? sbf (sync brake field) reception is judged during lin communication. ? the uansrf bit is held at 1 when an sbf reception error occurs, and then sbf reception is started again. 6 uansrt sbf reception trigger: 0: ? 1: sbf reception trigger ? this is the sbf reception trigger bit during lin communication, and when read, ?0? is always read. for sbf reception, set the uansrt bit (to 1) to enable sbf reception. ? set the uansrt bit after setting the uanpwr bit = uanrxe bit = 1. 5 uanstt sbf transmission trigger: 0: ? 1: sbf transmission trigger a ? this is the sbf transmission trigger bit during lin communication, and when read, ?0? is always read. ? set the uanstt bit after setting the uanpwr bit = uantxe bit = 1. 4 to 2 uansbl[2:0] sbf transmission length selection: uansbl2 uansbl1 uansbl0 sbf transmission length 1 0 1 13-bit output (default value) 1 1 0 14-bit output 1 1 1 15-bit output 0 0 0 16-bit output 0 0 1 17-bit output 0 1 0 18-bit output 0 1 1 19-bit output 1 0 0 20-bit output this register can be set when the uanpwr bit = 0 or when the uantxe bit = 0.
582 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 (5) uanstr - uartan status register the uanstr register is an 8-bit register that displays the uartan transfer status and reception error contents. access this register can be read or written in 8-bit or 1-bit units. address + 4 h initial value 00 h . this register is cleared by any reset. the initialization conditions are shown below. 1 uantdl transmit data level bit 0: normal output of transfer data 1: inverted output of transfer data ? the output level of the txdan pin can be inverted using the uantdl bit. ? this register can be set when the uanpwr bit = 0 or when the uantxe bit = 0. 0 uanrdl receive data level bit 0: normal input of transfer data 1: inverted input of transfer data ? the output level of the rxdan pin can be inverted using the uanrdl bit. ? this register can be set when the uanpwr bit = 0 or the uanrxe bit = 0. a) before starting the sbf transmission by uanopt0.uanstt = 1 make sure that no data transfer is ongoing, that means check that uanstr.uantsf = 0. table 17-4 uanopt0 register contents (2/2) bit position bit name function register/bit initialization conditions uanstr register ? reset ? uanctl0.uanpwr = 0 uantsf bit ? uanctl0.uantxe = 0 uanpe, uanfe, uanove bits ? 0 write ? uanctl0.uanrxe = 0 76543210 uantsf 0 0 0 0 uanpe uanfe uanove r r/w r/w r/w r/w r/w a a) these bits can only be cleared by writing, they cannot be set by writing 1 (even if 1 is written, the value is retained). r/w a r/w a
583 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 table 17-5 uanstr register contents bit position bit name function 7 uantsf transfer status flag: 0: ? when the uanpwr bit = 0 or the uantxe bit = 0 has been set. ? when, following transfer completion, there was no next data transfer from uantx register 1: write to uantxb bit the uantsf bit is always 1 when performing continuous transmission. when initializing the transmission unit, check that the uantsf bit = 0 before performing initialization. the transmit data is not guaranteed when initialization is performed while the uantsf bit = 1. 2 uanpe parity error flag: 0: ? when the uanpwr bit = 0 or the uanrxe bit = 0 has been set. ? when 0 has been written 1: when parity of data and parity bit do not match during reception. ? the operation of the uanpe bit is controlled by the settings of the uanctl0.uanps1 and uanctl0.uanps0 bits. ? the uanpe bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained. 1 uanfe framing error flag 0: ? when the uanpwr bit = 0 or the uanrxe bit = 0 has been set ? when 0 has been written 1: when no stop bit is detected during reception ? only the first bit of the receive data stop bits is checked, regardless of the value of the uanctl0.uansl bit. ? the uanfe bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained. 0 uanove overrun error flag 0: ? when the uanpwr bit = 0 or the uanrxe bit = 0 has been set. ? when 0 has been written 1: when receive data has been set to the uanrxb register and the next receive operation is completed before that receive data has been read ? when an overrun error occurs, the data is discarded without the next receive data being written to the receive buffer. ? the uanove bit can be both read and written, but it can only be cleared by writing 0 to it. when 1 is written to this bit, the value is retained.
584 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 (6) uanrx - uartan receive data register the uanrx register is an 8-bit buffer register that stores parallel data converted by the receive shift register. the data stored in the receive shift register is transferred to the uanrx register upon completion of reception of 1 byte of data. during lsb-first reception when the data length has been specified as 7 bits, the receive data is transferred to bits 6 to 0 of the uanrx register and the msb always becomes 0. during msb-first reception, the receive data is transferred to bits 7 to 1 of the uanrx register and the lsb always becomes 0. when an overrun error (uanove) occurs, the receive data at this time is not transferred to the uanrx register and is discarded. access this register can be read only in 8-bit units. address + 6 h initial value ff h . this register is cleared by any reset. in addition to reset input, the uanrx register can be set to ff h by clearing the uanctl0.uanpwr bit to 0. (7) uantx - uartan transmit data register the uantx register is an 8-bit register used to set transmit data. access this register can be read or written in 8-bit units. address + 7 h initial value ff h . this register is cleared by any reset. 76543210 receive data r 76543210 transmit data r/w
585 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 17.4 interrupt request signals the following three interrupt request signals are generated from uartan: ? reception complete interrupt request signal (intuanr) ? receive error interrupt request signal (intuanre) ? transmission enable interrupt request signal (intuant) (1) reception complete interrupt request signal (intuanr) a reception complete interrupt request signal is output when data is shifted into the receive shift register and transferred to the uanrx register in the reception enabled status. in case of erroneous reception, the reception error interrupt intuanre is generated instead of intuanr. no reception complete interrupt request signal is generated in the reception disabled status. (2) receive error interrupt request signal (intuanre) a receive error interrupt request is generated if an error condition occurred during reception, as reflected by uanstr.uanpe (parity error flag), uanstr.uanfe (framing error flag), uanstr.uanove (overrun error flag). note that intuanr and intuanre do exclude each other: upon correct reception of data only intuanr is generated. in case of a reception error intuanre is generated only. (3) transmission enable interrupt request signal (intuant) if transmit data is transferred from the uantx register to the uartan transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated.
586 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 17.5 operation 17.5.1 data format full-duplex serial data reception and transmission is performed. as shown in the figures below, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of msb/lsb-first transfer are performed using the uanctl0 register. moreover, control of uart output/inverted output for the txdan bit is performed using the uanopt0.uantdl bit. ? start bit..........................1 bit ? character bits................7 bits/8 bits ? parity bit ........................even parity/odd parity/0 parity/no parity ? stop bit ..........................1 bit/2 bits (1) uarta transmit/receive data format (a) 8-bit data length, lsb first, even parity, 1 stop bit, transfer data: 55h (b) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h 1 d a t a fr a me s t a rt b it d0 d1 d2 d 3 d4 d5 d6 d7 p a rity b it s top b it 1 d a t a fr a me s t a rt b it d7 d6 d5 d4 d 3 d2 d1 d0 p a rity b it s top b it
587 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 (c) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h, txdan inversion (d) 7-bit data length, lsb first, odd parity, 2 stop bits, transfer data: 36h (e) 8-bit data length, lsb first, no parity, 1 stop bit, transfer data: 87h 1 d a t a fr a me s t a rt b it d7 d6 d5 d4 d 3 d2 d1 d0 p a rity b it s top b it 1 d a t a fr a me s t a rt b it d0 d1 d2 d 3 d4 d5 d6 p a rity b it s top b it s top b it 1 d a t a fr a me s t a rt b it d0 d1 d2 d 3 d4 d5 d6 d7 s top b it
588 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 17.5.2 sbf transmissi on/reception format the uarta has an sbf (sync break field) transmission/reception control function to enable use of the lin function. about lin lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial co mmunication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to control the switches, actuators, and sensors, and these are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method and is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. therefore, communication is possible when the baud rate error in the slave is 15% or less. figure 17-2 and figure 17-3 outline the transmission and reception manipulations of lin. figure 17-2 lin transmission manipulation outline note 1. the interval between each field is controlled by software. 2. sbf output is performed by hardware. the output width is the bit length set by the uanopt0.uansbl2 to uanopt0.uansbl0 bits. if even finer output width adjustments are required, such adjustments can be performed using the uanctln.uanbrs7 to uanctln.uanbrs0 bits. 3. 80h transfer in the 8-bit mode is substituted for the wakeup signal frame. s leep bus w a ke- u p s ign a l fr a me s ynch b re a k field s ynch field ident field data field data field check s um field intuanr interr u pt txdan (o u tp u t) note 3 8 b it s note 1 note 2 1 3 b it s s bf tr a n s mi ss ion note 4 55h tr a n s mi ss ion d a t a tr a n s mi ss ion d a t a tr a n s mi ss ion d a t a tr a n s mi ss ion d a t a tr a n s mi ss ion
589 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 4. a transmission enable interrupt request signal (intuant) is output at the start of each transmission. the intuant signal is also output at the start of each sbf transmission. figure 17-3 lin reception manipulation outline note 1. the wakeup signal is sent by the pin edge detector, uartan is enabled, and the sbf reception mode is set. 2. the receive operation is performed until detection of the stop bit. upon detection of sbf reception of 11 or more bits, normal sbf reception end is judged, and an interrupt signal is output. upon detection of sbf reception of less than 11 bits, an sbf reception error is judged, no interrupt signal is output, and the mode returns to the sbf reception mode. 3. if sbf reception ends normally, an interrupt request signal is output. the timer is enabled by an sbf reception complete interrupt. moreover, error detection for the uanstr.uanove, uanstr.uanpe, and uanstr.uanfe bits is suppressed and uart communication error detection processing and uartan receive shift register and data transfer of the uanrx register are not performed. the uartan receive shift register holds the initial value, ffh. 4. the rxdan pin is connected to ti (capture input) of the timer, the transfer rate is calculated, and the baud rate error is calculated. the value of the uanctl2 register obtained by correcting the baud rate error after dropping uarta enable is set again, causing the status to become the reception status. 5. check-sum field distinctions are made by software. uartan is initialized following csf reception, and the processing for setting the sbf reception mode again is performed by software. reception interr u pt (intuanr) edge detection c a pt u re timer di sab le di sab le en ab le txdan (o u tp u t) en ab le note 2 1 3 b it s s bf reception note 3 note 4 note 1 s f reception id reception d a t a tr a n s mi ss ion d a t a tr a n s mi ss ion note 5 d a t a tr a n s mi ss ion s leep bus w a ke- u p s ign a l fr a me s ynch b re a k field s ynch field ident field data field data field check s um field
590 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 17.5.3 sbf transmission when the uanctl0.uanpwr bit = uanctl0.uantxe bit = 1, the transmission enabled status is entered, and sbf transmission is started by setting (to 1) the sbf transmission trigger (uanopt0.uanstt bit). thereafter, a low level the width of bits 13 to 20 specified by the uanopt0.uansbl2 to uanopt0.uansbl0 bits is output. a transmission enable interrupt request signal (intuant) is generated upon sbf transmission start. following the end of sbf transmission, the uanstt bit is automatically cleared. thereafter, the uart transmission mode is restored. transmission is suspended until the data to be transmitted next is written to the uantx register, or until the sbf transmission trigger (uanstt bit) is set. figure 17-4 sbf transmission 17.5.4 sbf reception the reception enabled status is achieved by setting the uanctl0.uanpwr bit to 1 and then setting the uanctl0.uanrx bit to 1. the sbf reception wait status is set by setting the sbf reception trigger (uanopt0.uanstr bit) to 1. in the sbf reception wait status, similarly to the uart reception wait status, the rxdan pin is monitored and start bit detection is performed. following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate. when a stop bit is received, if the sbf width is 11 or more bits, normal processing is judged and a reception complete interrupt request signal (intuanr) is output. the uanopt0.uansrf bit is automatically cleared and sbf reception ends. error detection for the uanstr.uanove, uanstr.uanpe, and uanstr.uanfe bits is suppressed and uart communication error detection processing is not performed. moreover, data transfer of the uartan reception shift register and uanrx register is not performed and ffh, the initial value, is held. if the sbf width is 10 or fewer bits, reception is terminated as error processing without outputting an interrupt, and the sbf reception mode is returned to. the uansrf bit is not cleared at this time. intuant interr u pt 12 3 4567 8 91011121 3 s top b it s etting of uan s tt b it
591 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 (a) normal sbf reception (detection of stop bit in more than 10.5 bits) (b) sbf reception error (detection of stop bit in 10.5 or fewer bits) uan s rf 12 3 456 11.5 7 8 91011 intuanr interr u pt ua0 s rf 12 3 456 10.5 7 8 910 intuanr interr u pt
592 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 17.5.5 uart transmission a high level is output to the txdan pin by setting the uanctl0.uanpwr bit to 1. next, the transmission enabled status is set by setting the uanctl0.uantxe bit to 1, and transmission is started by writing transmit data to the uantx register. the start bit, parity bit, and stop bit are automatically added. since the cts (transmit enable signal) input pin is not provided in uartan, use a port to check that reception is enabled at the transmit destination. the data in the uantx register is transferred to the uartan transmit shift register upon the start of the transmit operation. a transmission enable interrupt request signal (intuant) is generated upon completion of transmission of the data of the uantx register to the uartan transmit shift register, and thereafter the contents of the uartan transmit shift register are output to the txdan pin. write of the next transmit data to the uantx register is enabled by generating the intuant signal. note lsb first s t a rt b it d0 d1 d2 d 3 d4 d5 d6 d7 p a rity b it s top b it intuant
593 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 17.5.6 continuous transmission procedure uartan can write the next transmit data to the uantx register when the uartan transmit shift register starts the shift operation. the transmit timing of the uartan transmit shift register can be judged from the transmission enable interrupt request signal (intuant). an efficient communication rate is realized by writing the data to be transmitted next to the uantx register during transfer. caution during continuous transmission execution, perform initialization after checking that the uanstr.uantsf bit is 0. the transmit data cannot be guaranteed when initialization is performed while the uantsf bit is 1. figure 17-5 continuous transmission processing flow s t a rt regi s ter s etting s uantx write ye s ye s no no occ u rrence of tr a n s mi ss ion interr u pt? re qu ired n u m b er of write s performed? end
594 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 figure 17-6 continuous transmission op eration timing ?transmission start figure 17-7 continuous transmission operation timing?transmission end s t a rt d a t a (1) d a t a (1) txdan uantx tr a n s mi ss ion s hift regi s ter intuant uant s f d a t a (2) d a t a (2) d a t a (1) d a t a ( 3 ) p a rity s top s t a rt d a t a (2) p a rity s top s t a rt s t a rt d a t a (n ? 1) d a t a (n ? 1) d a t a (n ? 1) d a t a (n) ff d a t a (n) uattxd uantx tr a n s mi ss ion s hift regi s ter intuant uant s f uanpwr or uantxe b it p a rity s top s top s t a rt d a t a (n) p a rity p a rity s top
595 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 17.5.7 uart reception the reception wait status is set by setting the uanctl0.uanpwr bit to 1 and then setting the uanctl0.uanrxe bit to 1. in the reception wait status, the rxdan pin is monitored and start bit detection is performed. start bit detection is performed using a two-step detection routine. first the rising edge of the rxdan pin is detected and sampling is started at the falling edge. the start bit is recognized if the rxdan pin is low level at the start bit sampling point. after a start bit has been recognized, the receive operation starts, and serial data is saved to the uartan receive shift register according to the set baud rate. when the reception complete interrupt request signal (intuanr) is output upon reception of the stop bit, the data of the uartan receive shift register is written to the uanrx register. however, if an overrun error (uanstr.uanove bit) occurs, the receive data at this time is not written to the uanrx register and is discarded. even if a parity error (uanstr.uanpe bit) or a framing error (uanstr.uanfe bit) occurs during reception, reception continues until the reception position of the first stop bit, and intuanr is output following reception completion. figure 17-8 uart reception caution 1. be sure to read the uanrx register even when a reception error occurs. if the uanrx register is not read, an overrun error occurs during reception of the next data, and reception errors continue occurring indefinitely. 2. the operation during reception is performed assuming that there is only one stop bit. a second stop bit is ignored. 3. when reception is completed, read the uanrx register after the reception complete interrupt request signal (intuanr) has been generated, and clear the uanpwr or uanrxe bit to 0. if the uanpwr or uanrxe bit is cleared to 0 before the intuanr signal is generated, the read value of the uanrx register cannot be guaranteed. s t a rt b it d0 d1 d2 d 3 d4 d5 d6 d7 p a rity b it s top b it intuanr uanrx
596 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 4. if receive completion processing (intuanr signal generation) of uartan and the uanpwr bit = 0 or uanrxe bit = 0 conflict, the intuanr signal may be generated in spite of these being no data stored in the uanrx register. to complete reception without waiting intuanr signal generation, be sure to clear (0) the interrupt request flag (uanrif) of the uanric register, after setting (1) the interrupt mask flag (uanrmk) of the interrupt control register (uanric) and then set (1) the uanpwr bit = 0 or uanrxe bit = 0. 17.5.8 reception errors errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. data reception result error flags are set in the uanstr register and a reception error interrupt request signal (intuanre) is output when an error occurs. it is possible to ascertain which error occurred during reception by reading the contents of the uanstr register. clear the reception error flag by writing 0 to it after reading it. table 17-6 reception error causes note note that even in case of a parity or framing error, data is transferred from the receive shift register to the receive data register uanrx. consequently the data from uanrx must be read. otherwise an overrun error uanstr.uanove will occur at reception of the next data. in case of an overrun error, the receive shift register data is not transferred to uanrx, thus the previous data is not overwritten. error flag reception error cause uanpe parity error received parity bit does not match the setting uanfe framing error stop bit not detected uanove overrun error reception of next data completed before data was read from receive buffer
597 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 17.5.9 parity typ es and operations caution when using the lin function, fix the uanps1 and uanps0 bits of the uanctl0 register to 00. the parity bit is used to detect bit errors in the communication data. normally the same parity is used on the transmission side and the reception side. in the case of even parity and odd parity, it is possible to detect odd-count bit errors. in the case of 0 parity and no parity, errors cannot be detected. (1) even parity ? during transmission the number of bits whose value is ?1? among the transmit data, including the parity bit, is controlled so as to be an even number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data:1 ? even number of bits whose value is ?1? among transmit data:0 ? during reception the number of bits whose value is ?1? among the reception data, including the parity bit, is counted, and if it is an odd number, a parity error is output. (2) odd parity ? during transmission opposite to even parity, the number of bits whose value is ?1? among the transmit data, including the parity bit, is controlled so that it is an odd number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 0 ? even number of bits whose value is ?1? among transmit data: 1 ? during reception the number of bits whose value is ?1? among the receive data, including the parity bit, is counted, and if it is an even number, a parity error is output. (3) 0 parity during transmission, the parity bit is always made 0, regardless of the transmit data. during reception, parity bit check is not performed. therefore, no parity error occurs, regardless of whether the parity bit is 0 or 1. (4) no parity no parity bit is added to the transmit data. reception is performed assuming that there is no parity bit. no parity error occurs since there is no parity bit.
598 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 17.5.10 receive data noise filter this filter samples the rxdan pin using the base clock of the prescaler output. when the same sampling value is read twice, the match detector output changes and the rxdan signal is sampled as the input data. therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit (see figure 17-10 ). see ?base clock? on page 599 regarding the base clock. moreover, since the circuit is as shown in figure 17-9 , the processing that goes on within the receive operation is delayed by 3 clocks in relation to the external signal status. figure 17-9 noise filter circuit figure 17-10 timing of rxdan signal judged as noise m a tch detector in b as e clock (f uclk ) rxdan qin ld_en q intern a l s ign a l c intern a l s ign a l b in q intern a l s ign a l a intern a l s ign a l b b as e clock rxdan (inp u t) intern a l s ign a l c mi s m a tch (j u dged as noi s e) intern a l s ign a l a mi s m a tch (j u dged as noi s e) m a tch m a tch
599 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 17.6 baud rate generator the dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with uartan. regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. there is an 8-bit counter for transmission and another one for reception. 17.6.1 baud rate gene rator configuration figure 17-11 configuration of baud rate generator (a) base clock when the uanctl0.uanpwr bit is 1, the clock selected by the uanctl1.uancks[2:0] bits is supplied to the 8-bit counter. this clock is called the base clock. when the uanpwr bit = 0, f uclk is fixed to the low level. (b) serial clock generation a serial clock can be generated by setting the uanctl1 register and the uanctl2 register. the base clock is selected by uanctl1.uancks2 to uanctl1.uancks0 bits. the frequency division value for the 8-bit counter can be set using the uanctl2.uanbrs[7:0] bits. f uclk selector uanpwr 8-bit counter match detector baud rate uanctl2: uanbrs7 to uanbrs0 1/2 uanpwr, uantxen bus (or uanrxe bit) uanctl1: uancks2 to uancks0 pclk7 pclk8 pclk1 pclk2 pclk3 pclk4 pclk5 pclk6
600 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 17.6.2 baud rate generator registers (1) uanctl1 - uartan control register 1 the uanctl1 register is an 8-bit register that selects the uartan base clock. access this register can be read or written in 8-bit units. address + 1 h initial value 00 h . this register is cleared by any reset. caution clear the uanctl0.uanpwr bit to 0 before rewriting the uanctl1 register. 76543210 0 0 0 0 0 uancks2 uancks1 uancks0 rrrrrr/wr/wr/w table 17-7 uanctl1 register contents bit position bit name function 2 to 0 uancks[2:0] base clock f uclk selection: uancks2 uancks1 uancks0 base clock f uclk 000pclk1 001pclk2 010pclk3 011pclk4 100pclk5 101pclk6 110pclk7 111pclk8
601 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 (2) uanctl2 - uartan control register 2 the uanctl2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of uartan. access this register can be read or written in 8-bit units. address + 1 h initial value ff h . this register is cleared by any reset. caution clear the uanctl0.uanpwr bit to 0 or clear the uantxe and uanrxe bits to 00 before rewriting the uanctl2 register. note f uclk : clock frequency selected by uanctl1.uancks[2:0] 76543210 uanbrs7 uanbrs6 uanbrs5 uanbrs4 uanbrs3 uanbrs2 uanbrs1 uanbrs0 rrrrrr/wr/wr/w table 17-8 uanctl2 register contents bit position bit name function 2 to 0 uanbrs[7:0] serial clock setting uan br s7 uan br s6 uan br s5 uan br s4 uan br s3 uan br s2 uan br s1 uan br s0 k serial clock 000000xxxsetting prohibited 000001004f uclk /4 000001015f uclk /5 000001106f uclk /6 :::::::::: 11111100252f uclk /252 11111101253f uclk /253 11111110254f uclk /254 11111111255f uclk /255
602 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 17.6.3 baud rate calculation the baud rate is obtained by the following equation. f uclk = frequency of base clock selected by the uanctl1.uancks[2:0] k = value set using the uanctl2.uanbrs[7:0] bits (k = 4, 5, 6, ?, 255) 17.6.4 baud rate error the baud rate error is obtained by the following equation. caution 1. the baud rate error during transmission must be within the error tolerance on the receiving side. 2. the baud rate error during reception must satisfy the range indicated in (7) allowable baud rate range during reception. example base clock frequency = 8mhz setting value of - uandtl1.uancks[2:0] = 001b (pclk2 = 4mhz) - uanctl2.uanbrs[7:0] = 0000 1101b (k = 13) target baud rate = 153,600 bps baud rate = 4mhz/ (2 13) = 153,846 [bps] error = (153,846/153,600 ? 1) 100 = 0.160 [%] 17.6.5 baud rate setting example baud rate f uclk 2k -------------- - [bps] = error (%) actual baud rate (baud rate with error) target baud rate (correct baud rate) --------------------------------------------------------------------------- - 1 ? () 100 [%] = table 17-9 baud rate generator setting data (1/2) target baud rate uanctl1 uanctl2 effective baud rate [bps] baud rate error (%) [bps] selector divider divider k 300 07h 128 68h 104 300.48 0.16 600 07h 128 34h 52 600.96 0.16 1,200 07h 128 1ah 26 1,201.92 0.16 2,400 07h 128 0dh 13 2,403.85 0.16 4,800 06h 64 0dh 13 4,807.69 0.16 9,600 05h 32 0dh 13 9,615.38 0.16 19,200 04h 16 0dh 13 19,230.77 0.16 31,250 05h 32 04h 4 31,250.00 0.00
603 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 note table 17-9 assumes normal operation mode, i.e. pclk1 = 8 mhz. 17.6.6 allowable baud rate range during reception the baud rate error range at the destination that is allowable during reception is shown below. caution the baud rate error during reception must be set within the allowable error range using the following equation. figure 17-12 allowable baud rate range during reception as shown in figure 17-12 , the receive data latch timing is determined by the counter set using the uanctl2 register following start bit detection. the transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. when this is applied to 11-bit reception, the following is the theoretical result. fl = (brate) - 1 brate: uartan baud rate k: setting value of uanctl2.uanbrs[7:0] 38,400 03h 8 0dh 13 38,461.54 0.16 76,800 02h 4 0dh 13 76,923.08 0.16 153,600 01h 2 0dh 13 153,846.15 0.16 312,500 00h 1 0dh 13 307,692.31 ?1.54 table 17-9 baud rate generator setting data (2/2) fl 1 d a t a fr a me (11 fl) flmin flm a x uartn tr a n s fer r a te s t a rt b it bit 0 bit 1 bit 7 p a rity b it minim u m a llow ab le tr a n s fer r a te m a xim u m a llow ab le tr a n s fer r a te s top b it s t a rt b it bit 0 bit 1 bit 7 p a rity b it l a tch timing s top b it s t a rt b it bit 0 bit 1 bit 7 p a rity b it s top b it
604 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 fl: 1-bit data length latch timing margin: 2 clocks minimum allowable transfer rate: therefore, the maximum baud rate that can be received by the destination is as follows. similarly, obtaining the following maximum allowable transfer rate yields the following. therefore, the minimum baud rate that can be received by the destination is as follows. obtaining the allowable baud rate error for uartan and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. table 17-10 maximum/minimum allowable baud rate error note 1. the reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division ratio (k). the higher the input clock frequency and the larger the division ratio (k), the higher the accuracy. 2. k: setting value of uanctl2.uanbrs[7:0] fl min 11 fl k2 ? 2k ----------- - fl ? 21k 2 + 2k ------------------- fl == brmax flmin 11 ? () 1 ? 22k 21k 2 + ------------------- brate == 10 11 ------ flmax 11 fl k2 + 2k ------------ fl ? 21k 2 ? 2k ------------------ - fl == flmax 21k 2 ? 20k ------------------ - fl 11 = brmin flmax 11 ? () 1 ? 20k 21k 2 ? ------------------ - brate == division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 4+2.32% - 2.43% 8+3.52% - 3.61% 20 +4.26% - 4.30% 50 +4.56% - 4.58% 100 +4.66% - 4.67% 255 +4.72% - 4.72%
605 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 17.6.7 baud rate during continuous transmission during continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. however, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result. figure 17-13 transfer rate during continuous transfer assuming 1 bit data length: fl; stop bit length: flstp; and base clock frequency: f uclk , we obtain the following equation. flstp = fl + 2/f uclk therefore, the transfer rate during continuous transmission is as follows. transfer rate = 11 fl + (2/f uclk ) s t a rt b it bit 0 bit 1 bit 7 p a rity b it s top b it fl 1 d a t a fr a me fl fl fl fl fl fl fl s tp s t a rt b it of 2nd b yte s t a rt b it bit 0
606 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00 17.7 cautions 17.7.1 uartan behaviour duri ng and after power save mode when the clock supply to uartan is stopped (for example, in idle or stop mode), the operation stops with each register retaining the value it had immediately before the clock supply was stopped. the txdan pin output also holds and outputs the value it had immediately before the clock supply was stopped. however, the operation is not guaranteed after the clock supply is resumed. therefore, after the clock supply is resumed, the circuits should be initialized by setting the uanctl0.uanpwr, uanctl0.uanrxen, and uanctl0.uantxen bits to 000. 17.7.2 uartan behaviour during debugger break the uartan continues to operate in debugger break-mode, provided all clocks are continuing. reception when the uartan is in reception mode and an external device is sending data during debugger break-mode the uartan may produce an overflow error as it continues to receive data during break-mode. thus the overflow error flag uanstr.uanove may be set and the reception error interrupt intuanre may be generated. further all following received data are discarded. note that the reception error interrupt intuanre will not be served during break-mode, but after resuming run-mode, provided the interrupt controller is configured accordingly. transmission if the debugger?s break-mode is entered while the uartan is transmitting data, the transmission is completed, and finally a transmission enable interrupt request intuant is generated. note that the transmission enable interrupt intuant will not be served during break-mode, but after resuming run-mode, provided the interrupt controller is configured accordingly. dma reception if the dma controller is used to fetch received data from the uanrx register, the dma controller continues to do so in debugger break-mode, but the data in uanrx is not tagged as already read. thus the next receive data during break- mode will generate an overflow error, as described above. if the specified number of data units in the dbcn register has been fetched from the uartan the dchcn.tcn is set and the dma completion interrupt intdman is generated. the intdman request is served after resuming run- mode. since the dma trigger interrupt intuanr is not generated in case of an overflow (the intuanre interrupt is generated instead), no further dma triggers occur. only the first received data in break-mode is transferred by the dma, all following data are discarded.
607 asynchronous serial interface (uarta) chapter 17 user?s manual u17566ee5v1um00 dma transmission if the dma controller is used to write transmission data to the uantx register, the dma controller continues to do so in debugger break-mode. if the specified number of data units in the dbcn register has been transferred to the uartan the dchcn.tcn is set and the dma completion interrupt intdman is generated. the intdman request is served after resuming run-mode. 17.7.3 uartan operation stop if both of the following actions in uartan happen at the same time the intuanr signal may be generated inadvertently and no data is stored in the uanrx register: ? intuanr is generated due to completion of a serial receive operation, ? uanpwr bit or uanrxe bit is cleared (set to 0). workaround to avoid the generation of the intuanr signal when uanpwr bit or uanrxe bit is cleared (set to 0) do the following: 1. set (set to 1) the interrupt mask flag (uanrmk) of the interrupt control register (uanric), 2. clear (set to 0) the uanpwr bit or uanrxe bit, 3. clear (set to 0) the interrupt request flag (uanrif) of the uanric register.
608 chapter 17 asynchronous serial interface (uarta) user?s manual u17566ee5v1um00
609 user?s manual u17566ee5v1um00 chapter 18 clocked serial interface (csib) the v850e/dx3 microcontrollers have following instances of the clocked serial interface csib: throughout this chapter, the individual instances of clocked serial interface are identified by ?n?, for example csibn, or cbnctl0 for the control register 0 of csibn. 18.1 features ? transfer rate: 8 mbps to 2 kbps (using dedicated baud rate generator) the maximum transfer rate is the maximum transfer rate of the digital circuitry. it does neither regard any output buffer driver strength limitation nor the external capacitive load. both might reduce the practically achievable maximum baud rate. ? master mode and slave mode selectable ? 8-bit to 16-bit transfer, 3-wire serial interface ? 3 interrupt request signals (intcbnt, intcbnr, intcbnre) ? serial clock and data phase switchable ? transfer data length selectable in 1-bit units between 8 and 16 bits ? transfer data msb-first/lsb-first switchable ? 3-wire transfer sobn: serial data output sibn: serial data input sckbn: serial clock input/output transmission mode, reception mode, and transmission/reception mode specifiable ? dma support ? dedicated baud rate generator for each interface instance ? modulated and stable clock sources available csib pd70f3427, pd70f3426a, pd70f3425, pd70f3424 pd70f3423, pd70f3422, pd70f3421 instances 3 2 names csib0 to csib2 csib0 to csib1
610 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 18.2 configuration the following shows the block diagram of csibn. figure 18-1 block diagram of csibn note the clock is generated by the dedicated baud rate generator brgn. internal bus cbnctl2 cbnctl0 cbnstr controller intcbnr intcbnre sobn intcbnt cbntx so latch phase control shift register cbnrx cbnctl1 phase control sibn pclk1 (8 mhz) brgn pclk2 (4 mhz) pclk3 (2 mhz) pclk4 (1 mhz) pclk5 (500 khz) sckbn r o t c e l e s pclk6 (250 khz) spclk1 (8 mhz) note
611 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 18.3 csib control registers the clocked serial interfaces csibn are controlled and operated by means of the following registers: table 18-1 csibn registers overview register name shortcut address csibn control register 0 cbnctl0 csibn control register 1 cbnctl1 + 1 h csibn control register 2 cbnctl2 + 2 h csibn status register cbnstr + 3 h csibn receive data register cbnrx + 4 h csibn transmit data register cbntx + 6 h table 18-2 csibn register base address timer base address csib0 ffff fd00 h csib1 ffff fd10 h csib2 ffff fd20 h
612 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 (1) cbnctl0 - csibn control register 0 cbnctl0 is a register that controls the csibn serial transfer operation. access this register can be read/written in 8-bit or 1-bit units. address initial value 01 h . this register is cleared by any reset. 76543210 cbnpwr cbntxe a a) these bits can only be rewritten when the cbnpwr bit = 0. however, cbnpwr bit = 1 can also be set at the same time as rewriting these bits. cbnrxe a cbndir a 00cbntms a cbnsce r/w r/w r/w r/w r/w r/w r/w r/w table 18-3 cbnctl0 register contents (1/2) bit position bit name function 7 cbnpwr csibn operation disable/enable: 0: disable csibn operation and reset the csibn registers 1: enable csibn operation the cbnpwr bit controls the csibn operation and resets the internal circuit. 6 cbntxe transmit operation disable/enable: 0: disable transmit operation 1: enable transmit operation the sobn output is low level when the cbntxe bit is 0. 5 cbnrxe receive operation disable/enable: 0: disable receive operation 1: enable receive operation when the cbnrxe bit is cleared to 0, no reception complete interrupt is output even when the prescribed data is transferred in order to disable the receive operation, and the receive data (cbnrx register) is not updated.
613 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 4 cbndir transfer direction mode specification (msb/lsb): 0: msb first transfer 1: lsb first transfer 1 cbntms transfer mode specification (msb/lsb): 0: single transfer mode 1: continuous transfer mode 0 cbnsce specification of start transfer disable/enable: 0: communication start trigger invalid 1: communication start trigger valid ? in master mode this bit enables or disables the communication start trigger. (a)in single transmission or transmission/reception mode, or continuous transmission or continuous transmission/reception mode a communication operation can be started only when the cbnsce bit is 1. set the cbnsce bit to 1. (b)in single reception mode clear the cbnsce bit to 0 before reading the receive data (cbnrx register). if the cbnsce bit is read while it is 1, the next communication operation is started. (c)in continuous reception mode clear the cbnsce bit to 0 one communication clock before reception of the last data is completed the cbnsce bit is not cleared to 0 one communication clock before the completion of the last data reception, the next communication operation is automatically started. ? in slave mode this bit enables or disables the communication start trigger. set the cbnsce bit to 1. table 18-3 cbnctl0 register contents (2/2) bit position bit name function
614 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 (2) cbnctl1 - csibn control register 1 cbnctl1 is an 8-bit register that controls the csibn serial transfer operation. access this register can be read/written in 8-bit or 1-bit units. address + 1 h initial value 00 h . this register is cleared by any reset. caution the cbnctl1 register can be rewritten only when the cbnctl0.cbnpwr bit = 0. 76543210 0 0 0 cbnckp cbndap cbncks2 cbncks1 cbncks0 r/w r/w r/w r/w r/w r/w r/w r/w table 18-4 cbnctl1 register contents bit position bit name function 4 3 cbnckp cbndap specification of data transmission/reception timing in relation to sckbn. refer to table 18-5 . 2 to 0 cbncks[2:0] communication clock setting cbnck s2 cbnck s1 cbnck s0 communication clock mode 000f brgn master 001f pclk1 master 010f pclk2 master 011f pclk3 master 100f pclk4 master 101f pclk5 master 110f pclk6 master 1 1 1 external clock sckbn slave
615 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 table 18-5 specification of data transmission/reception timing in relation to sckbn communication type cbnckp cbndap sibn/sobn timing in relation to sckbn communication type 1 0 0 communication type 2 0 1 communication type 3 1 0 communication type 4 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture (output)
616 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 (3) cbnctl2 - csibn control register 2 cbnctl2 is an 8-bit register that controls the number of csibn serial transfer bits. access this register can be read/written in 8-bit units. address + 2 h initial value 00 h . this register is cleared by any reset. caution the cbnctl2 register can be rewritten only when the cbnctl0.cbnpwr bit = 0 or when both the cbntxe and cbnrxe bits = 0. note if the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the lsb of the cbntx and cbnrx registers. 76543210 0 0 0 0 cbncl3 cbncl2 cbncl1 cbncl0 r/w r/w r/w r/w r/w r/w r/w r/w table 18-6 cbnctl2 register contents bit position bit name function 3 to 0 cbncl[3:0] number of serial transfer bits cbncl3 cbncl2 cbncl1 cbncl0 number of serial transfer bits 00008 bits 00019 bits 001010 bits 001111 bits 010012 bits 010113 bits 011014 bits 011115 bits 1xxx16 bits
617 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 (a) transfer data length change function the csibn transfer data length can be set in 1-bit units between 8 and 16 bits using the cbnctl2.cbncl3 to cbnctl2.cbncl0 bits. when the transfer bit length is set to a value other than 16 bits, set the data to the cbntx or cbnrx register starting from the lsb, regardless of whether the transfer start bit is the msb or lsb. any data can be set for the higher bits that are not used, but the receive data becomes 0 following serial transfer. figure 18-2 (i) transfer bit length = 10 bits, msb first figure 18-3 (ii) transfer bit length = 12 bits, lsb first 15 10 9 0 s obn s ibn in s ertion of 0 0 s obn 11 12 15 s ibn in s ertion of 0
618 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 (4) cbnstr - csibn status register cbnstr is an 8-bit register that displays the csibn status. access this register can be read/written in 8-bit or 1-bit units. bit cbntsf is read-only. address + 3 h initial value 00 h . this register is cleared by any reset. in addition to reset input, the cbnstr register can be initialized by clearing the cbnctl0.cbnpwr bit to 0. note in case of an overrun error, the reception error interrupt intcbnre behaves different, depending on the transfer mode: ? continuous transfer mode the reception error interrupt intcbnre is generated instead of the reception completion interrupt intcbnr. ? single transfer mode no interrupt is generated. in either case the overflow flag cbnstr.cbnove is set to 1 and the previous data in cbnrx will be overwritten with the new data. 76543210 cbntsf000000cbnove r r/w r/w r/w r/w r/w r/w r/w table 18-7 cbnstr register contents bit position bit name function 7 cbntsf communication status flag 0: communication stopped 1: communicating during transmission, this register is set when data is prepared in the cbntx register, and during reception, it is set when a dummy read of the cbnrx register is performed. when transfer ends, this flag is cleared to 0 at the last edge of the clock. 0 cbnove overrun error flag 0: no overrrun 1: overrun ? an overrun error occurs when the next reception starts without performing a cpu read of the value of the receive buffer, upon completion of the receive operation. the cbnove flag displays the overrun error occurrence status in this case. ? the cbnove flag is cleared by writing 0 to it. it cannot be set even by writing 1 to it.
619 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 (5) cbnrx - csibn receive data register the cbnrx register is a 16-bit buffer register that holds receive data. access this register can be read-only in 16-bit units. if the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the cbnrxl register. address + 4 h initial value 0000 h . this register is cleared by any reset. in addition to reset input, the cbnrx register can be initialized by clearing (to 0) the cbnpwr bit of the cbnctl0 register. the receive operation is started by reading the cbnrx register in the reception enabled status. (6) cbntx - csib transmit data register the cbntx register is a 16-bit buffer register used to write the csibn transfer data. access this register can be read/written in 16-bit units. if the transfer data length is 8 bits, the lower 8 bits of this register are read/write in 8-bit units as the cbntxl register. address + 6 h initial value 0000 h . this register is cleared by any reset. in addition to reset input, the cbntx register can be initialized by clearing (to 0) the cbnpwr bit of the cbnctl0 register. the transmit operation is started by writing data to the cbntx register in the transmission enabled status. note the communication start conditions are shown below: ? transmission mode (cbntxe bit = 1, cbnrxe bit = 0): write to cbntx register ? transmission/reception mode (cbntxe bit = 1, cbnrxe bit = 1): write to cbntx register ? reception mode (cbntxe bit = 0, cbnrxe bit = 1): read from cbnrx register 1514131211109876543210 receive data r 1514131211109876543210 transmit data r/w
620 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 18.4 operation 18.4.1 single transfer mode (mas ter mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (see 16.4 (2) csibn control register 1 (cbnctl1), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbntxe, cbnrxe, and cbnsce bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the transmission/reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) write transfer data to the cbntx register (transmission start). (6) the reception complete interrupt request signal (intcbnr) is output. (7) read the cbnrx register before clearing the cbnpwr bit to 0. (8) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop operation of csibn (end of transmission/reception). to continue transfer, repeat steps (5) to (7) before (8). in transmission mode or transmission/reception mode, communication is not started by reading the cbnrx register. cbntx write (55h) cbnrx read (aah) (aah) (55h) 1 0 1 1 0 1 abh 56h adh 5ah b5h 6ah d5h aah 55h (transmit data) sckbn cbntx aah 00h 00h cbnrx shift register intcbnr note sibn sobn 0 0 0 1 0 0 1 0 1 1 cbntsf cbnsce (1) (5) (6) (8) (7) (2) (3) (4)
621 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 note 1. in single transmission or single transmission/reception mode, the intcbnt signal is not generated. when communication is complete, the intcbnr signal is generated. 2. the processing of steps (3) and (4) can be set simultaneously. caution in case the csib interface is operating in ? single transmit/reception mode (cbnctl0.cbntms = 0) ? communication type 2 respectively type 4 (cbnctl1.cbndap = 1) pay attention to following effect: in case the next transmit should be initiated immediately after the occurrence of the reception completion interrupt intcbnr any write to the cbntx register is ignored as long as the communication status flag is still reflecting an ongoing communication (cbntsf = 1). thus the new transmission will not be started. for transmitting data continuously use one of the following options: ? use continuous transfer mode (cbnctl0.cbntms = 1). this is the only usable mode for automatic transmission of data by the dma controller. ? if single transfer mode (cbnctl0.cbntms = 0) should be used, cbnstr.cbntsf = 0 needs to be verified before writing data to the cbntx register.
622 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 18.4.2 single transfer mode (master mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (see 16.4 (2) csibn control register 1 (cbnctl1), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe and cbnctl0.cbnsce bits to 1, cbnctl0.txe to 0, at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. (7) set the cbnsce bit to 0 to set the final receive data status. (8) read the cbnrx register. (9) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the csibn operation (end of reception). to continue transfer, repeat steps (5) and (6) before (7). (at this time, (5) is not a dummy read, but a receive data read combined with the reception trigger.) note the processing of steps (3) and (4) can be set simultaneously. (aah) 1 0 1 1 00 1 abh 56h adh 5ah b5h 6ah d5h aah 55h (receive data) sckbn cbnrx cbnrx read (55h) shift register cbnsce cbntsf intcbnr sibn sobn 0 l (1) (2) (3) (4) (5) (6) (7) (9) (8) cbnrx read (aah) aah 00h 00h
623 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 18.4.3 continuous mode (master mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 3 (see 16.4 (2) csibn control register 1 (cbnctl1)), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbntxe, cbnrxe, and cbnsce bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the transmission/reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) write transfer data to the cbntx register (transmission start). (6) the transmission enable interrupt request signal (intcbnt) is received and transfer data is written to the cbntx register. (7) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. (8) (7) (7) (6) (5) (1) (2) (3) (4) 96h 00h cch 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 55h cbntx sckbn sobn sibn intcbnt intcbnr cbntsf cbnsce shift register so latch cbnrx 0 0 0 0 aah 96h cch 1 1 1 0 0 0 00h 1 01 0 0
624 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 (8) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the operation of csibn (end of transmission/reception). to continue transfer, repeat steps (5) to (7) before (8). in transmission mode or transmission/reception mode, the communication is not started by reading the cbnrx register. 18.4.4 continuous mode (mast er mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 2 (see 16.4 (2) csibn control register 1 (cbnctl1)), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe bit to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. (7) set the cbnctl0.cbnsce bit = 0 while the last data being received to set the final receive data status. ( 8 ) (6) (6) (7) (5) (1) (2) ( 3 ) (4) 1 0 0 0 0 0 0 01 1 1 1 1 55h s ckbn cbn s ce s ibn intcnr cbn t s f s hift regi s ter cbn rx 1 1 0 55h aah aah 00h 00h s obn l
625 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 (8) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the operation of csibn (end of reception). to continue transfer, repeat steps (5) and (6) before (7). 18.4.5 continuous re ception mode (error) msb first (cbnctl0.cbndir bit = 0), communication type 2 (see 16.4 (2) csibn control register 1 (cbnctl1)), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe bit to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit = 1 to enable csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. (7) if the data could not be read before the end of the next transfer, the cbnstr.cbnove flag is set to 1 upon the end of reception and the reception error interrupt intcbnre is output. (8) overrun error processing is performed after checking that the cbnove bit = 1 in the intcbnre interrupt servicing. (9) clear cbnove bit to 0. (10)check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the operation csibn (end of reception). ( 8 ) (9) (10) (7) (6) (5) aah 00h 00h 1 0 0 0 0 0 01 1 1 1 1 s ckbn s ibn intcbnr cbnove 55h 55h 0 1 0 aah 1 (1) (2) ( 3 ) (4) s obn l intcbnre cbnt s f s hift regi s ter cbnrx
626 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 18.4.6 continuous mode (slave mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 2 (see 16.4 (2) csibn control register 1 (cbnctl1)), transfer data length = 8 bits (cbnctl2.csncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbntxe, cbnrxe and cbnsce bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the transmission/reception enabled status. (4) set the cbnpwr bit to 1 to enable supply of the csibn operation. (5) write the transfer data to the cbntx register. (6) the transmission enable interrupt request signal (intcbnt) is received and the transfer data is written to the cbntx register. (7) the reception complete interrupt request signal (intcbnr) is output. (8) (7) (7) (6) (5) 96h 00h cch 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 55h cbntx sckbn sobn sibn intcbnt intcbnr shift register so latch cbnrx 0 0 0 0 0 0 aah 96h cch 1 0 0 0 1 1 cbntsf cbnsce 00h (1) (2) (3) (4)
627 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 read the cbnrx register. (8) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the operation of csibn (end of transmission/reception). to continue transfer, repeat steps (5) to (7) before (8). note in order to start the entire data transfer the cbntx register has to be written initially, as done in step (5) above. if this step is omitted also no data will be received. discontinued transmission in case the csib is operating in continuous slave transmission mode (cbnctl0.cbntms = 1, cbnctl1.cbncks[2:0] = 111 b ) and new data is not written to the cbntx register the sobn pin outputs the level of the last bit. table 18-4 outlines this behaviour. figure 18-4 discontinued slave transmission the example shows the situation that two data bytes (55 h , aa h ) are transmitted correctly, but the third (96 h ) fails. (1) data 55 h is written (by the cpu or dma) to cbntx. (2) the master issues the clock sckbn and transmission of 55 h starts. (3) intcbnt is generated and the next data aa h is written to cbntx promptly, i.e. before the first data has been transmitted completely. (4) transmission of the second data aa h continues correctly and intcbnt is generated. but this time the next data is not written to cbntx in time. (5) since there is no new data available in cbntx, but the master continuous to apply sckbn clocks, sobn remains at the level of the transmitted last bit. (6) new data (96 h ) is written to cbntx. (7) with the next sckbn cycle transmission of the new data (96 h ) starts. as a consequence the master receives a corrupted data byte from (5) onwards, which is made up of a random number of the repeated last bit of the former data and some first bits of the new data. 0 s ckbn s obn intcbnt cbntx cbnt s f 1010 01 1 1 0 10 10 10 55h aah 1001011 0 96h (1) (2) (4) (5) (6) (7) (3)
628 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 18.4.7 continuous mode (sla ve mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (see 16.4 (2) csibn control register 1 (cbnctl1)), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe and cbnctl0.cbnsce bits to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit = 1 to enable csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register. (7) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the operation of csibn (end of reception). to continue transfer, repeat steps (5) and (6) before (7). (7) (6) (6) (5) 1 0 0 0 0 0 0 01 1 1 1 1 55h sckbn sibn intcbnr cbntsf cbnsce shift register cbnrx 1 1 55h aah 00h 00h aah 0 (1) (2) (3) (4)
629 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 18.4.8 clock timing figure 18-5 (i) communication type 1 (cbnckp = 0, cbndap = 0) figure 18-6 (ii) communication type 3 (cbnckp = 1, cbndap = 0) d6 d5 d4 d3 d2 d1 sckbn sibn capture reg-r/w sobn intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 sckbn sibn capture reg-r/w sobn intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf
630 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 figure 18-7 (iii) communication type 2 (cbnckp = 0, cbndap = 1) figure 18-8 (iv) communication type 4 (cbnckp = 1, cbndap = 1) note 1. the intcbnt interrupt is set when the data written to the transmit buffer is transferred to the data shift register in the continuous transmission or continuous transmission/reception modes. in the single transmission or single transmission/reception modes, the intcbnt interrupt request signal is not generated, but the intcbnr interrupt request signal is generated upon completion of communication. 2. the intcbnr interrupt occurs if reception is correctly completed and receive data is ready in the cbnrx register while reception is enabled, and if an overrun error occurs. in the single mode, the intcbnr interrupt request signal is generated even in the transmission mode, upon completion of communication. d6 d5 d4 d3 d2 d1 d0 d7 sckbn sibn capture reg-r/w sobn intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf d6 d5 d4 d3 d2 d1 d0 d7 sckbn sibn capture reg-r/w sobn intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf
631 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 18.5 output pins (1) sckbn pin when csibn operation is disabled (cbnctl0.cbnpwr bit = 0), the sckbn pin output status is as follows. note the output level of the sckbn pin changes if any of the cbnctl1.cbnckp and cbncks2 to cbncks0 bits is rewritten. (2) sobn pin when csibn operation is disabled (cbnpwr bit = 0), the sobn pin output status is as follows. note 1. the sobn pin output changes when any one of the cbnctl0.cbntxe, cbnctl0.cbndir bits, and cbnctl1.cbndap bit is rewritten. 2. : don?t care cbnckp cbncks2 cbncks1 cbncks0 sckbn pin output 0 don?t care don?t care don?t care fixed to high level 1111high impedance other than above fixed to low level cbntxe cbndap cbndir sobn pin output 0 fixed to low level 1 0 sobn latch value (low level) 10cbntxn value (msb) 1 cbntxn value (lsb)
632 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 18.6 operation flow (1) single transmission note set the cbnsce bit to 1 in the initial setting. caution in the slave mode, data cannot be correctly transmitted if the next transfer clock is input earlier than the cbntx register is written. s ta rt no ye s intcbnr gener a ted? tr a n s fer d a t a exi s t s ? end ye s no initi a l s etting (cbnctl0 note , cbnctl1 regi s ter s , etc.) write cbntx regi s ter ( s t a rt tr a n s fer). cbnpwr b it = 0 (cbnctl0)
633 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 (2) single reception note set the cbnsce bit to 1 in the initial setting. caution in the single mode, data cannot be correctly received if the next transfer clock is input earlier than the cbnrx register is read. s ta rt no intcbnr gener a ted? l as t d a t a ? end ye s ye s no initi a l s etting (cbnctl0 note , cbnctl1 regi s ter s , etc.) cbnrx regi s ter d u mmy re a d ( s t a rt reception) cbn s ce b it = 0 (cbnctl0) cbnpwr b it = 0 (cbnctl0) cbnrx regi s ter re a d cbnrx regi s ter re a d
634 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 (3) single transmission/reception note 1. set the cbnsce bit to 1 in the initial setting. 2. if the next transfer is reception only, dummy data is written to the cbntx register. caution even in the single mode, the cbnstr.cbnove flag is set to 1. if only transmission is used in the transmission/reception mode, therefore, programming without checking the cbnove flag is recommended. s ta rt initi a l s etting (cbnctl0 note 1 , cbnctl1 regi s ter s , etc.) write cbntx regi s ter ( s t a rt tr a n s fer). end cbnpwr b it = 0, cbntxe b it = cbnrxe b it = 0 (cbnctl0) no tr a n s mi ss ion/reception tr a n s mi ss ion reception intcbnr gener a ted? ye s tr a n s fer end? write cbntx regi s ter note 2 . re a d cbnrx regi s ter. re a d cbnrx regi s ter. no ye s tr a n s fer end? write cbntx regi s ter note 2 . no ye s tr a n s fer end? write cbntx regi s ter note 2 . no ye s b b a a
635 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 (4) continuous transmission note set the cbnsce bit to 1 in the initial setting. s ta rt no ye s intcbnt gener a ted? exi s t s d a t a to b e tr a n s ferred next? end ye s no initi a l s etting (cbnctl0 note , cbnctl1 regi s ter s , etc.) write cbntx regi s ter ( s t a rt tr a n s fer). cbnpwr b it = 0 (cbnctl0) no cbnt s f b it = 0? (cbn s tr) ye s
636 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 (5) continuous reception note set the cbnsce bit to 1 in the initial setting. caution in the master mode, the clock is output without limit when dummy data is read from the cbnrx register. to stop the clock, execute the flow marked ? ? s ta rt end no ye s intcbnr gener a ted? intcbnre gener a ted? no ye s initi a l s etting (cbnctl0 note , cbnctl1 regi s ter s , etc.) cbnrx regi s ter d u mmy re a d ( s t a rt reception) cbnrx regi s ter re a d cbnrx regi s ter re a d cbnrx regi s ter re a d cbnrx regi s ter re a d ye s i s d a t a b eing received l as t d a t a ? cbn s ce b it = 0 (cbnctl0) no intcbnr gener a ted? ye s cbnove b it cle a r (cbn s tr) no cbn s ce b it = 0 (cbnctl0)
637 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 (6) continuous transmission/reception note set the cbnsce bit to 1 in the initial setting. s ta rt end no no intcbnr gener a ted? ye s no intcbnt gener a ted? ye s initi a l s etting (cbnctl0 note , cbnctl1 regi s ter s , etc.) write cbntx regi s ter. cbnrx regi s ter re a d ye s ye s d a t a received completely? no write cbntx regi s ter. ye s l as t d a t a tr a n s ferred? no intcbnre gener a ted? cbnove b it cle a r (cbn s tr) cbnrx regi s ter re a d
638 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 18.7 baud rate generator 18.7.1 overview each csibn interface is equipped with a dedicated baud rate generator. 18.7.2 baud rate generator registers the baud rate generators brgn are controlled and operated by means of the following registers: bgncs1, bgncs0 prscmn match detector 1/2 brgnout 8-bit timer counter selector (1, 1/2, 1/4, 1/8) spclk1 table 18-8 brgn registers overview register name shortcut address brgn prescaler mode register prsmn brgn prescaler compare register prscmn + 1 h table 18-9 brgn register base address timer base address brg0 ffff fdc0 h brg1 ffff fde0 h brg2 ffff fdf0 h
639 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 (1) prsmn - prescaler mode registers the prsmn registers control generation of the baud rate signal for csib. access this register can be read/written in 8-bit or 1-bit units. address initial value 00 h . this register is cleared by any reset. caution 1. do not rewrite the prsmn register during operation. 2. set the bgcsn[1:0] bits before setting the bgcen bit to 1. (2) prscmn - prescaler compare registers the prscmn registers are 8-bit compare registers. access this register can be read/written in 8-bit units. address + 1 h initial value 00 h . this register is cleared by any reset. caution 1. do not rewrite the prscmn register during operation. 2. set the prscmn register before setting the prsmn.bgcen bit to 1. 76543210 0 0 0 bgcen 0 0 bgcsn1 bgcsn0 r/w r/w r/w r/w r/w r/w r/w r/w table 18-10 prsmn register contents bit position bit name function 4 bgcen baud rate output 0: disabled 1: enabled 1 to 0 bgcsn[1:0] input clock selection bgcsn1 bgcsn0 input clock selection (f bgcsn ) setting value k 00f spclk1 0 01f spclk1 /2 1 10f spclk1 /4 2 11f spclk1 /8 3 76543210 prscmn7 prscmn6 prscmn5 prscmn4 prscmn3 prscmn2 prscmn1 prscmn0 r/w
640 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 18.7.3 baud rate calculation the transmission/reception clock is generated by dividing the main clock. the baud rate generated from the main clock is obtained by the following equation. note f brgn : brgn count clock f spclk1 : main clock oscillation frequency k: prsmn.bgcsn[1:0] register setting value (0  k  3) n: prscmn.prscmn[7:0] register value if prscmn = 00h: n = 256. f brgn f spclk1 2 k n 2 --------------------------- - =
641 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 18.8 cautions 18.8.1 csibn behaviour during debugger break the csibn continues to operate in debugger break-mode, provided all clocks are continuing. the csibn continuous to operate during debugger break-mode ? in continuous reception/transmission mode ? in slave reception/transmission mode reception when the csibn is in reception mode and an external device is sending data during debugger break-mode the csibn may produce an overflow error as it continues to receive data during break-mode. thus the overflow error flag ucbnstr.cbnove may be set and the reception error interrupt intcbnre may be generated. further all following received data are discarded. note that the reception error interrupt intcbnre will not be served during break-mode, but after resuming run-mode, provided the interrupt controller is configured accordingly. transmission if the debugger?s break-mode is entered while the csibn is transmitting data, the transmission is completed, and finally a transmission enable interrupt request intcbnt is generated. note that the transmission enable interrupt intcnnt will not be served during break-mode, but after resuming run-mode, provided the interrupt controller is configured accordingly. dma reception if the dma controller is used to fetch received data from the cbnrx register, the dma controller continues to do so in debugger break-mode, but the data in cbnrx is not tagged as already read. thus the next receive data during break-mode will generate an overflow error, as described above. if the specified number of data units in the dbcn register has been fetched from the csibn the dchcn.tcn is set and the dma completion interrupt intdman is generated. the intdman request is served after resuming run- mode. since the dma trigger interrupt intcbnr is not generated in case of an overflow (the intcbnre interrupt is generated instead), no further dma triggers occur. only the first received data in break-mode is transferred by the dma, all following data are discarded. dma transmission if the dma controller is used to write transmission data to the cbntx register, the dma controller continues to do so in debugger break-mode. if the specified number of data units in the dbcn register has been transferred to the csibn the dchcn.tcn is set and the dma completion interrupt intdman is generated. the intdman request is served after resuming run-mode.
642 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00 18.8.2 csib operation stop (1) details - master mode operation when any channel of csib is operated with a peripheral clock source different to the clock source of the cpu, the csib may stop operating. depending on the csib operating configuration the csib behaves as described below. ? transmit mode or transmit/receive mode: any write to the related cbntx0 register will no longer start a transmission sequence. furthermore the related transmission interrupt request will not be generated. ? receive mode: any read from the related cbnrx0 register will no longer start a receive sequence. furthermore the related receive interrupt request will not be generated. the described csibn stuck condition can be escaped by initiating a system reset or by a sequential clear and set of the cbnctl0.cbnpwr bit. (2) details - slave mode operation when any channel of csib is operated in slave mode and an external clock signal is input via the sckbn pin while no transmission or reception sequence is in progress the csib may stop operating. depending on the csib operating configuration the csib behaves as described below. ? transmit mode or transmit/receive mode any further write to the cbntx0 register followed by an external input clock signal input will no longer start a transmission sequence. furthermore the related transmission interrupt request will not be generated. ? receive mode: any read from the related cbnrx0 register followed by an external input clock signal input will no longer start a receive sequence. furthermore the related receive interrupt request will not be generated. the described csibn stuck condition can be escaped by initiating a system reset or by a sequential clear and set of the cbnctl0.cbnpwr bit. (3) workaround - master mode operation in order to avoid the csibn stuck condition in master mode use only the following cpu clock to csibn input clock combinations: cpu clock source scc. spsel0 ckc. peric brgn clock source (spclk1) csib clock input 4 mhz main osc 0 0 4 mhz main osc pclk6 .. 1, brgn 0 1 4 mhz main osc pclk6 .. 2, brgn 1 0 pll pclk6 .. 1 1 1 pll pclk6 .. 2 pll 1 0 pll brgn 1 1 pclk1, brgn sscg 1 x pll brgn
643 clocked serial interface (csib) chapter 18 user?s manual u17566ee5v1um00 (4) workaround - slave mode operation in order to avoid the csibn stuck condition in slave mode take the following precautions. ? transmit mode or transmit/receive mode: make sure the external csibn clock is not input in parallel when writing to the cbntx0 register after a transmission sequence is finished. ? receive mode: make sure the external csibn clock is not input in parallel when reading from the cbnrx0 register after a reception sequence is finished.
644 chapter 18 clocked serial interface (csib) user?s manual u17566ee5v1um00
645 user?s manual u17566ee5v1um00 chapter 19 i 2 c bus (iic) the v850e/dx3 microcontrollers have following instances of the i 2 c bus interface iic: throughout this chapter, the individual instances of i 2 c bus interface are identified by ?n?, for example iicn, or iiccn for the iicn control register. 19.1 features the i2c provides a synchronous serial interface with the following features: ? supports master and slave mode ? 8-bit data transfer ? transfer speed ? up to 100 kbit/s (standard mode) ? up to 381kbit/s (fast mode) ?i 2 c root clock sources from main oscillator, pll and sscg ? two wire interface ? scln: serial clock ? sdan: serial data ? noise filter on scln and sdan input ? spikes with a width of less than one period of iiclk are suppressed ? iicn interrupts can be used for triggering the dma controller iic all devices instances 2 names iic0 to iic1
646 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.2 i 2 c pin configuration the i 2 c function requires to define the pins scl0 and sda0 as input and open drain output pins simultaneously. in the following the pin configuration registers are listed to be set up properly for i 2 c: ? pfsr0.pfsr04 = 1/0: select input for i 2 c0 ? plcdc6.plcdc64/65 = 0: no lcd output (if applicable) ? pmcn.pmcnm = 1: alternative mode ? input type: ? piccn.piccnm = 0: non-schmitt trigger input for standard mode ? piccn.piccnm = 1: schmitt trigger input for fast-speed mode ? pilcn.pilcnm = 0: cmos1 level ? pdscn.pdscnm = 1: drive strength control limit2 ? podcn.podcnm = 1: open drain output ? pmn.pmnm = 1: input mode it is recommended to set the output mode as the last step. table 19-2 shows how to set up the registers for activating i 2 c0 from different pin groups. table 19-1 i 2 c interface pins set up i 2 cn pfsr0 register pins and pin group register settings i 2 c0 pfsr0.pfsr04 = 0 sda0/scl0 via p16/p17 pmc1.pmc1[7:6] = 11 b picc1.picc1[7:6] = 00 b /11 b a pilc1.pilc1[7:6] = 00 b pdsc1.pdsc1[7:6] = 11 b podc1.podc1[7:6] = 11 b pm1.pm1[7:6] = 11 b a) piccnm = 00 b for standard mode, piccnm = 11 b for fast-speed mode pfsr0.pfsr04 = 1 scl0/sda0 via p64/p65 plcdc6.plcdc6[5:4] = 00 b pmc6.pmc6[5:4] = 11 b picc6.picc6[5:4] = 00 b /11 b a pilc6.pilc6[5:4] = 00 b pdsc6.pdsc6[5:4] = 11 b podc6.podc6[5:4] = 11 b pm6.pm6[5:4] = 11 b
647 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 19.3 i 2 c pin configuration the i 2 c function requires to define the pins scln and sdan as input and open drain output pins simultaneously. in the following the pin configuration registers are listed to be set up properly for i 2 c: ? pfsr0.pfsr04/5 = 1/0: select input for i 2 cn (where applicable) ? plcdcn.plcdcnm = 0: no lcd output (where applicable) ? pfcn.pfcnm = 1/0: select alt1-/alt2-out (where applicable) ? pmcn.pmcnm = 1: alternative mode ? input type: ? piccn.piccnm = 0: non-schmitt trigger input for standard mode ? piccn.piccnm = 1: schmitt trigger input for fast-speed mode ? pilcn.pilcnm = 0: cmos1 level ? pdscn.pdscnm = 1: drive strength control limit2 ? podcn.podcnm = 1: open drain output ? pmn.pmnm = 1: input mode it is recommended to set the output mode in the last step. table 19-2 shows how to set up the registers for activating i 2 c0 and i 2 c1 from different pin groups.
648 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 table 19-2 i 2 c interface pins set up i 2 cn pfsr0 register pins and pin group register settings i 2 c0 pfsr0.pfsr04 = 0 sda0/scl0 via p16/p17 pmc1.pmc1[7:6] = 11 b picc1.picc1[7:6] = 00 b /11 b a pilc1.pilc1[7:6] = 00 b pdsc1.pdsc1[7:6] = 11 b podc1.podc1[7:6] = 11 b pm1.pm1[7:6] = 11 b a) piccnm = 00 b for standard mode, piccnm = 11 b for fast-speed mode pfsr0.pfsr04 = 1 scl0/sda0 via p64/p65 plcdc6.plcdc6[5:4] = 00 b pfc6.pfc6[5:4] = 00 b pmc6.pmc65 = 1 b picc6.picc6[5:4] = 00 b /11 b a pilc6.pilc6[5:4] = 00 b pdsc6.pdsc6[5:4] = 11 b podc6.podc6[5:4] = 11 b pm6.pm6[5:4] = 11 b i 2 c1 pfsr0.pfsr05 = 0 sda1/scl1 via p20/p21 plcdc2.plcdc2[1:0] = 00 b pmc2.pmc2[1:0] = 11 b picc2.picc2[1:0] = 00 b /11 b a pilc2.pilc2[1:0] = 00 b pdsc2.pdsc2[1:0] = 11 b podc2.podc2[1:0] = 11 b pm2.pm2[1:0] = 11 b pfsr0.pfsr05 = 1 sda1/scl1 via p30/p31 pfc3.pfc30 = 1 b pmc3.pmc3[1:0] = 11 b picc3.picc3[1:0] = 00 b /11 b a pilc3.pilc3[1:0] = 00 b pdsc3.pdsc3[1:0] = 11 b podc3.podc3[1:0] = 11 b pm3.pm3[1:0] = 11 b
649 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 19.4 i 2 c pin configuration the i 2 c function requires to define the pins scln and sdan as input and open drain output pins simultaneously. in the following the pin configuration registers are listed to be set up properly for i 2 c: ? pfsr0.pfsr04/5 = 1/0: select input for i 2 cn (where applicable) ? plcdcn.plcdcnm = 0: no lcd output (where applicable) ? pfcn.pfcnm = 1/0: select alt1-/alt2-out (where applicable) ? pmcn.pmcnm = 1: alternative mode ? input type: ? piccn.piccnm = 0: non-schmitt trigger input for standard mode ? piccn.piccnm = 1: schmitt trigger input for fast-speed mode ? pilcn.pilcnm = 0: cmos1 level ? pdscn.pdscnm = 1: drive strength control limit2 ? podcn.podcnm = 1: open drain output ? pmn.pmnm = 1: input mode it is recommended to set the output mode as the last step. table 19-2 shows how to set up the registers for activating i 2 c0 and i 2 c1 from different pin groups.
650 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 table 19-3 i 2 c interface pins set up i 2 cn pfsr0 register pins and pin group register settings i 2 c0 pfsr0.pfsr04 = 0 sda0/scl0 via p16/p17 pmc1.pmc1[7:6] = 11 b picc1.picc1[7:6] = 00 b /11 b a pilc1.pilc1[7:6] = 00 b pdsc1.pdsc1[7:6] = 11 b podc1.podc1[7:6] = 11 b pm1.pm1[7:6] = 11 b a) piccnm = 00 b for standard mode, piccnm = 11 b for fast-speed mode pfsr0.pfsr04 = 1 scl0/sda0 via p64/p65 plcdc6.plcdc6[5:4] = 00 b pfc6.pfc6[5:4] = 00 b pmc6.pmc6[5:4] = 11 b picc6.picc6[5:4] = 00 b /11 b a pilc6.pilc6[5:4] = 00 b pdsc6.pdsc6[5:4] = 11 b podc6.podc6[5:4] = 11 b pm6.pm6[5:4] = 11 b i 2 c1 pfsr0.pfsr05 = 0 sda1/scl1 via p20/p21 plcdc2.plcdc2[1:0] = 00 b pfc2.pfc2[1:0] = 00 b pmc2.pmc2[1:0] = 11 b picc2.picc2[1:0] = 00 b /11 b a pilc2.pilc2[1:0] = 00 b pdsc2.pdsc2[1:0] = 11 b podc2.podc2[1:0] = 11 b pm2.pm2[1:0] = 11 b pfsr0.pfsr05 = 1 sda1/scl1 via p30/p31 pfc3.pfc30 = 1 b pmc3.pmc3[1:0] = 11 b picc3.picc3[1:0] = 00 b /11 b a pilc3.pilc3[1:0] = 00 b pdsc3.pdsc3[1:0] = 11 b podc3.podc3[1:0] = 11 b pm3.pm3[1:0] = 11 b
651 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 19.5 configuration the block diagram of the i 2 c0n is shown below. figure 19-1 block diagram of i 2 c0n iicen dq cln1, cln0 sdan scln iiclk intiicn lreln wreln spien wtimn acken sttn sptn mstsn aldn excn coin trcn ackdn stdn spdn stcfn iicbsyn stcenn iicrsvn cldn dadn smcn dfcn cln1 cln0 clxn prescaler internal bus internal bus iic control register n (iiccn) iic status register n (iicsn) set clear slave address register n (svan) noise eliminator match signal iic shift register n (iicn) so latch star t condition generator data hold time correction circuit acknowledge output circuit wake-up controller n-ch open-drain output acknowledge detector star t condition detector stop condition detector serial clock counter interrupt request signal generator noise eliminator serial clock controller serial clock wait controller bus status detector iic clock select register n (iiccln) iic function expansion register n (iicxn) iic flag register n (iicfn) n-ch open-drain output ocksn0 iic division clock select register m (ocksn) ocksn1 ocksthn ocksenn prescaler iiclkps = iiclk to iiclk/5 iiclktc note note note: schmitt trigger input buffer for fast-speed mode, non schmitt trigger for standard mode ( ) ( )
652 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 a serial bus configuration example is shown below. figure 19-2 serial bus configuration example using i 2 c bus i 2 c0n includes the following hardware. (1) iic shift register n (iicn) the iicn register converts 8-bit serial data into 8-bit parallel data and vice versa, and can be used for both transmission and reception. write and read operations to the iicn register are used to control the actual transmit and receive operations. (2) slave address register n (svan) the svan register sets local addresses when in slave mode. (3) so latch the so latch is used to retain the output level of the sdan pin. (4) wakeup controller this circuit generates an interrupt request when the address received by this register matches the address value set to the svan register or when an extension code is received. s da s cl s da +v dd +v dd s cl s da s cl s l a ve cpu 3 addre ss 3 s da s cl s l a ve ic addre ss 4 s da s cl s l a ve ic addre ss n m as ter cpu1 s l a ve cpu1 addre ss 1 s eri a l d a t a bus s eri a l clock m as ter cpu2 s l a ve cpu2 addre ss 2
653 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiicn). an i 2 c interrupt is generated following either of two triggers: ? falling edge of eighth or ninth clock of the serial clock (set by iiccn.wtimn bit) ? interrupt occurrence due to stop condition detection (set by iiccn.spien bit) (8) serial clock controller in master mode, this circuit generates the clock output via the scln pin from the sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack output circuit, stop condition detector, start condition detector, and ack detector these circuits are used to output and detect various control signals. (11) data hold time correction circuit this circuit generates the hold time for data corresponding to the falling edge of the scln pin. (12) start condition generator a start condition is issued when the iiccn.sttn bit is set. however, in the communication reservation disabled status (iicfn.iicrsvn = 1), this request is ignored and the iicfn.stcfn bit is set if the bus is not released (iicfn.iicbsyn = 1). (13) bus status detector whether the bus is released or not is ascertained by detecting a start condition and stop condition. however, the bus status cannot be detected immediately after operation, so set the bus status detector to the initial status by using the iicfn.stcenn bit.
654 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.6 iic registers the i 2 c serial interfaces iicn are controlled and operated by means of the following registers: note iicn control register the iiccn registers enable/stop i2c operations, set the wait timing and other i2c operations. these registers can be read or written in 8-bit or 1-bit units. however, set the spien, wtimn, and acken bits when the iicn.iicen bit is 0 or during the wait period. when setting the iicn.iicen bit from ?0? to ?1?, these bits can also be set at the same time. table 19-4 iicn registers overview register name shortcut address iicn shift register iicn iicn control register iiccn + 2 h iicn slave address register svan + 3 h iicn clock select register iiccln + 4 h iicn function expansion register iicxn + 5 h iicn status register iicsn + 6 h iicn flag register iicf0n + a h iicn division clock select registers ocksn + 20 h table 19-5 iicn register base address iicn base address iic0 ffff fd80 h iic1 ffff fd90 h
655 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 (1) iiccn - iicn control registers the iiccn registers enable/stop i 2 cn operations, set the wait timing, and set other i 2 cn operations. access this register can be read/written in 8-bit or 1-bit units. address + 2 h initial value 00 h . this register is cleared by any reset. note the iics register, iicfn.stcfn and iicfn.iicbsyn bits, and iiccln.cldn and iiccln.dadn bits are reset. 76543210 iicen lreln wreln spien wtimn acken sttn sptn r/w r/w r/w r/w r/w r/w r/w r/w iicen specification of i 2 cn operation enable/disable 0 operation stopped. iicsn register reset note . internal operation stopped. 1 operation enabled. condition for clearing (iicen = 0) condition for setting (iicen = 1) ? cleared by instruction ? after reset ? set by instruction lreln exit from communications 0 normal operation 1 this exits from the current communication operation and sets stand-by mode. this setting is automatically cleared after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scln and sdan lines are set to high impedance. the sttn and sptn bits and the mstsn, excn, coin, trcn, ackdn, and stdn bits of the iicsn register are cleared. the stand-by mode following exit from communications remains in effect until the following communication entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match occurs or an extension code is received after the start condition. condition for clearing (lreln = 0) condition for setting (lreln = 1) ? automatically cleared after execution ? after reset ? set by instruction wreln wait cancellation control 0 wait not cancelled 1 wait cancelled. this setting is automatically cleared after wait is cancelled. condition for clearing (wreln = 0) condition for setting (wreln = 1) ? automatically cleared after execution ? after reset ? set by instruction
656 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 spien enable/disable generation of interrupt request when stop condition is detected 0 disabled 1 enabled condition for clearing (spien = 0) condition for setting (spien = 1) ? cleared by instruction ? after reset ? set by instruction wtimn control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, clock output is set to low level and wait is set. slave mode: after input of eight clocks, the clock is set to low level and wait is set for the master device. in order to generate the ninth clock on scln the wait status must be cancelled by writing to iicn or setting iiccn.wreln = 1. consequently the ninth clock will be delayed until the wait status is cancelled. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clocks, the clock is set to low level and wait is set for the master device. during address transfer, an interrupt occurs at the falling edge of the ninth clock regardless of this bit setting. this bit setting becomes valid when the address transfer is completed. in master mode, a wait is inserted at the falling edge of the ninth clock during address transfer. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ack signal is issued. when the slave device has received an extension code, however, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtimn = 0) condition for setting (wtimn = 1) ? cleared by instruction ? after reset ? set by instruction acken acknowledgement control 0 acknowledgment disabled. 1 acknowledgment enabled. during the ninth clock period, the sdan line is set to low level. however, ack is invalid in other than extension mode during address transfers. condition for clearing (acken = 0) condition for setting (acken = 1) ? cleared by instruction ? after reset ? set by instruction
657 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 note the sttn bit is 0 if it is read immediately after data setting. sttn start condition trigger 0 start condition is not generated. 1 when bus is released (in stop mode): a start condition is generated (for starting as master). the sdan line is changed from high level to low level and then the start condition is generated. next, after the rated amount of time has elapsed, the scln line is changed to low level. during communication with a third party: if the communication reservation function is enabled (iicfn.iicrsvn = 0) ? this trigger functions as a start condition reserve flag. when set, it releases the bus and then automatically generates a start condition. if the communication reservation function is disabled (iicrsvn = 1) ? the iicfn.stcfn bit is set. this trigger does not generate a start condition. in the wait state (when master device): a restart condition is generated after the wait is released. cautions concerning set timing for master reception: cannot be set during transfer. can be set only when the acken bit has been set to 0 and the slave has been notified of final reception. for master transmission: a start condition cannot be generated normally during the ack period. set during the wait period. for slave: even when the communication reservation function is disabled (iicrsvn bit = 1), the communication reservation status is entered. condition for clearing (sttn = 0) note condition for setting (sttn = 1) ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? when the lreln = 1 (communication save) ? when the iicen= 0 (operation stop) ? after reset ? set by instruction
658 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 note 1. set the sptn bit only in master mode. however, when communication reservation is enabled (iicfn.iicrsvn = 0), the sptn bit must be set and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. for details, see ?cautions? on page 705 . 2. clearing the iicen bit to 0 invalidates the signals of this flag. 3. the sptn bit is 0 if it is read immediately after data setting. caution when the trcn = 1, the wreln bit is set during the ninth clock and wait is canceled, after which the trcn bit is cleared and the sdan line is set to high impedance. sptn stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (termination of master device?s transfer). after the sdan line goes to low level, either set the scln line to high level or wait until it goes to high level. next, after the rated amount of time has elapsed, the sdan line is changed from low level to high level and a stop condition is generated. cautions concerning set timing for master reception: cannot be set during transfer. can be set only when the acken bit has been set to 0 and during the wait period after the slave has been notified of final reception. for master transmission: a stop condition cannot be generated normally during the ack period. set during the wait period. ? sptn cannot be set at the same time as the sttn bit. ? the sptn bit can be set only when in master mode note 1 . ? when the wtimn bit has been set to 0 and the sptn bit is set during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. when the ninth clock must be output to apply the ack on the bus by the receiving device, proceed as follows: - change iiccn.wtimn from 0 to 1 in order to receive an additional interrupt after the ninth clock. - cancel the wait state by iiccn.wreln = 1 or by writing to the iicn register. - upon the interrupt after the ninth clock require to set the stop condition by iiccn.stpn = 1. by this the wait status will be cancelled and the stop condition will be generated on the bus. condition for clearing (sptn = 0) note 2 condition for setting (sptn = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when the lreln = 1 (communication save) ? when the iicen = 0 (operation stop) ? after reset ? set by instruction
659 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 (2) iicsn - iicn status registers the iicsn registers indicate the status of the i 2 cn bus. access this register can only be read in 8-bit or 1-bit units. address + 6 h initial value 00 h . this register is cleared by any reset. note any bit manipulation instruction targetting this register also clears this bit. 76543210 mstsn aldn excn coin trcn ackdn stdn spdn rrrrrrrr mstsn master device status 0 slave device status or communication stand-by status 1 master device communication status condition for clearing (mstsn = 0) condition for setting (mstsn = 1) ? when a stop condition is detected ? when the aldn = 1 (arbitration loss) ? cleared by lreln = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when a start condition is generated aldn arbitration loss detection 0 this status means either that there was no arbitration or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. the mstsn bit is cleared. condition for clearing (aldn = 0) condition for setting (aldn = 1) ? automatically cleared after the iicsn register is read note ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when the arbitration result is a ?loss?. excn detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (excn = 0) condition for setting (excn = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when the higher four bits of the received address data are either ?0000? or ?1111? (set at the rising edge of the eighth clock).
660 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 note the trcn bit is cleared and sdan line becomes high impedance when the wreln bit is set and the wait state is canceled at the ninth clock by trcn = 1. coin matching address detection 0 addresses do not match. 1 addresses match. condition for clearing (coin = 0) condition for setting (coin = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to (operation stop) ? after reset ? when the received address matches the local address (svan register) (set at the rising edge of the eighth clock). trcn transmit/receive status detection 0 receive status (other than transmit status). the sdan line is set to high impedance. 1 transmit status. the value in the so latch is enabled for output to the sdan line (valid starting at the falling edge of the first byte?s ninth clock). condition for clearing (trcn = 0) condition for setting (trcn = 1) ? when a stop condition is detected ? cleared by lreln = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? cleared by wreln = 1 note ? when the aldn bit changes from 0 to 1 (arbitration loss) ? after reset master ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated slave ? when ?1? is input by the first byte?s lsb (transfer direction specification bit) ackdn ack detection 0 ack was not detected. 1 ack was detected. condition for clearing (ackdn = 0) condition for setting (ackd = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by lreln = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? after the sdan bit is set to low level at the rising edge of the scln pin?s ninth clock
661 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 stdn start condition detection 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (stdn = 0) condition for setting (stdn = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by lreln = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when a start condition is detected spdn stop condition detection 0 stop condition was not detected. 1 stop condition was detected. the master device?s communication is terminated and the bus is released. condition for clearing (spdn = 0) condition for setting (spdn = 1) ? at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when a stop condition is detected
662 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 (3) iicfn - iicn flag registers the registers set the i 2 cn operation mode and indicate the i 2 c bus status. access this register can be read/written in 8-bit or 1-bit units. stcfn and iicbsyn bits are read-only. address + a h initial value 00 h . this register is cleared by any reset. iicrsvn enables/disables the communication reservation function. the initial value of the iicbsyn bit is set by using the stcenn bit (see ?cautions? on page 705 ). the iicrsvn and stcenn bits can be written only when operation of i 2 cn is disabled (iiccn.iicen = 0). after operation is enabled, iicfn can be read. 76543210 stcfn iicbsyn 0000stcenniicrsvn r r r/w r/w r/w r/w r/w r/w stcfn sttn clear 0 start condition issued 1 start condition cannot be issued, sttn bit cleared condition for clearing (stcfn = 0) condition for setting (stcfn = 1) ? cleared by iiccn.sttn = 1 ? after reset ? when start condition is not issued and sttn flag is cleared during communication reservation is disabled (iicrsvn = 1). iicbsyn i 2 cn bus status 0 bus released status 1 bus communication status condition for clearing (iicbsyn = 0) condition for setting (iicbsyn = 1) ? when stop condition is detected ? after reset ? when start condition is detected ? by setting the iiccn.iicen bit when the stcenn = 0 stcenn initial start enable trigger 0 start conditions cannot be generated until a stop condition is detected following operation enable (iicen bit = 1). 1 start conditions can be generated even if a stop condition is not detected following operation enable (iicen = 1). condition for clearing (stcenn = 0) condition for setting (stcenn = 1) ? when start condition is detected ? after reset ? setting by instruction
663 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 note bits 6 and 7 are read-only bits. caution 1. write the stcenn bit only when operation is stopped (iicen = 0). 2. when the stcenn = 1, the bus released status (iicbsyn = 0) is recognized regardless of the actual bus status immediately after the i 2 cn bus operation is enabled. therefore, to issue the first start condition (sttn = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. 3. write the iicrsvn bit only when operation is stopped (iicen = 0). iicrsvn communication reservation function disable bit 0 communication reservation enabled 1 communication reservation disabled condition for clearing (iicrsvn = 0) condition for setting (iicrsvn = 1) ? clearing by instruction ? after reset ? setting by instruction
664 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 (4) iiccln - iicn clock select registers the iiccln registers set the transfer clock for the i 2 cn bus. the smcn, cln1, and cln0 bits are set by the combination of the iicxn.clxn bit and the ocksthn, ocksn[1:0] bits of the ocksn register (see ?transfer rate setting? on page 666 ). access this register can be read/written in 8-bit or 1-bit units. cldn and dadn bits are read-only. address + 4 h initial value 00 h . this register is cleared by any reset. 76543210 0 0 cldn dadn smcn dfcn cln1 cln0 r/w r/w r r r/w r/w r/w r/w cldn detection of scln pin level (valid only when iiccn.iicen = 1) 0 the scln pin was detected at low level. 1 the scln pin was detected at high level. condition for clearing (cldn = 0) condition for setting (cldn = 1) ? when the scln pin is at low level ? when the iicen = 0 (operation stop) ? after reset ? when the scln pin is at high level dadn detection of sdan pin level (valid only when iicen = 1) 0 the sdan pin was detected at low level. 1 the sdan pin was detected at high level. condition for clearing (dadn = 0) condition for setting (dad0n = 1) ? when the sdan pin is at low level ? when the iicen = 0 (operation stop) ? after reset ? when the sdan pin is at high level smcn operation mode switching 0 operation in standard mode. 1 operation in fast-speed mode. dfcn digital filter operation control 0 digital filter off. 1 digital filter on. the digital filter can be used only in fast-speed mode. in fast-speed mode, the transfer clock does not vary regardless of the dfcn bit setting (on/off). the digital filter is used to eliminate noise in fast-speed mode.
665 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 (5) iicxn - iicn function expansion registers the iicxn registers provide additional transfer data rate configuration in fast- speed mode. setting of the iicxn.clxn is performed in combination with the iiccln.smcn, iiccln.cln[1:0], ocksn.ocksthn and ocksn.ocksn[1:0] (refer to ?transfer rate setting? on page 666 ) access this register can be read/written in 8-bit or 1-bit units. address + 5 h initial value 00 h . this register is cleared by any reset. (6) ocksn - iicn division clock select registers the ocksn registers control the i 2 cn division clock. access this register can be read/written in 8-bit or 1-bit units. address + 20 h initial value 00 h . this register is cleared by any reset. 76543210 0000000clxn r/w r/w r/w r/w r/w r/w r/w r/w 76543210 0 0 0 ocksenn ocksthn 0 ocksn1 ocksn0 r/w r/w r/w r/w r/w r/w r/w r/w ocksenn operation setting of i 2 c clock 0 disable i 2 c division clock operation 1 enable i 2 c division clock operation ocksthn ocksn1 ocksn0 output clock iiclkps 000iiclk/2 001iiclk/3 010iiclk/4 011iiclk/5 100iiclk other than above setting prohibited
666 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 (7) transfer rate setting the nominal transfer rate of the i 2 c interface is determined by the following means: ? the root clock source for the i 2 c clock iiclk can be chosen as ? main oscillator (4 mhz): icc.iicsel1 = 0 ? 32 mhz clock from the pll: icc.iicsel1 = 1 ? a prescaler in the clock generator divides the chosen clock source by ? 1.0: icc.iicps[2:0]=000 b ? 3.5: icc.iicps[2:0]=101 b ? 4.5: icc.iicps[2:0]=111 b the output clock iiclk supplies the iic interface. ? the iiclk can be divided by 1 to 5, configured by ocksn.ocksthn and ocksn.ocksn[1:0] (refer to ?ocksn - iicn division clock select registers? on page 665 ). the output clock of this divider is named iiclkps. ? iiclk respectively iiclkps is passed through another configurable divider that finally outputs the clock for the serial transfer iiclktc. this divider is configured by iiccln.cl[1:0] and iicxn.clx0 according to the following table: note the clock chosen as the input clock, that means iiclk or iiclkps, must lie in the range of 1 mhz to 10 mhz. iicxn.clxn iiccln.smcn iiccln.cln1 iiccln.cln0 input clock transfer clock mode 0000f iiclkps f iiclkps /44 standard 01f iiclkps f iiclkps /86 standard 10f iiclk f iiclk /86. standard 11f iiclkps f iiclkps /66 standard 100f iiclkps f iiclkps /24 fast-speed 01f iiclkps f iiclkps /24 fast-speed 10f iiclk f iiclk /24 fast-speed 11f iiclkps f iiclkps /18 fast-speed 1 0 x x n.a. n.a. n.a. 100f iiclkps f iiclkps /12 fast-speed 01f iiclkps f iiclkps /12 fast-speed 10f iiclk f iiclk /12 fast-speed
667 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 following table lists set-ups for some useful i 2 c transfer clocks. note the calculations in the above table assumes that iiclk is 32 mhz (iic.iicsel1 = 1) clock stretching heavy capacitive load and the dimension of the external pull-up resistor on the i 2 c bus pins may yield extended rise times of the rising edge of scln and sdan. since the controller senses the level of the i 2 c bus signals it recognizes such situation and takes countermeasures by stretching the clock scln in order to ensure proper high level time t sclh of scln. after the microcontroller releases the (open-drain) scln pin it waits until the scln level exceeds the valid high level threshold v thh . then it does not pull scln to low level before the nominal high level time t sclh_nom has elapsed. this mechanism is the same used, when a slow i 2 c slave device is pulling down scln to low level to initiate a wait state. figure 19-3 shows an example. figure 19-3 clock stretching of scln the effective clock frequency appearing at the scln pin calculates to f scl_eff = 1 / (t scl_nom + t r ) with a nominal frequency of f scl_nom = 395 khz (t scl_nom = 2.532 s and a rise time of t r = 135 ns the effective frequency is f eff =375khz. clock generator prescaler i 2 c module set-up transfer clock [khz] iicps [2:0] divisor ocksn divisor iiccln. smcn iicxn. clxn iiccln. cln[1:0] divisor 101 b 3.5 1 0000 b = 10 h 21 1 00 b 12 380,95 101 b 3.5 1 0010 b = 12 h 41 0 00 b 24 95,24 111 b 4.5 1 0010 b = 12 h 41 0 11 b 18 98,77 t r t sclh t scll t r t scl_nom t scl_eff scl signal effective scl clock v thh
668 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 (8) iicn - iicn shift registers the iicn registers are used for serial transmission/reception (shift operations) synchronized with the serial clock. a wait state is released by writing the iicn register during the wait period, and data transfer is started. access this register can be read/written in 8-bit units. data should not be written to the iicn register during a data transfer. address initial value 00 h . this register is cleared by any reset. (9) svan - iicn slave address registers the svan registers hold the i 2 c bus?s slave addresses. access this register can be read/written in 8-bit units. bit 0 should be fixed to 0. address + 3 h initial value 00 h . this register is cleared by any reset. 76543210 input/output data r/w 76543210 slave address r/w
669 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 19.7 i 2 c bus pin functions the serial clock pin (scln) and serial data bus pin (sdan) are configured as follows. ?scln this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt trigger input for fast-speed mode respectively non schmitt trigger for standard mode. ?sdan this pin is used for serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt trigger input for fast-speed mode respectively non schmitt trigger for standard mode. since outputs from the serial clock line and the serial data bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 19-4 pin configuration diagram 19.8 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. the transfer timing for the ?start portv dd s cln s dan ( ) note note s cln s dan portv dd clock o u tp u t m as ter device (clock inp u t) d a t a o u tp u t d a t a inp u t (clock o u tp u t) clock inp u t d a t a o u tp u t d a t a inp u t s l a ve device ( ) note note ( ) ( ) note: schmitt trigger input buffer for fast-speed mode, non schmitt trigger for standard mode
670 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 condition?, ?data?, and ?stop condition? output via the i 2 c bus?s serial data bus is shown below. figure 19-5 i 2 c bus serial data transfer timing with stop termination instead of a stop condition the master may also send a repeated start condition, when it wishes to keep hold of the bus and to start a new data transfer. figure 19-6 i 2 c bus serial data transfer timing with restart the master device outputs the start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scln) is continuously output by the master device. however, in the slave device, the scln pin?s low-level period can be extended and a wait can be inserted. 19.8.1 start condition a start condition is met when the scln pin is high level and the sdan pin changes from high level to low level. the start condition for the scln and sdan pins is a signal that the master device outputs to the slave device when starting a serial transfer. the slave device can detect the start condition. 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 s cln s dan s t a rt condition addre ss r/w ack d a t a d a t as top condition ack ack repe a ted s t a rt condition 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 s cln s dan s t a rt condition addre ss r/w ack d a t a d a t a ack ack
671 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 figure 19-7 start condition a start condition is output when the iiccn.sttn bit is set (1) after a stop condition has been detected (iicsn.spdn bit = 1). when a start condition is detected, the iicsn.stdn bit is set (1). by setting iiccn.sttn=1 the master device will also cancel its own wait status. 19.8.2 addresses the 7 bits of data that follow the start condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in the svan register. if the address data matches the values of the svan register, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition. figure 19-8 address note the interrupt request signal (intiicn) is generated if a local address or extension code is received during slave device operation. the slave address and the eighth bit, which specifies the transfer direction as described in ?transfer direction specification? on page 672 , are written together to iic shift register n (iicn) and then output. received addresses are written to the iicn register. the slave address is assigned to the higher 7 bits of the iicn register. h s cln s dan addre ss s cln 1 s dan intiicn note 2 3 4567 8 9 ad6 ad5 ad4 ad 3 ad2 ad1 ad0 r/w
672 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.8.3 transfer direction specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. when this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. figure 19-9 transfer direction specification note the intiicn signal is generated if a local address or extension code is received during slave device operation. 19.8.4 acknowledge signal (ack ) the acknowledge signal (ack ) is used by the transmitting and receiving devices to confirm serial data reception. the receiving device returns one ack signal for each 8 bits of data it receives. the transmitting device normally receives an ack signal after transmitting 8 bits of data. however, when the master device is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. the transmitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as normal and processing continues. if the slave device does not return an ack signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. failure to return an ack signal may be caused by the following two factors. (a) reception was not performed normally. (b) the final data was received. when the receiving device sets the sdan line to low level during the ninth clock, the ack signal becomes active (normal receive response). when the iiccn.acken bit is set to 1, automatic ack signal generation is enabled. transmission of the eighth bit following the 7 address data bits causes the iicsn.trcn bit to be set. when this trcn bit?s value is 0, it indicates receive mode. therefore, the acken bit should be set to 1. when the slave device is receiving (when trcn bit = 0), if the slave device does not need to receive any more data after receiving several bytes, clearing s cln 1 s dan intiicn 2 3 4567 8 9 ad6 ad5 ad4 ad 3 ad2 ad1 ad0 r/w tr a n s fer direction s pecific a tion note
673 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 the acken bit to 0 will prevent the master device from starting transmission of the subsequent data. similarly, when the master device is receiving (when trcn bit = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, clearing the acken bit to 0 will prevent the ack signal from being returned. this prevents the msb from being output via the sdan line (i.e., stops transmission) during transmission from the slave device. figure 19-10 ack signal when the local address is received, an ack signal is automatically output in synchronization with the falling edge of the scln pin?s eighth clock regardless of the value of the acken bit. no ack signal is output if the received address is not a local address. the ack signal output method during data reception is based on the wait timing setting, as described below. when 8-clock wait is selected (iiccn.wtimn bit = 0): the ack signal is output at the falling edge of the scln pin?s eighth clock if the acken bit is set to 1 before wait cancellation. when 9-clock wait is selected (iiccn.wtimn bit = 1): the ack signal is automatically output at the falling edge of the scln pin?s eighth clock if the acken bit has already been set to 1. s cl0n 1 s da0n 2 3 4567 8 9 ad6 ad5 ad4 ad 3 ad2 ad1 ad0 r/w ack
674 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.8.5 stop condition when the scln pin is high level, changing the sdan pin from low level to high level generates a stop condition. a stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. when used as the slave device, the start condition can be detected. figure 19-11 stop condition a stop condition is generated when the iiccn.sptn bit is set to 1. when the stop condition is detected, the iicsn.spdn bit is set to 1 and the intiicn signal is generated when the iiccn.spien bit is set to 1. by setting iiccn.stpn=1 the master device will also cancel its own wait status. h s cln s dan
675 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 19.8.6 wait signal (wait ) the wait signal (wait ) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scln pin to low level notifies the communication partner of the wait status. when the wait status has been cancelled for both the master and slave devices, the next data transfer can begin. (1) when master device has a nine-clock wait and slave device has an eight- clock wait (master: transmission, slave: reception, and iiccn.acken bit = 1) figure 19-12 wait signal (1/2) s cln 6 s dan 7 8 912 3 s cln iicn 6 h 7 8 12 3 d2 d1 d0 ack d7 d6 d5 9 iicn s cln acken m as ter (tx) m as ter ret u rn s to high imped a nce bu t s l a ve i s in w a it s t a te (low level). w a it a fter o u tp u t of ninth clock. iicn d a t a write (c a ncel w a it) s l a ve (rx) w a it a fter o u tp u t of eighth clock. ffh i s written to iicn regi s ter or iiccn.wreln b it i s s et to 1. tr a n s fer line s w a it s ign a l from s l a ve w a it s ign a l from m as ter
676 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 (2) when master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and acken bit = 1) figure 19-13 wait signal (2/2) a wait may be automatically generated depending on the setting of the iiccn.wtimn bit. normally, when the iiccn.wreln bit is set to 1 or when ffh is written to the iicn register on the receiving side, the wait status is cancelled and the transmitting side writes data to the iicn register to cancel the wait status. the master device can also cancel its own wait status via either of the following methods. ? by setting the iiccn.sttn bit to 1 ? by setting the iiccn.sptn bit to 1 s cln 6 s dan 7 8 912 3 s cln iicn 6 h 7 8 12 3 d2 d1 d0 ack d7 d6 d5 9 iicn s cln acken m as ter (tx) m as ter a nd s l a ve b oth w a it a fter o u tp u t of ninth clock. iicn d a t a write (c a ncel w a it) s l a ve (rx) ffh i s written to iicn regi s ter or wreln b it i s s et to 1. o u tp u t a ccording to previo us ly s et acken b it v a l u e tr a n s fer line s w a it s ign a l from m as ter / s l a ve w a it s ign a l from s l a ve
677 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 19.9 i 2 c interrupt request signals (intiicn) the following shows the value of the iicsn register at the intiicn interrupt request signal generation timing and at the intiicn signal timing. 19.9.1 master device operation (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when wtimn bit = 0 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 5 1: iicsn register = 10xxx110b 2: iicsn register = 10xxx000b 3: iicsn register = 10xxx000b (wtimn bit = 1) 4: iicsn register = 10xxxx00b 5: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 <2> when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iicsn register = 10xxx110b 2: iicsn register = 10xxx100b 3: iicsn register = 10xxxx00b 4: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
678 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) <1> when wtimn bit = 0 sttn bit = 1 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 7 1: iicsn register = 10xxx110b 2: iicsn register = 10xxx000b (wtimn bit = 1) 3: iicsn register = 10xxxx00b (wtimn bit = 0) 4: iicsn register = 10xxx110b (wtimn bit = 0) 5: iicsn register = 10xxx000b (wtimn bit = 1) 6: iicsn register = 10xxxx00b 7: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 <2> when wtimn bit = 1 sttn bit = 1 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iicsn register = 10xxx110b 2: iicsn register = 10xxxx00b 3: iicsn register = 10xxx110b 4: iicsn register = 10xxxx00b 5: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
679 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 (3) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtimn bit = 0 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 5 1: iicsn register = 1010x110b 2: iicsn register = 1010x000b 3: iicsn register = 1010x000b (wtimn bit = 1) 4: iicsn register = 1010xx00b 5: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 <2> when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iicsn register = 1010x110b 2: iicsn register = 1010x100b 3: iicsn register = 1010xx00b 4: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
680 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.9.2 slave device operation (1) start ~ address ~ data ~ data ~ stop <1> when wtimn bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iicsn register = 0001x110b 2: iicsn register = 0001x000b 3: iicsn register = 0001x000b 4: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iicsn register = 0001x110b 2: iicsn register = 0001x100b 3: iicsn register = 0001xx00b 4: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
681 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address match) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iicsn register = 0001x110b 2: iicsn register = 0001x000b 3: iicsn register = 0001x110b 4: iicsn register = 0001x000b 5: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, address match) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iicsn register = 0001x110b 2: iicsn register = 0001xx00b 3: iicsn register = 0001x110b 4: iicsn register = 0001xx00b 5: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
682 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 (3) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtimn bit = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iicsn register = 0001x110b 2: iicsn register = 0001x000b 3: iicsn register = 0010x010b 4: iicsn register = 0010x000b 5: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 1: iicsn register = 0001x110b 2: iicsn register = 0001xx00b 3: iicsn register = 0010x010b 4: iicsn register = 0010x110b 5: iicsn register = 0010xx00b 6: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
683 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address mismatch (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 1: iicsn register = 0001x110b 2: iicsn register = 0001x000b 3: iicsn register = 00000x10b 4: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, address mismatch (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 1: iicsn register = 0001x110b 2: iicsn register = 0001xx00b 3: iicsn register = 00000x10b 4: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
684 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.9.3 slave device operation (w hen receiving extension code) (1) start ~ code ~ data ~ data ~ stop <1> when wtimn bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iicsn register = 0010x010b 2: iicsn register = 0010x000b 3: iicsn register = 0010x000b 4: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 5 1: iicsn register = 0010x010b 2: iicsn register = 0010x110b 3: iicsn register = 0010x100b 4: iicsn register = 0010xx00b 5: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
685 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 (2) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address match) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iicsn register = 0010x010b 2: iicsn register = 0010x000b 3: iicsn register = 0001x110b 4: iicsn register = 0001x000b 5: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, address match) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 1: iicsn register = 0010x010b 2: iicsn register = 0010x110b 3: iicsn register = 0010xx00b 4: iicsn register = 0001x110b 5: iicsn register = 0001xx00b 6: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
686 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 (3) start ~ code ~ data ~ start ~ code ~ data ~ stop <1> when wtimn bit = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iicsn register = 0010x010b 2: iicsn register = 0010x000b 3: iicsn register = 0010x010b 4: iicsn register = 0010x000b 5: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 7 1: iicsn register = 0010x010b 2: iicsn register = 0010x110b 3: iicsn register = 0010xx00b 4: iicsn register = 0010x010b 5: iicsn register = 0010x110b 6: iicsn register = 0010xx00b 7: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
687 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 (4) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address mismatch (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 1: iicsn register = 0010x010b 2: iicsn register = 0010x000b 3: iicsn register = 00000x10b 4: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, address mismatch (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iicsn register = 0010x010b 2: iicsn register = 0010x110b 3: iicsn register = 0010xx00b 4: iicsn register = 00000x10b 5: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
688 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.9.4 operation without communication (1) start ~ code ~ data ~ data ~ stop 19.9.5 arbitration loss operati on (operation as slave after arbitration loss) (1) when arbitration loss occurs during transmission of slave address data st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 1: iicsn register = 00000001b remarks 1. : generated only when spien bit = 1 2. n = 0 to 2 <1> when wtimn bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iicsn register = 0101x110b (example: when aldn bit is read during interrupt servicing) 2: iicsn register = 0001x000b 3: iicsn register = 0001x000b 4: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iicsn register = 0101x110b (example: when aldn bit is read during interrupt servicing) 2: iicsn register = 0001x100b 3: iicsn register = 0001xx00b 4: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
689 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 (2) when arbitration loss occurs during transmission of extension code <1> when wtimn bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) 2: iicsn register = 0010x000b 3: iicsn register = 0010x000b 4: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 5 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) 2: iicsn register = 0010x110b 3: iicsn register = 0010x100b 4: iicsn register = 0010xx00b 5: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
690 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.9.6 operation when arbitration loss occurs (1) when arbitration loss occurs during transmission of slave address data (2) when arbitration loss occurs during transmission of extension code st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 1: iicsn register = 01000110b (example: when aldn bit is read during interrupt servicing) 2: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 2. n = 0 to 2 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) iiccn.lreln bit is set to 1 by software 2: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
691 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 (3) when arbitration loss occurs during data transfer <1> when wtimn bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 1: iicsn register = 10001110b 2: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) 3: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 1: iicsn register = 10001110b 2: iicsn register = 01000100b (example: when aldn bit is read during interrupt servicing) 3: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 2. n = 0 to 2
692 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 (4) when arbitration loss occurs due to restart condition during data transfer (5) when arbitration loss occurs due to stop condition during data transfer <1> not extension code (example: address mismatch) st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 1: iicsn register = 1000x110b 2: iicsn register = 01000110b (example: when aldn bit is read during interrupt servicing) 3: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. dn = d6 to d0 n = 0 to 2 <2> extension code st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 1: iicsn register = 1000x110b 2: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) iiccn.lreln bit is set to 1 by software 3: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. dn = d6 to d0 n = 0 to 2 st ad6 to ad0 rw ak d7 to dn sp 1 2 1: iicsn register = 1000x110b 2: iicsn register = 01000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. dn = d6 to d0 n = 0 to 2
693 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 (6) when arbitration loss occurs due to low level of sdan pin when attempting to generate a restart condition (7) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition when wtimn bit = 1 sttn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iicsn register = 1000x110b 2: iicsn register = 1000xx00b 3: iicsn register = 01000100b (example: when aldn bit is read during interrupt servicing) 4: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2 when wtimn bit = 1 sttn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 1: iicsn register = 1000x110b 2: iicsn register = 1000xx00b 3: iicsn register = 01000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
694 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 (8) when arbitration loss occurs due to low level of sdan pin when attempting to generate a stop condition when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iicsn register = 1000x110b 2: iicsn register = 1000xx00b 3: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) 4: iicsn register = 00000001b remarks 1. : always generated : generated only when spien bit = 1 x: dont care 2. n = 0 to 2
695 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 19.10 interrupt request signal (intiicn) the setting of the iiccn.wtimn bit determines the timing by which the intiicn register is generated and the corresponding wait control, as shown below. note 1. the slave device?s intiicn signal and wait period occur at the falling edge of the ninth clock only when there is a match with the address set to the svan register. at this point, the ack signal is output regardless of the value set to the iiccn.acken bit. for a slave device that has received an extension code, the intiicn signal occurs at the falling edge of the eighth clock. when the address does not match after restart, the intiicn signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. if the received address does not match the contents of the svan register and an extension code is not received, neither the intiicn signal nor a wait occurs. 3. the numbers in the table indicate the number of the serial clock?s clock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) during address transmission/reception ? slave device operation: interrupt and wait timing are determined regardless of the wtimn bit. ? master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtimn bit. (2) during data reception ? master/slave device operation: interrupt and wait timing is determined according to the wtimn bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing is determined according to the wtimn bit. table 19-6 intiicn generation timing and wait control wtimn bit during slave device operation during master device operation address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 98 8 1 9 notes 1, 2 9 note 2 9 note 2 99 9
696 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 (4) wait cancellation method the four wait cancellation methods are as follows. ? by setting the iiccn.wreln bit to 1 ? by writing to the iicn register ? by start condition setting (iiccn.sttn bit = 1) note ? by stop condition setting (iiccn.sptn bit = 1) note note master only when an 8-clock wait has been selected (wtimn bit = 0), the output level of the ack signal must be determined prior to wait cancellation. (5) stop condition detection the intiicn signal is generated when a stop condition is detected. 19.11 address match detection method in i 2 c bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. address match detection is performed automatically by hardware. the intiicn signal occurs when a local address has been set to the svan register and when the address set to the svan register matches the slave address sent by the master device, or when an extension code has been received. 19.12 error detection in i 2 c bus mode, the status of the serial data bus pin (sdan) during data transmission is captured by the iicn register of the transmitting device, so the data of the iicn register prior to transmission can be compared with the transmitted iicn data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match.
697 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 19.13 extension code ? when the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (iicsn.excn bit) is set for extension code reception and an interrupt request signal (intiicn) is issued at the falling edge of the eighth clock. the local address stored in the svan register is not affected. ? if 11110xx0 is set to the svan register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. note that the intiicn signal occurs at the falling edge of the eighth clock ? higher four bits of data match: excn bit = 1 ? seven bits of data match: iicsn.coin bit = 1 ? since the processing after the interrupt request signal occurs differs according to the data that follows the extension code, such processing is performed by software. for example, when operation as a slave is not desired after the extension code is received, set the iiccn.lreln bit to 1 and the cpu will enter the next communication wait state. table 19-7 extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for different bus format 1111 0xx x 10-bit slave address specification
698 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.14 arbitration when several master devices simultaneously output a start condition (when the iiccn.sttn bit is set to 1 before the iicsn.stdn bit is set to 1), communication between the master devices is performed while the number of clocks is adjusted until the data differs. this kind of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (iicsn.aldn bit) is set to 1 via the timing by which the arbitration loss occurred, and the scln and sdan lines are both set to high impedance, which releases the bus. arbitration loss is detected based on the timing of the next interrupt request signal (the eighth or ninth clock, when a stop condition is detected, etc.) and the setting of the aldn bit to 1, which is made by software. for details of interrupt request timing, see ?i 2 c interrupt request signals (intiicn)? on page 677 . figure 19-14 arbitration timing example m as ter 1 m as ter 2 tr a n s fer line s s cln s dan s cln s dan s cln s dan m as ter 1 lo s e s a r b itr a tion hi-z hi-z
699 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 note 1. when the iiccn.wtimn bit = 1, an interrupt request signal occurs at the falling edge of the ninth clock. when the wtimn bit = 0 and the extension code?s slave address is received, an interrupt request signal occurs at the falling edge of the eighth clock. 2. when there is a possibility that arbitration will occur, set the spien bit to 1 for master device operation. 19.15 wakeup function the i 2 c bus slave function is a function that generates an interrupt request signal (intiicn) when a local address and extension code have been received. this function makes processing more efficient by preventing unnecessary interrupt request signals from occurring when addresses do not match. when a start condition is detected, wakeup stand-by mode is set. this wakeup stand-by mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detected, the iiccn.spien bit is set regardless of the wakeup function, and this determines whether interrupt request signals are enabled or disabled. table 19-8 status during arbitration and interrupt request signal generation timing status during arbitration interrupt request generation timing transmitting address transmission at falling edge of eighth or ninth clock following byte transfer note 1 read/write data after address transmission transmitting extension code read/write data after extension code transmission transmitting data ack signal transfer period after data reception when restart condition is detected during data transfer when stop condition is detected during data transfer when stop condition is output (when iiccn.spien bit = 1) note 2 when sdan pin is low level while attempting to output restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to output restart condition when stop condition is output (when iiccn.spien bit = 1) note 2 when dsa0n pin is low level while attempting to output stop condition at falling edge of eighth or ninth clock following byte transfer note 1 when scln pin is low level while attempting to output restart condition
700 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.16 communication reservation 19.16.1 communication reserva tion function is enabled (iicfn.iicrsvn bit = 0) to start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes in which the bus is not used: ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (acknowledge is not returned and the bus was released when the iiccn.lreln bit was set to 1). if the iiccn.sttn bit is set to 1 while the bus is not used, a start condition is automatically generated and a wait status is set after the bus is released (after a stop condition is detected). when the bus release is detected (when a stop condition is detected), writing to the iicn register causes master address transfer to start. at this point, the iiccn.spien bit should be set to 1. when sttn has been set to 1, the operation mode (as start condition or as communication reservation) is determined according to the bus status. ? if the bus has been released: start condition is generated ? if the bus has not been released (standby mode): communication reservation to detect which operation mode has been determined for the sttn bit, set the sttn bit to 1, wait for the wait period, then check the iicsn.mstsn bit. the wait periods, which should be set via software, are listed in table 19-9 . these wait periods can be set by the smcn, cln1, and cln0 bits of the iiccln register and the iicxn.clxn bit.
701 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 the communication reservation timing is shown below. table 19-9 wait periods with communication reservation function enabled prescaler i 2 c module input clock i 2 c module set-up transfer clock iiclktc mode waiting time in iiclk cycles ocks iiclkps iicnn. clxn iiccln .smcn iiccln .cln1 iiccln .cln0 18 h iiclk iiclkps 0 0 0 0 iiclk/44 standard 26 10 h iiclk/2 0 0 0 0 1/2 * iiclk/44 52 11 h iiclk/3 0 0 0 0 1/3 * iiclk/44 78 12 h iiclk/4 0 0 0 0 14 * iiclk/44 104 13 h iiclk/5 0 0 0 0 1/5 * iiclk/44 130 18 h iiclk iiclkps 0 0 0 1 iiclk/86 standard 47 10 h iiclk/2 0 0 0 1 1/2 * iiclk/86 94 11 h iiclk/3 0 0 0 1 1/3 * iiclk/86 141 12 h iiclk/4 0 0 0 1 14 * iiclk/86 188 13 h iiclk/5 0 0 0 1 1/5 * iiclk/86 235 x x iiclk 0 0 1 0 iiclk/86 47 18 h iiclk iiclkps 0 0 1 1 iiclk/66 standard 38 10 h iiclk/2 0 0 1 1 1/2 * iiclk/66 76 11 h iiclk/3 0 0 1 1 1/3 * iiclk/66 114 12 h iiclk/4 0 0 1 1 14 * iiclk/66 152 13 h iiclk/5 0 0 1 1 1/5 * iiclk/66 190 18 h iiclk iiclkps 0 1 0 x iiclk/24 fast- speed 16 10 h iiclk/2 0 1 0 x 1/2 * iiclk/24 32 11 h iiclk/3 0 1 0 x 1/3 * iiclk/24 48 12 h iiclk/4 0 1 0 x 14 * iiclk/24 64 13 h iiclk/5 0 1 0 x 1/5 * iiclk/24 80 x x iiclk 0 1 1 0 iiclk/24 16 18 h iiclk iiclkps 0 1 1 1 iiclk/18 fast- speed 13 10 h iiclk/2 0 1 1 1 1/2 * iiclk/18 26 11 h iiclk/3 0 1 1 1 1/3 * iiclk/18 39 12 h iiclk/4 0 1 1 1 14 * iiclk/18 52 13 h iiclk/5 0 1 1 1 1/5 * iiclk/18 65 18 h iiclk iiclkps 1 1 0 x iiclk/12 fast- speed 10 10 h iiclk/2 1 1 0 x 1/2 * iiclk/12 20 11 h iiclk/3 1 1 0 x 1/3 * iiclk/12 30 12 h iiclk/4 1 1 0 x 14 * iiclk/12 40 13 h iiclk/5 1 1 0 x 1/5 * iiclk/12 50 x x iiclk 1 1 1 0 iiclk/12 10
702 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 figure 19-15 communicati on reservation timing communication reservations are accepted via the following timing. after the iicsn.stdn bit is set to 1, a communication reservation can be made by setting the iiccn.sttn bit to 1 before a stop condition is detected. figure 19-16 timing for accepting communication reservations the communication reservation flowchart is illustrated below. 2 1 3 456 2 1 3 456 7 8 9 s cl0n s da0n progr a m proce ss ing h a rdw a re proce ss ing write to iicn s et s pdn a nd intiicn s ttn =1 comm u nic a tion re s erv a tion s et s tdn o u tp u t b y m as ter with bus a cce ss s cl0n s da0n s tdn s pdn s t a nd b y mode
703 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 figure 19-17 communication reservation flowchart note the communication reservation operation executes a write to the iicn register when a stop condition interrupt request occurs. di s et1 s ttn define comm u nic a tion re s erv a tion w a it c a ncel comm u nic a tion re s erv a tion no ye s iicn regi s ter  xxh ei m s t s n b it = 0? (comm u nic a tion re s erv a tion) note (gener a te s t a rt condition) s et s s ttn b it (comm u nic a tion re s erv a tion). s ec u re s w a it period s et b y s oftw a re ( s ee table 17-16 ). confirm a tion of comm u nic a tion re s erv a tion cle a r s us er fl a g. iicn regi s ter write oper a tion define s th a t comm u nic a tion re s erv a tion i s in effect (define s a nd s et s us er fl a g to a ny p a rt of ram).
704 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.16.2 communication reserva tion function is disabled (iicfn.iicrsvn bit = 1) when the iiccn.sttn bit is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. there are two modes in which the bus is not used: ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (acknowledge is not returned and the bus was released when the iiccn.lreln bit was set to 1) to confirm whether the start condition was generated or request was rejected, check the iicfn.stcfn flag. the time shown in table 19-10 is required until the stcfn flag is set after setting the sttn bit to 1. therefore, secure the time by software. table 19-10 wait periods with communication reservation function disabled prescaler i 2 c module input clock i 2 c module set-up waiting time in iiclk cycles ocks iiclkps iicnn. clxn iiccln .smcn iiccln .cln1 iiccln .cln0 18 h iiclk iiclkps xx0x 5 10 h iiclk/2 x x 0 x 10 11 h iiclk/3 x x 0 x 15 12 h iiclk/4 x x 0 x 20 13 h iiclk/5 x x 0 x 25 xx iiclk xx10 5
705 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 19.17 cautions (1) when iicfn.stcenn bit = 0 immediately after the i 2 c0n operation is enabled, the bus communication status (iicfn.iicbsyn bit = 1) is recognized regardless of the actual bus status. to execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication. use the following sequence for generating a stop condition. <1> set the iiccln register. <2> set the iiccn.iicen bit. <3> set the iiccn.sptn bit. (2) when iicfn.stcenn bit = 1 immediately after i 2 c0n operation is enabled, the bus released status (iicbsyn bit = 0) is recognized regardless of the actual bus status. to issue the first start condition (iiccn.sttn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) when the iiccn.iicen bit is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. be sure to set the iiccn.iicen bit to 1 when the scl0n and sda0n lines are high level. (4) determine the operation clock frequency by the iiccln, iicxn, and ocksm registers before enabling the operation (iiccn.iicen bit = 1). to change the operation clock frequency, clear the iiccn.iicen bit to 0 once. (5) after the iiccn.sttn and iiccn.sptn bits have been set to 1, they must not be reset without being cleared to 0 first. (6) if transmission has been reserved, set the iiccn.spien bit to 1 so that an interrupt request is generated by the detection of a stop condition. after an interrupt request has been generated, the wait status will be released by writing communication data to i2cn, then transferring will begin. if an interrupt is not generated by the detection of a stop condition, transmission will halt in the wait status because an interrupt request was not generated. however, it is not necessary to set the spien bit to 1 for the software to detect the iicsn.mstsn bit.
706 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.18 communication operations 19.18.1 master operation with communication reservation the following shows the flowchart for master communication when the communication reservation function is enabled (iicfn.iicrsvn bit = 0) and the master operation is started after a stop condition is detected (iicfn.stcenn bit = 0). figure 19-18 master operation flowchart with communication reservation note refer to table 19-9 on page 701 . iiccn  h iicen = s pien = wtimn = s ptn = 1 iiccln  h s elect tr a n s fer clock s ttn = 1 s ta rt acken = 0 no no no no no no no no no no ye s ye s ye s ye s intiicn = 1? wtimn = 0 acken = 1 intiicn = 1? intiicn = 1? trcn = 1? ackdn = 1? m s t s n = 1? ye s ye s no intiicn = 1? excn or coin = 1? intiicn = 1? ackdn = 1? no ye s ye s m s t s n = 1 & aldn = 0? no ye s m s t s n = 1 & aldn = 0? wreln = 1 s t a rt reception ye s ( s top condition detection) w a it w a it time i s s ec u red b y s oftw a re ( s ee b elow note) ye s ( s t a rt condition gener a tion) comm u nic a tion re s erv a tion no no ye s ye s ye s m s t s n = 1 & aldn = 0? excn or coin = 1? s l a ve oper a tion s t a rt iicn write tr a n s fer s top condition detection, s t a rt condition gener a tion b y comm u nic a tion re s erv a tion gener a te s top condition (no s l a ve with m a tching a ddre ss ) no (receive) addre ss tr a n s fer completion ye s (tr a n s mit) end s t a rt iicn write tr a n s fer d a t a proce ss ing tr a n s fer completed? gener a te s top condition s ptn = 1 (re s t a rt) end tr a n s fer completed? d a t a proce ss ing
707 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 19.18.2 master operation without communication reservation the following shows the flowchart for master communication when the communication reservation function is disabled (iicrsvn bit = 1) and the master operation is started without detecting a stop condition (stcenn bit = 1). figure 19-19 master operation flowchart without communication reservation note refer to table 19-10 on page 704 . no (receive) iiccln  h iicfn  h iiccn  h iicen = s pien = wtimn = 1 s ttn = 1 s ta rt no ye s iicb s yn = 0? no ye s wtimn = 0 acken = 1 wreln = 1 s t a rt reception acken = 0 s ptn = 1 gener a te s top condition no ye s ye s (tr a n s mit) intiicn = 1? no ye s intiicn = 1? no ye s intiicn = 1? no ye s ackdn = 1? no ye s no ackdn = 1? trcn = 1? s tcfn = 0? end tr a n s fer clock s election iicfn regi s ter s etting iiccn regi s ter initi a l s etting w a it time i s s ec u red b y s oftw a re ( s ee b elow note) in s ert w a it s t a rt iicn write tr a n s fer s top m as ter comm u nic a tion m as ter comm u nic a tion i s s topped b ec aus e bus i s occ u pied ye s ( a ddre ss tr a n s fer completion) s t a rt iicn write tr a n s fer gener a te s top condition (no s l a ve with m a tching a ddre ss ) end d a t a proce ss ing d a t a proce ss ing reception completed? tr a n s fer completed? (re s t a rt) no no ye s ye s ye s m s t s n = 1 & aldn = 0? excn or coin = 1? s l a ve oper a tion no ye s ye s m s t s n = 1 & aldn = 0? no ye s m s t s n = 1 & aldn = 0?
708 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.18.3 slave operation the following shows the processing procedure of the slave operation. basically, the operation of the slave device is event-driven. therefore, processing by an intiicn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary. the following description assumes that data communication does not support extension codes. also, it is assumed that the intiicn interrupt servicing performs only status change processing and that the actual data communication is performed during the main processing. figure 19-20 software outline during slave operation therefore, the following three flags are prepared so that the data transfer processing can be performed by transmitting these flags to the main processing instead of intiicn signal. (1) communication mode flag this flag indicates the following communication statuses. ? clear mode: data communication not in progress ? communication mode data communication in progress (valid address detection stop condition detection, ack signal from master not detected, address mismatch) (2) ready flag this flag indicates that data communication is enabled. this is the same status as an intiicn interrupt during normal data transfer. this flag is set in the interrupt processing block and cleared in the main processing block. the ready flag for the first data for transmission is not set in the interrupt processing block, so the first data is transmitted without clear processing (the address match is regarded as a request for the next data). i 2 c intiicn s ign a l s etting, etc. s etting, etc. fl a g d a t a m a in proce ss ing interr u pt s ervicing
709 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 (3) communication direction flag this flag indicates the direction of communication and is the same as the value of iicsn.trcn bit. the following shows the operation of the main processing block during slave operation. start i 2 c0n and wait for the communication enabled status. when communication is enabled, perform transfer using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). for transmission, repeat the transmission operation until the master device stops returning ack signal. when the master device stops returning ack signal, transfer is complete. for reception, receive the required number of data and do not return ack signal for the next data immediately after transfer is complete. after that, the master device generates the stop condition or restart condition. this causes exit from communications.
710 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 figure 19-21 slave operation flowchart (1) the following shows an example of the processing of the slave device by an intiicn interrupt (it is assumed that no extension codes are used here). ye s ye s ye s ye s ye s ye s ye s ye s no no no no no no no no s ta rt comm u nic a tion mode? comm u nic a tion mode? comm u nic a tion mode? re a dy? re a dy? re a d d a t a cle a r re a dy fl a g cle a r re a dy fl a g comm u nic a tion direction fl a g = 1? wtimn = 1 wreln = 1 acken = 0 wreln = 1 acken = wtimn = 1 ackdn = 1? wreln = 1 cle a r comm u nic a tion mode fl a g d a t a proce ss ing d a t a proce ss ing tr a n s fer completed? iicn  d a t a iiccn  xxh iicen = 1 iiccln  xxh iicfn  xxh s election of tr a n s fer fl a g iicfn regi s ter s etting
711 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 during an intiicn interrupt, the status is confirmed and the following steps are executed. <1> when a stop condition is detected, communication is terminated. <2> when a start condition is detected, the address is confirmed. if the address does not match, communication is terminated. if the address matches, the communication mode is set and wait is released, and operation returns from the interrupt (the ready flag is cleared). <3> for data transmission/reception, when the ready flag is set, operation returns from the interrupt while the iic0n bus remains in the wait status. note <1> to <3> in the above correspond to <1> to <3> in figure 19-22 . figure 19-22 slave operation flowchart (2) ye s ye s ye s no no no intiicn gener a ted s et re a dy fl a g interr u pt s ervicing completed interr u pt s ervicing completed interr u pt s ervicing completed termin a tion proce ss ing s pdn = 1? s tdn = 1? coin = 1? lreln = 1 cle a r comm u nic a tion mode comm u nic a tion direction fl a g  trcn s et comm u nic a tion mode fl a g cle a r re a dy fl a g <1> <2> < 3 >
712 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 19.19 timing of data communication when using i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device transmits the iicsn.trcn bit, which specifies the data transfer direction, and then starts serial communication with the slave device. the shift operation of the iicn register is synchronized with the falling edge of the serial clock pin (scln). the transmit data is transferred to the so latch and is output (msb first) via the sdan pin. data input via the sdan pin is captured by the iicn register at the rising edge of the scln pin. the data communication timing is shown below.
713 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 figure 19-23 example of master to slave communication (when 9-clock wait is selected for both master and slave) (1/3) start condition ~ address note to cancel slave wait, write ffh to iicn or set wreln. iicn ackdn s tdn s pdn wtimn h h l l l l h h h l l acken m s t s n s ttn s ptn wreln intiicn trcn iicn ackdn s tdn s pdn wtimn acken m s t s n s ttn s ptn wreln intiicn trcn s cl0n s da0n proce ss ing b y m as ter device tr a n s fer line s proce ss ing b y s l a ve device 12 3 4567 8 94 3 2 1 ad6 ad5 ad4 ad 3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iicn  a ddre ss iicn  d a t a iicn  ffh tr a n s mit s t a rt condition receive (when excn = 1) note note
714 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 figure 19-24 example of master to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data note to cancel slave wait, write ffh to iicn or set wreln. iicn ackdn s tdn s pdn wtimn h h l l l l l l h h h h l l l l l acken m s t s n s ttn s ptn wreln intiicn trcn iicn ackdn s tdn s pdn wtimn acken m s t s n s ttn s ptn wreln intiicn trcn s cl0n s da0n proce ss ing b y m as ter device tr a n s fer line s proce ss ing b y s l a ve device 1 9 8 2 3 4567 8 9 3 2 1 d7 d0 d6 d5 d4 d 3 d2 d1 d0 d5 d6 d7 iicn  d a t a iicn  ffh note iicn  ffh note iicn  d a t a tr a n s mit receive note note
715 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 figure 19-25 example of master to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition note to cancel slave wait, write ffh to iicn or set wreln. iicn ackdn s tdn s pdn wtimn h h l l l l h h h l acken m s t s n s ttn s ptn wreln intiicn trcn iicn ackdn s tdn s pdn wtimn acken m s t s n s ttn s ptn wreln intiicn trcn s cl0n s da0n proce ss ing b y m as ter device tr a n s fer line s proce ss ing b y s l a ve device 12 3 4567 8 92 1 d7 d6 d5 d4 d 3 d2 d1 d0 ad5 ad6 iicn  d a t a iicn  a ddre ss iicn  ffh note iicn  ffh note s top condition s t a rt condition tr a n s mit note note (when s pien = 1) receive (when s pien = 1)
716 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 figure 19-26 example of slave to master communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address note to cancel master wait, write ffh to iicn or set wreln. iicn ackdn s tdn s pdn wtimn h h l l h h l acken m s t s n s ttn l l s ptn wreln intiicn trcn iicn ackdn s tdn s pdn wtimn acken m s t s n s ttn s ptn wreln intiicn trcn s cl0n s da0n proce ss ing b y m as ter device tr a n s fer line s proce ss ing b y s l a ve device 12 3 4567 8 9456 3 2 1 ad6 ad5 ad4 ad 3 ad2 ad1 ad0 r d4 d 3 d2 d5 d6 d7 iicn  a ddre ss iicn  ffh note note iicn  d a t a s t a rt condition
717 i 2 c bus (iic) chapter 19 user?s manual u17566ee5v1um00 figure 19-27 example of slave to master communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data note to cancel master wait, write ffh to iicn or set wreln. iicn ackdn s tdn s pdn wtimn h h h l l l l l l h h h l l l l l acken m s t s n s ttn s ptn wreln intiicn trcn iicn ackdn s tdn s pdn wtimn acken m s t s n s ttn s ptn wreln intiicn trcn s cl0n s da0n proce ss ing b y m as ter device tr a n s fer line s proce ss ing b y s l a ve device 1 8 9 2 3 4567 8 9 3 2 1 d7 d0 ack d6 d5 d4 d 3 d2 d1 d0 ack d5 d6 d7 note note receive tr a n s mit iicn  d a t a iicn  d a t a iicn  ffh note iicn  ffh note
718 chapter 19 i 2 c bus (iic) user?s manual u17566ee5v1um00 figure 19-28 example of slave to master communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition note to cancel master wait, write ffh to iicn or set wreln. iicn ackdn s tdn s pdn wtimn h h l l l h acken m s t s n s ttn s ptn wreln intiicn trcn iicn ackdn s tdn s pdn wtimn acken m s t s n s ttn s ptn wreln intiicn trcn s cl0n s da0n proce ss ing b y m as ter device tr a n s fer line s proce ss ing b y s l a ve device 12 3 4567 8 92 1 d7d6d5d4d 3 d2d1d0ad5 ad6 iicn  a ddre ss iicn  ffh note note iicn  d a t a s top condition s t a rt condition (when s pien = 1) n- ack (when s pien = 1)
719 user?s manual u17566ee5v1um00 chapter 20 can controller (can) these microcontrollers feature an on-chip n-channel can (controller area network) controller that complies with the can protocol as standardized in iso 11898. the v850e/dx3 microcontrollers have following number of channels of the can controller: note 1. throughout this chapter, the individual can channels are identified by ?n?, for example cann, or cngmctrl for the cann global control register. 2. throughout this chapter, the can message buffer registers are identified by ?m? (m = 0 to 31), for example c0mdata4m for can0 message data byte 4 of message buffer register m. 3. it is recommended to configure the ports used for can data transmit ctxdn to its highest drive strength to limit2 by pdscn.pdscnm = 1 for can baud rates above 200 kbit/sec. can pd70f3427, pd70f3425, pd70f3424, pd70f3423, pd70f3422, pd70f3421 pd70f3426a instances 3 2 names can0 to can2 can0 to can1
720 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.1 features ? compliant with iso 11898 and tested according to iso/dis 16845 (can conformance test) ? standard frame and extended frame transmission/reception enabled ? transfer rate: 1 mbps max. (if can clock input  8 mhz, for 32 channels) ? 32 message buffers per channel ? receive/transmit history list function ? automatic block transmission function ? multi-buffer receive block function ? mask setting of four patterns is possible for each channel ? wake-up capability on can receive data pins crxdn ? data bit time, communication baud rate and sample point can be controlled by can module bit-rate prescaler register (cnbrp) and bit rate register (cnbtr) ? as an example the following sample-point configurations can be configured: ? 66.7%, 70.0%, 75.0%, 80.0%, 81.3%, 85.0%, 87.5% ? baudrates in the range of 10 kbps up to 1000 kbps can be configured ? enhanced features: ? each message buffer can be configured to operate as a transmit or a receive message buffer ? transmission priority is controlled by the identifier or by mailbox number (selectable) ? a transmission request can be aborted by clearing the dedicated transmit-request flag of the concerned message buffer. ? automatic block transmission operation mode (abt) ? time stamp function for can channels 0 and 1 in collaboration with timer timer g0 and timer g1 capture channels
721 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.1.1 overview of functions table 20-1 presents an overview of the can controller functions. table 20-1 overview of functions function details protocol can protocol iso 11898 (standard and extended frame transmission/reception) baud rate maximum 1 mbps (can clock input  8 mhz) data storage storing messages in the can ram number of messages ? 32 message buffers per channel ? each message buffer can be set to be either a transmit message buffer or a receive message buffer. message reception ? unique id can be set to each message buffer. ? mask setting of four patterns is possible for each channel. ? a receive completion interrupt is generated each time a message is received and stored in a message buffer. ? two or more receive message buffers can be used as a fifo receive buffer (multi-buffer receive block function). ? receive history list function message transmission unique id can be set to each message buffer. ? transmit completion interrupt for each message buffer ? message buffer number 0 to 7 specified as the transmit message buffer can be set for automatic block transfer. message transmission interval is programmable (automatic block transmission function (hereafter referred to as ?abt?)). ? transmission history list function remote frame processing remote frame processing by transmit message buffer time stamp function ? the time stamp function can be set for a message reception when a 16-bit timer is used in combination. ? time stamp capture trigger can be selected (sof or eof in a can message frame can be detected.). ? the time stamp function can be set for a transmit message. diagnostic function ? readable error counters ? ?valid protocol operation flag? for verification of bus connections ? receive-only mode ? single-shot mode ? can protocol error type decoding ? self-test mode release from bus-off state ? forced release from bus-off (by ignoring timing constraint) possible by software. ? no automatic release from bus-off (software must re-enable). power save mode ? can sleep mode (can be woken up by can bus) ? can stop mode (cannot be woken up by can bus)
722 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.1.2 configuration the can controller is composed of the following four blocks. ? npb interface this functional block provides an npb (nec peripheral i/o bus) interface and means of transmitting and receiving signals between the can module and the host cpu. ? mac (memory access controller) this functional block controls access to the can protocol layer and to the can ram within the can module. ? can protocol layer this functional block is involved in the operation of the can protocol and its related settings. ?can ram this is the can memory functional block, which is used to store message ids, message data, etc. figure 20-1 block diagram of can module ctxdn crxdn cpu can mod u le can ram npb (nec peripher a l i/o b us ) mcm (me ssa ge control mod u le) npb interf a ce interr u pt re qu e s t can protocol l a yer can tr a n s ceiver me ssa ge bu ffer 0 me ssa ge bu ffer 1 me ssa ge bu ffer 2 pclk0 t s outcn me ssa ge bu ffer 3 me ssa ge bu ffer m c1ma s k1 c1ma s k2 c1ma s k 3 c1ma s k4 ... intcntrx intcnrec intcnerr intcnwup can_h can_l can bus
723 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.2 can protocol can (controller area network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class c). can is prescribed by iso 11898. for details, refer to the iso 11898 specifications. the can specification is generally divided into two layers: a physical layer and a data link layer. in turn, the data link layer includes logical link and medium access control. the composition of these layers is illustrated below. figure 20-2 composition of layers note can controller specification 20.2.1 frame format (1) standard format frame ? the standard format frame uses 11-bit identifiers, which means that it can handle up to 2,048 messages. (2) extended format frame ? the extended format frame uses 29-bit (11 bits + 18 bits) identifiers, which increases the number of messages that can be handled to 2,048 2 18 messages. ? an extended format frame is set when ?recessive level? (cmos level of ?1?) is set for both the srr and ide bits in the arbitration field. phy s ic a l l a yer pre s cription of s ign a l level a nd b it de s cription d a t a link l a yer note logic a l link control (llc) medi u m a cce ss control (mac) accept a nce filtering overlo a d report recovery m a n a gement d a t a c a p su led/not c a p su led fr a me coding ( s t u ffing/no s t u ffing) medi u m a cce ss m a n a gement error detection error report acknowledgement s eri a ted/not s eri a ted higher lower
724 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.2.2 frame types the following four types of frames are used in the can protocol. table 20-2 frame types (1) bus value the bus values are divided into dominant and recessive. ? dominant level is indicated by logical 0. ? recessive level is indicated by logical 1. ? when a dominant level and a recessive level are transmitted simultaneously, the bus value becomes dominant level. 20.2.3 data frame and remote frame (1) data frame a data frame is composed of seven fields. figure 20-3 data frame note d: dominant = 0 r: recessive = 1 frame type description data frame frame used to transmit data remote frame frame used to request a data frame error frame frame used to report error detection overload frame frame used to delay the next data frame or remote frame r d interfr a me s p a ce end of fr a me (eof) ack field crc field d a t a field control field ar b itr a tion field s t a rt of fr a me ( s of) d a t a fr a me <1> <2> < 3 > <4> <5> <6> <7> < 8 >
725 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (2) remote frame a remote frame is composed of six fields. figure 20-4 remote frame note 1. the data field is not transferred even if the control field?s data length code is not ?0000 b ?. 2. d: dominant = 0 r: recessive = 1 (3) description of fields (a) start of frame (sof) the start of frame field is located at the start of a data frame or remote frame. figure 20-5 start of frame (sof) note d: dominant = 0 r: recessive = 1 ? if dominant level is detected in the bus idle state, a hard-synchronization is performed (the current tq is assigned to be the sync segment). ? if dominant level is sampled at the sample point following such a hard- synchronization, the bit is assigned to be a sof. if recessive level is detected, the protocol layer returns to the bus idle state and regards the preceding dominant pulse as a disturbance only. no error frame is generated in such case. r d interfr a me s p a ce end of fr a me (eof) ack field crc field control field ar b itr a tion field s t a rt of fr a me ( s of) remote fr a me <1> <2> < 3 > <5> <6> <7> < 8 > r d 1 b it s t a rt of fr a me (interfr a me s p a ce or bus idle) (ar b itr a tion field)
726 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (b) arbitration field the arbitration field is used to set the priority, data frame/remote frame, and frame format. figure 20-6 arbitration field (in standard format mode) caution 1. id28 to id18 are identifiers. 2. an identifier is transmitted msb first. note d: dominant = 0 r: recessive = 1 figure 20-7 arbitration field (in extended format mode) caution 1. id28 to id18 are identifiers. 2. an identifier is transmitted msb first. note d: dominant = 0 r: recessive = 1 table 20-3 rtr frame settings table 20-4 frame format setting (ide bit) and number of identifier (id) bits r d ide (r1) r0 rtr identifier arbitration field (control field) (11 bits) (1 bit) (1 bit) id28 id18 r d r1 r0 rtr ide srr identifier identifier arbitration field (control field) (11 bits) (18 bits) id17 id0 (1 bit) (1 bit) (1 bit) id28 id18 frame type rtr bit data frame 0 (d) remote frame 1 (r) frame format srr bit ide bit number of bits standard format mode none 0 (d) 11 bits extended format mode 1 (r) 1 (r) 29 bits
727 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (c) control field the control field sets ?dlc? as the number of data bytes in the data field (dlc = 0 to 8). figure 20-8 control field note d: dominant = 0 r: recessive = 1 in a standard format frame, the control field?s ide bit is the same as the r1 bit. table 20-5 data length setting caution in the remote frame, there is no data field even if the data length code is not 0000 b . r d r1 (ide) r0 rtr dlc2 dlc 3 dlc1 dlc0 control field (d a t a field) (ar b itr a tion field) data length code data byte count dlc3 dlc2 dlc1 dlc0 0000 0 bytes 0001 1 byte 0010 2 bytes 0011 3 bytes 0100 4 bytes 0101 5 bytes 0110 6 bytes 0111 7 bytes 1000 8 bytes other than above 8 bytes regardless of the value of dlc3 to dlc0
728 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (d) data field the data field contains the amount of data (byte units) set by the control field. up to 8 units of data can be set. figure 20-9 data field note d: dominant = 0 r: recessive = 1 (e) crc field the crc field is a 16-bit field that is used to check for errors in transmit data. figure 20-10 crc field note d: dominant = 0 r: recessive = 1 ? the polynomial p(x) used to generate the 15-bit crc sequence is expressed as follows. p(x) = x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1 ? transmitting node: transmits the crc sequence calculated from the data (before bit stuffing) in the start of frame, arbitration field, control field, and data field. ? receiving node: compares the crc sequence calculated using data bits that exclude the stuffing bits in the receive data with the crc sequence in the crc field. if the two crc sequences do not match, the node issues an error frame. r d d a t a 0 ( 8 b it s ) m s b  l s b d a t a 7 ( 8 b it s ) m s b  l s b d a t a field (crc field) (control field) r d crc s e qu ence crc delimiter (1 b it) (15 b it s ) crc field (ack field) (d a t a field or control field)
729 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (f) ack field the ack field is used to acknowledge normal reception. figure 20-11 ack field note d: dominant = 0 r: recessive = 1 ? if no crc error is detected, the receiving node sets the ack slot to the dominant level. ? the transmitting node outputs two recessive-level bits. (g) end of frame (eof) the end of frame field indicates the end of data frame/remote frame. figure 20-12 end of frame (eof) note d: dominant = 0 r: recessive = 1 (h) interframe space the interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. ? the bus state differs depending on the error status. ? error active node the interframe space consists of a 3-bit intermission field and a bus idle field. figure 20-13 interframe space (error active node) r d ack s lot (1 b it) ack delimiter (1 b it) ack field (end of fr a me) (crc field) r d end of fr a me (7 b it s ) (interfr a me s p a ce or overlo a d fr a me) (ack field) r d interfr a me s p a ce intermi ss ion ( 3 b it s ) b us idle (0 to b it s ) (fr a me) (fr a me)
730 chapter 20 can controller (can) user?s manual u17566ee5v1um00 note 1. bus idle: state in which the bus is not used by any node. 2. d: dominant = 0 r: recessive = 1 ? error passive node the interframe space consists of an intermission field, a suspend transmission field, and a bus idle field. figure 20-14 interframe space (error passive node) note 1. bus idle: state in which the bus is not used by any node. suspend transmission: sequence of 8 recessive-level bits transmitted from the node in the error passive status. 2. d: dominant = 0 r: recessive = 1 usually, the intermission field is 3 bits. if the transmitting node detects a dominant level at the third bit of the intermission field, however, it executes transmission. ? operation in error status table 20-6 operation in error status r d interfr a me s p a ce intermi ss ion ( 3 b it s ) sus pend tr a n s mi ss ion ( 8 b it s ) b us idle (0 to b it s ) (fr a me) (fr a me) error status operation error active a node in this status can transmit immediately after a 3-bit intermission. error passive a node in this status can transmit 8 bits after the intermission.
731 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.2.4 error frame an error frame is output by a node that has detected an error. figure 20-15 error frame note d: dominant = 0 r: recessive = 1 table 20-7 definition of error frame fields no. name bit count definition <1> error flag 1 6 error active node: outputs 6 dominant-level bits consecutively. error passive node: outputs 6 recessive-level bits consecutively. if another node outputs a dominant level while one node is outputting a passive error flag, the passive error flag is not cleared until the same level is detected 6 bits in a row. <2> error flag 2 0 to 6 nodes receiving error flag 1 detect bit stuff errors and issues this error flag. <3> error delimiter 8 outputs 8 recessive-level bits consecutively. if a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> error bit ? the bit at which the error was detected. the error flag is output from the bit next to the error bit. in the case of a crc error, this bit is output following the ack delimiter. <5> interframe space/ overload frame ? an interframe space or overload frame starts from here. <1> r d <2> < 3 > 6 b it s 0 to 6 b it s 8 b it s (<4>) (<5>) interfr a me s p a ce or overlo a d fr a me error delimiter error fl a g 2 error fl a g 1 error b it error fr a me
732 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.2.5 overload frame an overload frame is transmitted under the following conditions. ? when the receiving node has not completed the reception operation ? if a dominant level is detected at the first two bits during intermission ? if a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error delimiter/overload delimiter note the can is internally fast enough to process all received frames not generating overload frames. figure 20-16 overload frame note d: dominant = 0 r: recessive = 1 table 20-8 definition of overload frame fields 20.3 functions 20.3.1 determining bus priority (1) when a node starts transmission: ? during bus idle, the node that output data first transmits the data. no name bit count definition <1> overload flag 6 outputs 6 dominant-level bits consecutively. <2> overload flag from other node 0 to 6 the node that received an overload flag in the interframe space outputs an overload flag. <3> overload delimiter 8 outputs 8 recessive-level bits consecutively. if a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> frame ? output following an end of frame, error delimiter, or overload delimiter. <5> interframe space/overload frame ? an interframe space or overload frame starts from here. <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame overload delimiter overload flag overload flag frame overload frame
733 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (2) when more than one node starts transmission: ? the node that consecutively outputs the dominant level for the longest from the first bit of the arbitration field has the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value). ? the transmitting node compares its output arbitration field and the data level on the bus. table 20-9 determining bus priority (3) priority of data frame and remote frame ? when a data frame and a remote frame are on the bus, the data frame has priority because its rtr bit, the last bit in the arbitration field, carries a dominant level. note if the extended-format data frame and the standard-format remote frame conflict on the bus (if id28 to id18 of both of them are the same), the standard- format remote frame takes priority. 20.3.2 bit stuffing bit stuffing is used to establish synchronization by appending 1 bit of inverted- level data if the same level continues for 5 bits, in order to prevent a burst error. table 20-10 bit stuffing 20.3.3 multi masters as the bus priority (a node acquiring transmit functions) is determined by the identifier, any node can be the bus master. level match continuous transmission level mismatch stops transmission at the bit where mismatch is detected and starts reception at the following bit transmission during the transmission of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, 1 inverted-level bit of data is inserted before the following bit. reception during the reception of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, reception is continued after deleting the next bit.
734 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.3.4 multi cast although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes. 20.3.5 can sleep mode/can stop mode function the can sleep mode/can stop mode function puts the can controller in waiting mode to achieve low power consumption. the controller is woken up from the can sleep mode by bus operation but it is not woken up from the can stop mode by bus operation (the can stop mode is controlled by cpu access). 20.3.6 error control function (1) error types table 20-11 error types (2) output timing of error frame type description of error detection state detection method detection condition transmission/ reception field/frame bit error comparison of the output level and level on the bus (except stuff bit) mismatch of levels transmitting/ receiving node bit that is outputting data on the bus at the start of frame to end of frame, error frame and overload frame. stuff error check of the receive data at the stuff bit 6 consecutive bits of the same output level receiving node start of frame to crc sequence crc error comparison of the crc sequence generated from the receive data and the received crc sequence mismatch of crc receiving node crc field form error field/frame check of the fixed format detection of fixed format violation receiving node crc delimiter ack field end of frame error frame overload frame ack error check of the ack slot by the transmitting node detection of recessive level in ack slot transmitting node ack slot table 20-12 output timing of error frame type output timing bit error, stuff error, form error, ack error error frame output is started at the timing of the bit following the detected error. cec error error frame output is started at the timing of the bit following the ack delimiter.
735 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (3) processing in case of error the transmission node re-transmits the data frame or remote frame after the error frame. (however, it does not re-transmit the frame in the single-shot mode.) (4) error state (a) types of error states the following three types of error states are defined by the can specification: ? error active ? error passive ?bus-off these types of error states are classified by the values of the tec7 to tec0 bits (transmission error counter bits) and the rec6 to rec0 bits (reception error counter bits) as shown in table 20-13 . the present error state is indicated by the can module information register (cninfo). when each error counter value becomes equal to or greater than the error warning level (96), the tecs0 or recs0 bit of the cninfo register is set to 1. in this case, the bus state must be tested because it is considered that the bus has a serious fault. an error counter value of 128 or more indicates an error passive state and the tecs1 or recs1 bit of the cninfo register is set to 1. ? if the value of the transmission error counter is greater than or equal to 256 (actually, the transmission error counter does not indicate a value greater than or equal to 256), the bus-off state is reached and the boff bit of the cninfo register is set to 1. ? if only one node is active on the bus at startup (i.e., a particular case such as when the bus is connected only to the local station), ack is not returned even if data is transmitted. consequently, re-transmission of the error frame and data is repeated. in the error passive state, however, the transmission error counter is not incremented and the bus-off state is not reached.
736 chapter 20 can controller (can) user?s manual u17566ee5v1um00 table 20-13 types of error states note the value of the transmission error counter (tec) is invalid when the boff bit is set to 1. if an error that increments the value of the transmission error counter by +8 while the counter value is in a range of 248 to 255, the counter is not incremented and the bus-off state is assumed. type operation value of error counter indication of cninfo register operation specific to error state error active transmission 0 to 95 tecs1, tecs0 = 00 outputs an active error flag (6 consecutive dominant-level bits) on detection of the error. reception 0 to 95 recs1, recs0 = 00 transmission 96 to 127 tecs1, tecs0 = 01 reception 96 to 127 recs1, recs0 = 01 error passive transmission 128 to 255 tecs1, tecs0 = 11 outputs a passive error flag (6 consecutive recessive-level bits) on detection of the error. transmits 8 recessive-level bits, in between transmissions, following an intermission (suspend transmission). reception 128 or more recs1, recs0 = 11 bus-off transmission 256 or more (not indicated) note boff = 1, tecs1, tecs0 = 11 communication is not possible. messages are not stored when receiving frames, however, the following operations of <1>, <2>, and <3> are done. <1> tsout toggles. <2> rec is incremented/decremented. <3> valid bit is set. if the can module is entered to the initialization mode and then transition request to any operation mode is made, and when 11 consecutive recessive-level bits are detected 128 times, the error counter is reset to 0 and the error active state can be restored.
737 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (b) error counter the error counter counts up when an error has occurred, and counts down upon successful transmission and reception. the error counter is updated immediately after error detection. (c) occurrence of bit error in intermission an overload frame is generated. caution if an error occurs, it is controlled according to the contents of the transmission error counter and reception error counter before the error occurred. the value of the error counter is incremented after the error flag has been output. table 20-14 error counter state transmission error counter (tec7 to tec0 bits) reception error counter (rec6 to rec0 bits) receiving node detects an error (except bit error in the active error flag or overload flag). no change +1 (when reps = 0) receiving node detects dominant level following error flag of error frame. no change +8 (when reps = 0) transmitting node transmits an error flag. [as exceptions, the error counter does not change in the following cases.] <1> ack error is detected in error passive state and dominant level is not detected while the passive error flag is being output. <2> a stuff error is detected in an arbitration field that transmitted a recessive level as a stuff bit, but a dominant level is detected. +8 no change bit error detection while active error flag or overload flag is being output (error-active transmitting node) +8 no change bit error detection while active error flag or overload flag is being output (error-active receiving node) no change +8 (reps bit = 0) when the node detects 14 consecutive dominant-level bits from the beginning of the active error flag or overload flag, and then subsequently detects 8 consecutive dominant- level bits. when the node detects 8 consecutive dominant levels after a passive error flag +8 (transmitting) +8 (during reception, when reps = 0) when the transmitting node has completed transmission without error ( 0 if error counter = 0) ?1 no change when the receiving node has completed reception without error no change ? ?1 (1  rec6 to rec0  127, when reps = 0) ? 0 (rec6 to rec0 = 0, when reps = 0) ? value of 119 to 127 is set (when reps = 1)
738 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (5) recovery from bus-off state when the can module is in the bus-off state, the can module permanently sets its output signals (ctxdn) to recessive level. the can module recovers from the bus-off state in the following bus-off recovery sequence. 1. a request to enter th e can initialization mode 2. a request to enter a can operation mode (a)recovery operation through normal recovery sequence (b)forced recovery operation that skips recovery sequence (a) recovery from bus-off state through normal recovery sequence the can module first issues a request to enter the initialization mode (refer too timing <1> in figure 20-17 on page 739 ). this request will be immediately acknowledged, and the opmode bits of the cnctrl. register are cleared to 000 b . processing such as analyzing the fault that has caused the bus-off state, re-defining the can module and message buffer using application software, or stopping the operation of the can module can be performed by clearing the gom bit to 0. next, the module requests to change the mode from the initialization mode to an operation mode (refer to timing <2> in figure 20-17 on page 739 ). this starts an operation to recover the can module from the bus-off state. the conditions under which the module can recover from the bus-off state are defined by the can protocol iso 11898, and it is necessary to detect 11 consecutive recessive-level bits 128 times. at this time, the request to change the mode to an operation mode is held pending until the recovery conditions are satisfied. when the recovery conditions are satisfied (refer to timing <3> in figure 20-17 on page 739 ), the can module can enter the operation mode it has requested. until the can module enters this operation mode, it stays in the initialization mode. completion to be requested operation mode can be confirmed by reading the opmode bits of the cnctrl register. during the bus-off period and bus-off recovery sequence, the boff bit of the cninfo register stays set (to 1). in the bus-off recovery sequence, the reception error counter (rec[6:0]) counts the number of times 11 consecutive recessive-level bits have been detected on the bus. therefore, the recovery state can be checked by reading rec[6:0].
739 can controller (can) chapter 20 user?s manual u17566ee5v1um00 caution in the bus-off recovery sequence, rec[6:0] counts up (+1) each time 11 consecutive recessive-level bits have been detected. even during the bus-off period, the can module can enter the can sleep mode or can stop mode. to start the bus-off recovery sequence, it is necessary to transit to the initialization mode once. however, when the can module is in either can sleep mode or can stop mode, transition request to the initialization mode is not accepted, thus you have to release the can sleep mode first. in this case, as soon as the can sleep mode is released, the bus-off recovery sequence starts and no transition to initialization mode is necessary. if the can module detects a dominant edge on the can bus while in sleep mode even during bus-off, the sleep mode will be left and the bus-off recovery sequence will start. figure 20-17 recovery from bus-off state through normal recovery sequence (b) forced recovery operation that skips bus-off recovery sequence the can module can be forcibly released from the bus-off state, regardless of the bus state, by skipping the bus-off recovery sequence. here is the procedure. first, the can module requests to enter the initialization mode. for the operation and points to be noted at this time, ?recovery from bus-off state through normal recovery sequence? on page 738 . next, the module requests to enter an operation mode. at the same time, the ccerc bit of the cnctrl register must be set to 1. as a result, the bus-off recovery sequence defined by the can protocol iso 11898 is skipped, and the module immediately enters the operation mode. in this case, the module is connected to the can bus after it has monitored 11 consecutive recessive-level bits. for details, refer to the processing in figure 20-55 on page 850 . ?error-p ass ive? 00h 00h 00h 00h 8 0h  tec[7:0]  ffh ?? ? ? boff b it in cninfo regi s ter opmode[2:0] in cnctrl regi s ter ( us er writing s ) opmode[2:0] in cnctrl regi s ter ( us er re a ding s ) tec[7:0] in cnerc regi s ter rep s , rec[6:0] in cnerc regi s ter tec > ffh 00h 00h 00h ffh < tec [7:0] ? bus -off? ? bus -off-recovery- s e qu ence? ?error- a ctive? 00h  tec[7:0] < 8 0h 00h  rep s , rec[6:0] < 8 0h 00h  rep s , rec[6:0]  8 0h <1> <2> < 3 > undefined
740 chapter 20 can controller (can) user?s manual u17566ee5v1um00 caution this function is not defined by the can protocol iso 11898. when using this function, thoroughly evaluate its effect on the network system. (6) initializing can module error counter register (cnerc) in initialization mode if it is necessary to initialize the can module error counter register (cnerc) and can module information register (cninfo) for debugging or evaluating a program, they can be initialized to the default value by setting the ccerc bit of the cnctrl register in the initialization mode. when initialization has been completed, the ccerc bit is automatically cleared to 0. caution 1. this function is enabled only in the initialization mode. even if the ccerc bit is set to 1 in a can operation mode, the cnerc and cninfo registers are not initialized. 2. the ccerc bit can be set at the same time as the request to enter a can operation mode.
741 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.3.7 baud rate control function (1) prescaler the can controller has a prescaler that divides the clock (f can ) supplied to can. this prescaler generates a can protocol layer basic system clock (f tq ) derived from the can module system clock (f canmod ), and divided by 1 to 256 ( ?cnbrp - cann module bit rate prescaler register? on page 772 ). (2) data bit time (8 to 25 time quanta) one data bit time is defined as shown in figure 20-18 on page 741 . the can controller sets time segment 1, time segment 2, and resynchronization jump width (sjw) of data bit time, as shown in figure 20-18 . time segment 1 is equivalent to the total of the propagation (prop) segment and phase segment 1 that are defined by the can protocol specification. time segment 2 is equivalent to phase segment 2. figure 20-18 segment setting table 20-15 segment setting note 1. ipt: information processing time 2. tq: time quanta reference: the can protocol specification defines the segments constituting the data bit time as shown in figure 20-19 . segment name settable range notes on setting to conform to can specification time segment 1 (tseg1) 2tq to 15tq - time segment 2 (tseg2) 1tq to 8tq ipt of the can controller is 0tq. to conform to the can protocol specification, therefore, a length less or equal to phase segment 1 must be set here. this means that the length of time segment 1 minus 1tq is the settable upper limit of time segment 2. resynchronization jump width (sjw) 1tq to 4tq the length of time segment 1 minus 1tq or 4 tq, whichever is smaller. data bit time(dbt) phase segment 1 prop segment sync segment phase segment 2 time segment 1(tseg1) time segment 2 (tseg2) sample point (spt)
742 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-19 configuration of data bit time defi ned by can specification table 20-16 configuration of data bi t time defined by can specification note ipt: information processing time segment name settable range notes on setting to conform to can specification sync segment (synchronization segment) 1 this segment starts at the edge where the level changes from recessive to dominant when hardware synchronization is established. prop segment programmable to 1 to 8 or more this segment absorbs the delay of the output buffer, can bus, and input buffer. the length of this segment is set so that ack is returned before the start of phase segment 1. time of prop segment  (delay of output buffer) + 2 (delay of can bus) + (delay of input buffer) this segment compensates for an error of data bit time. the longer this segment, the wider the permissible range but the slower the communication speed. phase segment 1 programmable to 1 to 8 phase segment 2 phase segment 1 or ipt, whichever greater sjw programmable from 1tq to length of segment 1 or 4tq, whichever is smaller this width sets the upper limit of expansion or contraction of the phase segment during resynchronization. ph as e s egment 1 prop s egment s ync s egment ph as e s egment 2 sa mple point ( s pt) s jw d a t a b it time(dbt)
743 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (3) synchronizing data bit ? the receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. ? the transmitting node transmits data in synchronization with the bit timing of the transmitting node. (a) hardware synchronization this synchronization is established when the receiving node detects the start of frame in the interframe space. ? when a falling edge is detected on the bus, that tq means the sync segment and the next segment is the prop segment. in this case, synchronization is established regardless of sjw. figure 20-20 adjusting synchronization of data bit (b) resynchronization synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously). ? the phase error of the edge is given by the relative position of the detected edge and sync segment. 0: if the edge is within the sync segment positive: if the edge is before the sample point (phase error) negative: if the edge is after the sample point (phase error) if phase error is positive: phase segment 1 is lengthened by specified sjw. if phase error is negative: phase segment 2 is shortened by specified sjw. ? the sample point of the data of the receiving node moves relatively due to the ?discrepancy? in the baud rate between the transmitting node and receiving node. s t a rt of fr a me interfr a me s p a ce can bus bit timing ph as e s egment 1 prop s egment s ync s egment ph as e s egment 2
744 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-21 resynchronization 20.4 connection with target system the can module has to be connected to the can bus using an external transceiver. figure 20-22 connection to can bus can bus bit timing can bus bit timing ph as e s egment 1 prop s egment s ync s egment ph as e s egment 2 ph as e s egment 1 prop s egment s ync s egment ph as e s egment 2 sa mple point sa mple point if ph as e error i s neg a tive if ph as e error i s po s itive can module transceiver ctxdn crxdn canl canh
745 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.5 internal registers of can controller 20.5.1 can module register and message buffer addresses in this chapter all register and message buffer addresses are defined as address offsets to different base addresses. since all registers are accessed via the programmable peripheral area the bottom address is defined by the bpc register (refer to ?programmable peripheral i/o area? on page 133 or to ?programmable peripheral i/o area (ppa)? on page 296 ). the addresses given in the following tables are offsets to the programmable peripheral area base address pba. the recommended setting of pba is 8ffb h . this setting would define the programmable peripheral area base address pba = 03fe c000 h table 20-17 lists all base addresses used throughout this chapter. in the following respectively are used for the base address names for can channel n. table 20-17 can module base addresses base address name base address of address address for bpc =8ffb h c0rbaseaddr can0 registers pba + 000 h 03fe c000 h c0mbaseaddr can0 message buffers pba + 100 h 03fe c100 h c1rbaseaddr can1 registers pba + 600 h 03fe c600 h c1mbaseaddr can1 message buffers pba + 700 h 03fe c700 h c2rbaseaddr can2 registers pba + c00 h 03fe cc00 h c2mbaseaddr can2 message buffers pba + d00 h 03fe cd00 h
746 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.5.2 can controller configuration table 20-18 list of can controller registers item register name cann global registers cann global control register (cngmctrl) cann global clock selection register (cngmcs) cann global automatic block transmission control register (cngmabt) cann global automatic block transmission delay setting register (cngmabtd) cann module registers cann module mask 1 register (cnmask1l, cnmask1h) cann module mask 2 register (cnmask2l, cnmask2h) cann module mask3 register (cnmask3l, cnmask3h) cann module mask 4 registers (cnmask4l, cnmask4h) cann module control register (cnctrl) cann module last error information register (cnlec) cann module information register (cninfo) cann module error counter register (cnerc) cann module interrupt enable register (cnie) cann module interrupt status register (cnints) cann module bit rate prescaler register (cnbrp) cann module bit rate register (cnbtr) cann module last in-pointer register (cnlipt) cann module receive history list register (cnrgpt) cann module last out-pointer register (cnlopt) cann module transmit history list register (cntgpt) cann module time stamp register (cnts) cann message buffer registers cann message data byte 01 register m (cnmdata01m) cann message data byte 0 register m (cnmdata0m) cann message data byte 1 register m (cnmdata1m) cann message data byte 23 register m (cnmdata23m) cann message data byte 2 register m (cnmdata2m) cann message data byte 3 register m (cnmdata3m) cann message data byte 45 register m (cnmdata45m) cann message data byte 4 register m (cnmdata4m) cann message data byte 5 register m (cnmdata5m) cann message data byte 67 register m (cnmdata67m) cann message data byte 6 register m (cnmdata6m) cann message data byte 7 register m (cnmdata7m) cann message data length register m (cnmdlcm) cann message configuration register m (cnmconfm) cann message id register m (cnmidlm, cnmidhm) cann message control register m (cnmctrlm)
747 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.5.3 can registers overview (1) cann global and module registers the following table lists the address offsets to the cann register base address cnrbaseaddr. table 20-19 cann global and module registers address offset register name symbol r/w access after reset 1-bit 8-bit 16-bit 000 h cann global control register cngmctrl r/w ? ?  0000 h 002 h cann global clock selection register cngmcs  0f h 006 h cann global automatic block transmission register cngmabt ? ?  0000 h 008 h cann global automatic block transmission delay register cngmabtd ?  ?00 h 040 h cann module mask 1 register cnmask1l ? ?  undefined 042 h cnmask1h ? ?  undefined 044 h cann module mask 2 register cnmask2l ? ?  undefined 046 h cnmask2h ? ?  undefined 048 h cann module mask 3 register cnmask3l ? ?  undefined 04a h cnmask3h ? ?  undefined 04c h cann module mask 4 register cnmask4l ? ?  undefined 04e h cnmask4h ? ?  undefined 050 h cann module control register cnctrl ? ?  0000 h 052 h cann module last error code register cnlec ?  ?00 h 053 h cann module information register cninfo r ?  ?00 h 054 h cann module error counter register cnerc ? ?  0000v 056 h cann module interrupt enable register cnie r/w ? ?  0000 h 058 h cann module interrupt status register cnints ? ?  0000 h 05a h cann module bit-rate prescaler register cnbrp ?  ?ff h 05c h cann module bit-rate register cnbtr ? ?  370f h 05e h cann module last in-pointer register cnlipt r ?  ? undefined 060 h cann module receive history list register cnrgpt r/w ? ?  xx02 h 062 h cann module last out-pointer register cnlopt r ?  ? undefined 064 h cann module transmit history list register cntgpt r/w ? ?  xx02 h 066 h cann module time stamp register cnts ? ?  0000 h
748 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (2) cann message buffer registers the addresses in the following table denote the address offsets to the cann message buffer base address: cnmbaseaddr. example can0, message buffer register m = 14 = e h , byte 6 c0mdata614 has the address e h x 20 h + 6 h + c0mbaseaddr note the message buffer register number m in the register symbols has 2 digits, for example, comdata01m = comdata0100 for m = 0. table 20-20 cann message buffer registers address offset register name symbol r/w access after reset 1-bit 8-bit 16-bit mx20 h + 0 h cann message data byte 01 register m cnmdata01m r/w ? ?  undefined mx20 h + 0 h cann message data byte 0 register m cnmdata0m ?  ? undefined mx20 h + 1 h cann message data byte 1 register m cnmdata1m ?  ? undefined mx20 h + 2 h cann message data byte 23 register m cnmdata23m ? ?  undefined mx20 h + 2 h cann message data byte 2 register m cnmdata2m ?  ? undefined mx20 h + 3 h cann message data byte 3 register m cnmdata3m ?  ? undefined mx20 h + 4 h cann message data byte 45 register m cnmdata45m ? ?  undefined mx20 h + 4 h cann message data byte 4 register m cnmdata4m ?  ? undefined mx20 h + 5 h cann message data byte 5 register m cnmdata5m ?  ? undefined mx20 h + 6 h cann message data byte 67 register m cnmdata67m ? ?  undefined mx20 h + 6 h cann message data byte 6 register m cnmdata6m ?  ? undefined mx20 h + 7 h cann message data byte 7 register m cnmdata7m ?  ? undefined mx20 h + 8 h cann message data length register m cnmdlcm ?  ? 0000 xxxx b mx20 h + 9 h cann message configuration register m cnmconfm ?  ? undefined mx20 h + a h cann message identifier register m cnmidlm ? ?  undefined mx20 h + c h cnmidhm ? ?  undefined mx20 h + e h cann message control register m cnmctrlm ? ?  0x00 0000 0000 0000 b
749 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.5.4 register bit configuration table 20-21 can global register bit configuration address offset a a) base address: symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 00 h cngmctrl (w)0000000clear gom 01 h 000000set efsdset gom 00 h cngmctrl (r)000000efsdgom 01 h mbon000000 0 02 h cngmcs 0 0 0 0 ccp3 ccp2 ccp1 ccp0 06 h cngmabt (w)0000000clear abttrg 07 h 000000set abtclr set abttrg 06 h cngmabt (r)000000abtclrabttrg 07 h 0000000 0 08 h cngmabtd 0 0 0 0 abtd3 abtd2 abtd1 abtd0 table 20-22 can module register bit configuration (1/2) address offset a symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 40 h cnmask1l cmid7 to cmid0 41 h cmid15 to cmid8 42 h cnmask1h cmid23 to cmid16 43 h 0 0 0 cmid28 to cmid24 44 h cnmask2l cmid7 to cmid0 45 h cmid15 to cmid8 46 h cnmask2h cmid23 to cmid16 47 h 0 0 0 cmid28 to cmid24 48 h cnmask3l cmid7 to cmid0 49 h cmid15 to cmid8 4a h cnmask3h cmid23 to cmid16 4b h 0 0 0 cmid28 to cmid24 4c h cnmask4l cmid7 to cmid0 4d h cmid15 to cmid8 4e h cnmask4h cmid23 to cmid16 4f h 0 0 0 cmid28 to cmid24 50 h cnctrl (w) 0 clear al clear valid clear psmode1 clear psmode0 clear opmode2 clear opmode1 clear opmode0 51 h set ccerc set al 0set psmode1 set psmode0 set opmode2 set opmode1 set opmode0 50 h cnctrl (r) ccerc al valid ps mode1 ps mode0 op mode2 op mode1 op mode0 51 h 000 0 0 0rstattstat
750 chapter 20 can controller (can) user?s manual u17566ee5v1um00 52 h cnlec (w)00000000 52 h cnlec (r) 0 0 0 0 0 lec2 lec1 lec0 53 h cninfo 0 0 0 boff tecs1 tecs0 recs1 recs0 54 h cnerc tec7 to tec0 55 h rec7 to rec0 56 h cnie (w) 0 0 clear cie5 clear cie4 clear cie3 clear cie2 clear cie1 clear cie0 57 h 0 0 set cie5 set cie4 set cie3 set cie2 set cie1 set cie0 56 h cnie (r) 0 0 cie5 cie4 cie3 cie2 cie1 cie0 57 h 00000000 58 h cnints (w) 0 0 clear cints5 clear cints4 clear cints3 clear cints2 clear cints1 clear cints0 59 h 00000000 58 h cnints (r) 0 0 cints5 cints4 cints3 cints2 cints1 cints0 59 h 00000000 5a h cnbrp tqprs7 to tqprs0 5c h cnbtr 0 0 0 0 tseg13 to tseg10 5d h 0 0 sjw1, sjw0 0 tseg22 to tseg20 5e h cnlipt lipt7 to lipt0 60 h cnrgpt (w) 0 0 0 0 0 0 0 clear rovf 61 h 00000000 60 h cnrgpt (r) 0 0 0 0 0 0 rhpm rovf 61 h rgpt7 to rgpt0 f62 h cnlopt lopt7 to lopt0 64 h cntgpt (w)0000000clear tovf 65 h 00000000 64 h cntgpt (r) 0 0 0 0 0 0 thpm tovf 65 h tgpt7 to tgpt0 66 h cnts (w) 0 0 0 0 0 clear tslock clear tssel clear tsen 67 h 000 0 0set tslock set tssel set tsen 66 h cnts (r) 0 0 0 0 0 tslock tssel tsen 67 h 00000000 68 h to ff h - access prohibited (reserved for future use) a) base address: table 20-22 can module register bit configuration (2/2) address offset a symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8
751 can controller (can) chapter 20 user?s manual u17566ee5v1um00 note for calculation of the complete message buffer register addresses refer to ?can registers overview? on page 747 . table 20-23 message buffer register bit configuration address offset a a) base address: symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 0 h cnmdata01m message data (byte 0) 1 h message data (byte 1) 0 h cnmdata0m message data (byte 0) 1 h cnmdata1m message data (byte 1) 2 h cnmdata23m message data (byte 2) 3 h message data (byte 3) 2 h cnmdata2m message data (byte 2) 3 h cnmdata3m message data (byte 3) 4h cnmdata45m message data (byte 4) 5 h message data (byte 5) 4 h cnmdata4m message data (byte 4) 5 h cnmdata5m message data (byte 5) 6 h cnmdata67m message data (byte 6) 7 h message data (byte 7) 6 h cnmdata6m message data (byte 6) 7 h cnmdata7m message data (byte 7) 8 h cnmdlcm 0 mdlc3 mdlc2 mdlc1 mdlc0 9 h cnmconfm ows rtr mt2 mt1 mt0 0 0 ma0 a h cnmidlm id7 id6 id5 id4 id3 id2 id1 id0 b h id15 id14 id13 id12 id11 id10 id9 id8 c h cnmidhm id23 id22 id21 id20 id19 id18 id17 id16 d h ide 0 0 id28 id27 id26 id25 id24 e h cnmctrlm (w) 000clear mow clear ie clear dn clear trq clear rdy f h 0000set ie0set trqset rdy e h cnmctrlm (r) 0 0 0 mow ie dn trq rdy f h 00muc00000
752 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.6 bit set/clear function the can control registers include registers whose bits can be set or cleared via the cpu and via the can interface. an operation error occurs if the following registers are written directly. do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values. ? cann global control register (cngmctrl) ? cann global automatic block transmission control register (cngmabt) ? cann module control register (cnctrl) ? cann module interrupt enable register (cnie) ? cann module interrupt status register (cnints) ? cann module receive history list register (cnrgpt) ? cann module transmit history list register (cntgpt) ? cann module time stamp register (cnts) ? cann message control register (cnmctrlm) all the 16 bits in the above registers can be read via the usual method. use the procedure described in figure 20-23 below to set or clear the lower 8 bits in these registers. setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to the bit status after set/clear operation is specified in figure 20-26 ). figure 20-23 shows how the values of set bits or clear bits relate to set/clear/no change operations in the corresponding register.
753 can controller (can) chapter 20 user?s manual u17566ee5v1um00 figure 20-23 example of bit setting/clearing operations (1) bit status after bit setting/clearing operations 0000000011010001 0000101111011000 set00001011 0000000000000011 clear 11011000 set no change clear bit status register?s current value write value register?s value after write operation clear clear no change no change set 1514131211109876543210 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set 0 ... 7 clear 0 ... 7 status of bit n after bit set/clear operation 0 0 no change 010 101 1 1 no change
754 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.7 control registers (1) cngmctrl - cann global control register the cngmctrl register is used to control the operation of the can module. access this register can be read/written in 16-bit units. address + 000 h initial value 0000 h . the register is initialized by any reset. (a) cngmctrl read caution 1. while the mbon bit is cleared (to 0), software access to the message buffers (cnmdata0m, cnmdata1m, cnmdata01m, cnmdata2m, cnmdata3m, cnmdata23m, cnmdata4m, cnmdata5m, cnmdata45m, cnmdata6m, cnmdata7m, cnmdata67m, cnmdlcm, cnmconfm, cnmidlm, cnmidhm, and cnmctrlm), or registers related to transmit history or receive history (cnlopt, cntgpt, cnlipt, and cnrgpt) is disabled. 2. this bit is read-only. even if 1 is written to the mbon bit while it is 0, the value of the mbon bit does not change, and access to the message buffer registers, or registers related to transmit history or receive history remains disabled. note the mbon bit is cleared (to 0) when the can module enters can sleep mode/ can stop mode, or when the gom bit is cleared (to 0). the mbon bit is set (to 1) when the can sleep mode/can stop mode is released, or when the gom bit is set (to 1). caution 1. to request forced shut down, the gom bit must be cleared to 0 in a subsequent, immediately following access after the efsd bit has been set to 1. if access to another register (including reading the cngmctrl register) is executed without clearing the gom bit immediately after the 15 14 13 12 11 10 9 8 mbon0000000 76543210 000000efsdgom mbon bit enabling access to message buffer register, transmit/receive history registers 0 write access and read access to the message buffer register and the transmit/receive history list registers is disabled. 1 write access and read access to the message buffer register and the transmit/receive history list registers is enabled. efsd bit enabling forced shut down 0 forced shut down by gom bit = 0 disabled. 1 forced shut down by gom bit = 0 enabled.
755 can controller (can) chapter 20 user?s manual u17566ee5v1um00 efsd bit has been set to 1, the efsd bit is forcibly cleared to 0, and the forced shut down request is invalid. 2. efsd only works, if no continuous dma transfer is performed. caution the gom can be cleared only in the initialization mode or immediately after efsd bit is set (to 1). (b) cngmctrl write caution set the gom bit and efsd bit always separately. gom global operation mode bit 0 can module is disabled from operating. 1 can module is enabled to operate. 15 14 13 12 11 10 9 8 000000 set efsd set gom 76543210 0000000 clear gom set efsd efsd bit setting 0 no change in efsd bit. 1 efsd bit set to 1. set gom clear gom gom bit setting 01 gom bit cleared to 0. 10 gom bit set to 1. other than above no change in gom bit.
756 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (2) cngmcs - cann global clock selection register the cngmcs register is used to select the can module system clock. access this register can be read/written in 8-bit units. address + 002 h initial value 0f h . the register is initialized by any reset. note f can = clock supplied to can 76543210 0 0 0 0 ccp3 ccp2 ccp1 ccp0 ccp3 ccp2 ccp1 ccp1 can module system clock (f canmod ) 0000f can /1 0001f can /2 0010f can /3 0011f can /4 0100f can /5 0101f can /6 0110f can / 7 0111f can /8 1000f can /9 1001f can /10 1010f can /11 1011f can /12 1100f can /13 1101f can /14 1110f can /15 1111f can /16 (default value)
757 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (3) cngmabt - cann global automatic block transmission control register the cngmabt register is used to control the automatic block transmission (abt) operation. access this register can be read/written in 16-bit units. address + 006 h initial value 0000 h . the register is initialized by any reset. (a) cngmabt read note 1. set the abtclr bit to 1 while the abttrg bit is cleared to 0. the operation is not guaranteed if the abtclr bit is set to 1 while the abttrg bit is set to 1. 2. when the automatic block transmission engine is cleared by setting the abtclr bit to 1, the abtclr bit is automatically cleared to 0 as soon as the requested clearing processing is complete. caution 1. do not set the abttrg bit (1) in the initialization mode. if the abttrg bit is set in the initialization mode, the operation is not guaranteed after the can module has entered the normal operation mode with abt. 2. do not set the abttrg bit (1) while the cnctrl.tstat bit is set (1). confirm tstat = 0 directly in advance before setting abttrg bit. 15 14 13 12 11 10 9 8 00000000 76543210 000000abtclrabttrg abtclr automatic block transmission engine clear status bit 0 clearing the automatic transmission engine is completed. 1 the automatic transmission engine is being cleared. abttrg automatic block transmission status bit 0 automatic block transmission is stopped. 1 automatic block transmission is under execution.
758 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (b) cngmabt write caution before changing the normal operation mode with abt to the initialization mode, be sure to set the cngmabt register to the default value (0000 h ) and confirm the cngmabt register is surely initialized to the default value (0000 h ). 15 14 13 12 11 10 9 8 000000 set abtclr set abttrg 76543210 0000000 clear abttrg set abtclr automatic block transmission engine clear request bit 0 the automatic block transmission engine is in idle status or under operation. 1 request to clear the automatic block transmission engine. after the automatic block transmission engine has been cleared, automatic block transmission is started from message buffer 0 by setting the abttrg bit to 1. set abttrg clear abttrg automatic block transmission start bit 0 1 request to stop automatic block transmission. 1 0 request to start automatic block transmission. other than above no change in abttrg bit.
759 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (4) cngmabtd - cann global automatic block transmission delay register the cngmabtd register is used to set the interval at which the data of the message buffer assigned to abt is to be transmitted in the normal operation mode with abt. access this register can be read/written in 8-bit units. address + 008 h initial value 00 h . the register is initialized by any reset. caution 1. do not change the contents of the cngmabtd register while the abttrg bit is set to 1. 2. the timing at which the abt message is actually transmitted onto the can bus differs depending on the status of transmission from the other station or how a request to transmit a message other than an abt message (message buffers 8 to 31) is made. 76543210 0 0 0 0 abtd3 abtd2 abtd1 abtd0 abtd3 abtd2 abtd1 abtd0 data frame interval during automatic block transmission in dbt a a) unit: data bit time (dbt) 00000 dbt (default value) 00012 5 dbt 00102 6 dbt 00112 7 dbt 01002 8 dbt 01012 9 dbt 01102 10 dbt 01112 11 dbt 10002 12 dbt other than above setting prohibited
760 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (5) cnmaskal, cnmaskah - cann module mask control register (a = 1 to 4) the cnmaskal and cnmaskah registers are used to extend the number of receivable messages into the same message buffer by masking part of the identifier (id) comparison of a message and invalidating the id of the masked part. (a) cann module mask 1 register (cnmask1l, cnmask1h) access these registers can be read/written in 16-bit units. address cnmask1l: + 040 h cnmask1h: + 042 h initial value undefined. (b) cann module mask 2 register (cnmask2l, cnmask2h) access these registers can be read/written in 16-bit units. address cnmask2l: + 044 h cnmask2h: + 046 h initial value undefined. cnmask1l 15 14 13 12 11 10 9 8 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 76543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 cnmask1h 15 14 13 12 11 10 9 8 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 76543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 cnmask2l 15 14 13 12 11 10 9 8 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 76543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 cnmask2h 15 14 13 12 11 10 9 8 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 76543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16
761 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (c) cann module mask 3 register (cnmask3l, cnmask3h) access these registers can be read/written in 16-bit units. address cnmask3l: + 048 h cnmask3h: + 04a h initial value undefined. (d) cann module mask 4 register (cnmask4l, cnmask4h) access these registers can be read/written in 16-bit units. address cnmask4l: + 04c h cnmask4h: + 04e h initial value undefined. note masking is always defined by an id length of 29 bits. if a mask is assigned to a message with a standard id, the cmid17 to cmid0 bits are ignored. therefore, only the cmid28 to cmid18 bits of the received id are masked. the same mask can be used for both the standard and extended ids. cnmask3l 15 14 13 12 11 10 9 8 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 76543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 cnmask3h 15 14 13 12 11 10 9 8 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 76543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 cnmask4l 15 14 13 12 11 10 9 8 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 76543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 cnmask4h 15 14 13 12 11 10 9 8 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 76543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 cmid28 to cmid0 mask pattern setting of id bit 0 the id bits of the message buffer set by the cmid28 to cmid0 bits are compared with the id bits of the received message frame. 1 the id bits of the message buffer set by the cmid28 to cmid0 bits are not compared with the id bits of the received message frame (they are masked).
762 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (6) cnctrl - cann module control register the cnctrl register is used to control the operation mode of the can module. access this register can be read/written in 16-bit units. address + 050 h initial value 0000 h . the register is initialized by any reset. (a) cnctrl read note 1. the rstat bit is set to 1 under the following conditions (timing) ? the sof bit of a receive frame is detected ? on occurrence of arbitration loss during a transmit frame 2. the rstat bit is cleared to 0 under the following conditions (timing) ? when a recessive level is detected at the second bit of the interframe space ? on transition to the initialization mode at the first bit of the interframe space note 1. the tstat bit is set to 1 under the following conditions (timing) ? the sof bit of a transmit frame is detected 2. the tstat bit is cleared to 0 under the following conditions (timing) ? during transition to bus-off state ? on occurrence of arbitration loss in transmit frame ? on detection of recessive level at the second bit of the interframe space ? on transition to the initialization mode at the first bit of the interframe space 15 14 13 12 11 10 9 8 000000rstattstat 76543210 ccerc al valid psmode1 psmode0 opmode2 opmode1 opmode0 rstat reception status bit 0 reception is stopped. 1 reception is in progress. tstat transmission status bit 0 transmission is stopped. 1 transmission is in progress.
763 can controller (can) chapter 20 user?s manual u17566ee5v1um00 note 1. the ccerc bit is used to clear the cnerc and cninfo registers for re- initialization or forced recovery from the bus-off state. this bit can be set to 1 only in the initialization mode. 2. when the cnerc and cninfo registers have been cleared, the ccerc bit is also cleared to 0 automatically. 3. the ccerc bit can be set to 1 at the same time as a request to change the initialization mode to an operation mode is made. 4. the ccerc bit is read-only in the can sleep mode or can stop mode. 5. the receive data may be corrupted in case of setting the ccerc bit to (1) immediately after entering the init mode from self-test mode. note the al bit is valid only in the single-shot mode. note 1. detection of a valid receive message frame is not dependent upon storage in the receive message buffer (data frame) or transmit message buffer (remote frame). 2. clear the valid bit (0) before changing the initialization mode to an operation mode. 3. if only two can nodes are connected to the can bus with one transmitting a message frame in the normal mode and the other in the receive-only mode, the valid bit is not set to 1 before the transmitting node enters the error passive state, because in receive-only mode no acknowledge is generated. 4. to clear the valid bit, set the clear valid bit to 1 first and confirm that the valid bit is cleared. if it is not cleared, perform clearing processing again. ccerc error counter clear bit 0 the cnerc and cninfo registers are not cleared in the initialization mode. 1 the cnerc and cninfo registers are cleared in the initialization mode. al bit to set operation in case of arbitration loss 0 re-transmission is not executed in case of an arbitration loss in the single-shot mode. 1 re-transmission is executed in case of an arbitration loss in the single- shot mode. valid valid receive message frame detection bit 0 a valid message frame has not been received since the valid bit was last cleared to 0. 1 a valid message frame has been received since the valid bit was last cleared to 0.
764 chapter 20 can controller (can) user?s manual u17566ee5v1um00 caution 1. transition to and from the can stop mode must be made via can sleep mode. a request for direct transition to and from the can stop mode is ignored. 2. the mbon flag of cngmctrl must be checked after releasing a power save mode, prior to access the message buffers again. 3. can sleep mode requests are kept pending, until cancelled by software or entered on appropriate bus condition (bus idle). software can check the actual status by reading psmode. caution transit to initialization mode or power saving modes may take some time. be sure to verify the success of mode change by reading the values, before proceeding. note the opmode0 to opmode2 bits are read-only in the can sleep mode or can stop mode. psmode1 psmode0 power save mode 0 0 no power save mode is selected. 0 1 can sleep mode 1 0 setting prohibited 1 1 can stop mode opmode2 opmode1 opmode0 operation mode 000 no operation mode is selected (can module is in the initialization mode). 0 0 1 normal operation mode 010 normal operation mode with automatic block transmission function (normal operation mode with abt) 0 1 1 receive-only mode 1 0 0 single-shot mode 101self-test mode other than above setting prohibited
765 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (b) cnctrl write 15 14 13 12 11 10 9 8 set ccerc set al 0 set psmode1 set psmode0 set opmode2 set opmode1 set opmode0 76543210 0 clear al clear valid clear psmode1 clear psmode0 clear opmode2 clear opmode1 clear opmode0 set ccerc setting of ccerc bit 1 ccerc bit is set to 1. other than above ccerc bit is not changed. set al clear al setting of al bit 0 1 al bit is cleared to 0. 1 0 al bit is set to 1. other than above al bit is not changed. clear valid setting of valid bit 0 valid bit is not changed. 1 valid bit is cleared to 0. set psmode0 clear psmode0 setting of psmode0 bit 0 1 psmode0 bit is cleared to 0. 1 0 psmode0 bit is set to 1. other than above psmode0 bit is not changed. set psmode1 clear psmode1 setting of psmode1 bit 0 1 psmode1 bit is cleared to 0. 1 0 psmode1 bit is set to 1. other than above psmode1 bit is not changed. set opmode0 clear opmode0 setting of opmode0 bit 0 1 opmode0 bit is cleared to 0. 1 0 opmode0 bit is set to 1. other than above opmode0 bit is not changed.
766 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (7) cnlec - cann module last error information register the cnlec register provides the error information of the can protocol. access this register can be read/written in 8-bit units. address + 052 h initial value 00 h . the register is initialized by any reset. note 1. the contents of the cnlec register are not cleared when the can module changes from an operation mode to the initialization mode. 2. if an attempt is made to write a value other than 00 h to the cnlec register by software, the access is ignored. set opmode1 clear opmode1 setting of opmode1 bit 0 1 opmode1 bit is cleared to 0. 1 0 opmode1 bit is set to 1. other than above opmode1 bit is not changed. set opmode2 clear opmode2 setting of opmode2 bit 0 1 opmode2 bit is cleared to 0. 1 0 opmode2 bit is set to 1. other than above opmode2 bit is not changed. 76543210 0 0 0 0 0 lec2 lec1 lec0 lec2 lec1 lec0 last can protocol error information 000no error 001stuff error 010form error 011ack error 100 bit error. (the can module tried to transmit a recessive-level bit as part of a transmit message (except the arbitration field), but the value on the can bus is a dominant-level bit.) 101 bit error. (the can module tried to transmit a dominant-level bit as part of a transmit message, ack bit, error frame, or overload frame, but the value on the can bus is a recessive- level bit.) 1 1 0 crc error 111undefined
767 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (8) cninfo - cann module information register the cninfo register indicates the status of the can module. access this register is read-only in 8-bit units. address + 053 h initial value 00 h . the register is initialized by any reset. 76543210 0 0 0 boff tecs1 tecs0 recs1 recs0 boff bus-off state bit 0 not bus-off state (transmit error counter  255). (the value of the transmit counter is less than 256.) 1 bus-off state (transmit error counter > 255). (the value of the transmit counter is 256 or more.) tecs1 tecs0 transmission error counter status bit 00 the value of the transmission error counter is less than that of the warning level (< 96). 01 the value of the transmission error counter is in the range of the warning level (96 to 127). 1 0 undefined 11 the value of the transmission error counter is in the range of the error passive or bus-off status (  128). recs1 recs0 reception error counter status bit 00 the value of the reception error counter is less than that of the warning level (< 96). 01 the value of the reception error counter is in the range of the warning level (96 to 127). 1 0 undefined 11 the value of the reception error counter is in the error passive range (  128).
768 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (9) cnerc - cann module error counter register the cnerc register indicates the count value of the transmission/reception error counter. access this register is read-only in 16-bit units. address + 054 h initial value 0000 h . the register is initialized by any reset. note rec6 to rec0 of the reception error counter are invalid in the reception error passive state (cninfo.recs[1:0] = 11 b ). note the tec7 to tec0 bits of the transmission error counter are invalid in the bus- off state (cninfo.boff = 1). 15 14 13 12 11 10 9 8 reps rec6 rec5 rec4 rec3 rec2 rec1 rec0 76543210 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 reps reception error passive status bit 0 the reception error counter is not in the error passive range (< 128) 1 the reception error counter is in the error passive range (  128) rec6 to rec0 reception error counter bit 0 to 127 number of reception errors. these bits reflect the status of the reception error counter. the number of errors is defined by the can protocol. tec7 to tec0 transmission error counter bit 0 to 255 number of transmission errors. these bits reflect the status of the transmission error counter. the number of errors is defined by the can protocol.
769 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (10) cnie - cann module interrupt enable register the cnie register is used to enable or disable the interrupts of the can module. access this register can be read/written in 16-bit units. address + 056 h initial value 0000 h . the register is initialized by any reset. (a) cnie read (b) cnie write 15 14 13 12 11 10 9 8 00000000 76543210 0 0 cie5 cie4 cie3 cie2 cie1 cie0 cie5 to cie0 can module interrupt enable bit 0 output of the interrupt corresponding to interrupt status register cintsx is disabled. 1 output of the interrupt corresponding to interrupt status register cintsx is enabled. 15 14 13 12 11 10 9 8 00 set cie5 set cie4 set cie3 set cie2 set cie1 set cie0 76543210 00 clear cie5 clear cie4 clear cie3 clear cie2 clear cie1 clear cie0 set cie5 clear cie5 setting of cie5 bit 0 1 cie5 bit is cleared to 0. 1 0 cie5 bit is set to 1. other than above cie5 bit is not changed. set cie4 clear cie4 setting of cie4 bit 0 1 cie4 bit is cleared to 0. 1 0 cie4 bit is set to 1. other than above cie4 bit is not changed. set cie3 clear cie3 setting of cie3 bit 0 1 cie3 bit is cleared to 0. 1 0 cie3 bit is set to 1. other than above cie3 bit is not changed.
770 chapter 20 can controller (can) user?s manual u17566ee5v1um00 set cie2 clear cie2 setting of cie2 bit 0 1 cie2 bit is cleared to 0. 1 0 cie2 bit is set to 1. other than above cie2 bit is not changed. set cie1 clear cie1 setting of cie1 bit 0 1 cie1 bit is cleared to 0. 1 0 cie1 bit is set to 1. other than above cie1 bit is not changed. set cie0 clear cie0 setting of cie0 bit 0 1 cie0 bit is cleared to 0. 1 0 cie0 bit is set to 1. other than above cie0 bit is not changed.
771 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (11) cnints - cann module interrupt status register the cnints register indicates the interrupt status of the can module. access this register can be read/written in 16-bit units. address + 058 h initial value 0000 h . the register is initialized by any reset. (a) cnints read (b) cnints write caution please clear the status bit of this register with software when the confirmation of each status is necessary in the interrupt processing, because these bits are not cleared automatically. 15 14 13 12 11 10 9 8 00000000 76543210 0 0 cints5 cints4 cints3 cints2 cints1 cints0 cints5 to cints0 can interrupt status bit 0 no related interrupt source event is pending. 1 a related interrupt source event is pending. interrupt status bit related interrupt source event cints5 wakeup interrupt from can sleep mode a a) the cints5 bit is set only when the can module is woken up from the can sleep mode by a can bus operation. the cints5 bit is not set when the can sleep mode has been released by software. cints4 arbitration loss interrupt cints3 can protocol error interrupt cints2 can error status interrupt cints1 interrupt on completion of reception of valid message frame to message buffer m cints0 interrupt on normal completion of transmission of message frame from message buffer m 15 14 13 12 11 10 9 8 00000000 76543210 00 clear cints5 clear cints4 clear cints3 clear cints2 clear cints1 clear cints0 clear cints5 to cints0 setting of cints5 to cints0 bits 0 cints5 to cints0 bits are not changed. 1 cints5 to cints0 bits are cleared to 0.
772 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (12) cnbrp - cann module bit rate prescaler register the cnbrp register is used to select the can protocol layer basic system clock (f tq ). the communication baud rate is set to the cnbtr register. access this register can be read/written in 8-bit units. address + 05a h initial value ff h . the register is initialized by any reset. figure 20-24 can module clock note f can : clock supplied to can f canmod : can module system clock f tq : can protocol layer basic system clock caution the cnbrp register can be write-accessed only in the initialization mode. 76543210 tqprs7 tqprs6 tqprs5 tqprs4 tqprs3 tqprs2 tqprs1 tqprs0 tqprs7 to tqprs0 can protocol layer base system clock (f tq ) 0f canmod /1 1f canmod /2 nf canmod /(n+1) : : 255 f canmod /256 (default value) ccp 3 ccp2 prescaler cann module bit-rate prescaler register (cnbrp) cann module clock selection register (cngmcs) baud rate generator cann bit-rate register (cnbtr) ccp1 ccp0 tqprs0 f can f canmod f tq 0 0 0 0 tqprs1 tqprs2 tqprs3 tqprs4 tqprs5 tqprs6 tqprs7
773 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (13) cnbtr - cann module bit rate register the cnbtr register is used to control the data bit time of the communication baud rate. access this register can be read/written in 16-bit units. address + 05c h initial value 370f h . the register is initialized by any reset. figure 20-25 data bit time 15 14 13 12 11 10 9 8 0 0 sjw1 sjw0 0 tseg22 tseg21 tseg20 76543210 0 0 0 0 tseg13 tseg12 tseg11 tseg10 data bit time (dbt) time segment 1 (tseg1) phase segment 2 phase segment 1 sample point (spt) prop segment sync segment time segment 2 (tseg2) sjw1 sjw0 length of synchronization jump width 001t q 012t q 103t q 114t q (default value) tseg22 tseg21 tseg20 length of time segment 2 0001t q 0012t q 0103t q 0114t q 1005t q 1016t q 1107t q 1118t q (default value)
774 chapter 20 can controller (can) user?s manual u17566ee5v1um00 note t q = 1/f tq (f tq : can protocol layer basic system clock) (14) cnlipt - cann module last in-pointer register the cnlipt register indicates the number of the message buffer in which a data frame or a remote frame was last stored. access this register is read-only in 8-bit units. address + 05e h initial value undefined. note the read value of the cnlipt register is undefined if a data frame or a remote frame has never been stored in the message buffer. if the rhpm bit of the cnrgpt register is set to 1 after the can module has changed from the initialization mode to an operation mode, therefore, the read value of the cnlipt register is undefined. tseg13 tseg12 tseg11 tseg10 length of time segment 1 0 0 0 0 setting prohibited 00012t q a a) this setting must not be made when the cnbrp register = 00 h 00103t q a 00114t q 01005t q 01016t q 01107t q 01118t q 10009t q 100110t q 101011t q 101112t q 110013t q 110114t q 111015t q 111116t q (default value) 76543210 lipt7 lipt6 lipt5 lipt4 lipt3 lipt2 lipt1 lipt0 lipt7 to lipt0 last in-pointer register (cnlipt) 0 to 31 when the cnlipt register is read, the contents of the element indexed by the last in-pointer (lipt) of the receive history list are read. these contents indicate the number of the message buffer in which a data frame or a remote frame was last stored.
775 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (15) cnrgpt - cann module receive history list register the cnrgpt register is used to read the receive history list. access this register can be read/written in 16-bit units. address + 060 h initial value xx02 h . the register is initialized by any reset. (a) cnrgpt read 15 14 13 12 11 10 9 8 rgpt7 rgpt6 rgpt5 rgpt4 rgpt3 rgpt2 rgpt1 rgpt0 76543210 000000rhpmrovf rgpt7 to rgpt0 receive history list read pointer 0 to 31 when the cnrgpt register is read, the contents of the element indexed by the receive history list get pointer (rgpt) of the receive history list are read. these contents indicate the number of the message buffer in which a data frame or a remote frame has been stored. rhpm a a) the read value of the rgpt0 to rgpt7 bits is invalid when the rhpm bit = 1. receive history list pointer match 0 the receive history list has at least one message buffer number that has not been read. 1 the receive history list has no message buffer numbers that have not been read. rovf a a) if rovf is set, rhpm is no longer cleared on message storage, but rhpm is still set, if all entries of cnrgpt are read by software. receive history list overflow bit 0 all the message buffer numbers that have not been read are preserved. all the numbers of the message buffers in which a new data frame or remote frame has been received and stored are recorded to the receive history list (the receive history list has a vacant element). 1 at least 23 entries have been stored since the host processor has serviced the rhl last time (i.e. read cnrgpt). the first 22 entries are sequentially stored while the last entry can have been overwritten whenever newly received message is stored because all buffer numbers are stored at position lipt-1 when rovf bit is set. thus the sequence of receptions can not be recovered completely now.
776 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (b) cnrgpt write (16) cnlopt - cann module last out-pointer register the cnlopt register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last. access this register is read-only in 8-bit units. address + 062 h initial value undefined note the value read from the cnlopt register is undefined if a data frame or remote frame has never been transmitted from a message buffer. if the cntgpt.thpm bit is set to 1 after the can module has changed from the initialization mode to an operation mode, therefore, the read value of the cnlopt register is undefined. 15 14 13 12 11 10 9 8 00000000 76543210 0000000 clear rovf clear rovf setting of rovf bit 0 rovf bit is not changed. 1 rovf bit is cleared to 0. 76543210 lopt7 lopt6 lopt5 lopt4 lopt3 lopt2 lopt1 lopt0 lopt7 to lopt0 last out-pointer of transmit history list (lopt) 0 to 31 when the cnlopt register is read, the contents of the element indexed by the last out-pointer (lopt) of the receive history list are read. these contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last.
777 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (17) cntgpt - cann module transmit history list register the cntgpt register is used to read the transmit history list. access this register can be read/written in 16-bit units. address + 064 h initial value xx02 h . the register is initialized by any reset. (a) cntgpt read note transmission from message buffers 0 to 7 is not recorded to the transmit history list in the normal operation mode with abt. 15 14 13 12 11 10 9 8 tgpt7 tgpt6 tgpt5 tgpt4 tgpt3 tgpt2 tgpt1 tgpt0 76543210 000000thpmtovf tgpt7 to tgpt0 transmit history list read pointer 0 to 31 when the cntgpt register is read, the contents of the element indexed by the read pointer (tgpt) of the transmit history list are read. these contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. thpm a a) the read value of the tgpt0 to tgpt7 bits is invalid when the thpm bit = 1. transmit history pointer match 0 the transmit history list has at least one message buffer number that has not been read. 1 the transmit history list has no message buffer numbers that have not been read. tovf a a) if tovf is set, thpm is no longer cleared on message transmission, but thpm is still set, if all entries of cntgpt are read by software. transmit history list overflow bit 0 all the message buffer numbers that have not been read are preserved. all the numbers of the message buffers to which a new data frame or remote frame has been transmitted are recorded to the transmit history list (the transmit history list has a vacant element). 1 at least 7 entries have been stored since the host processor has serviced the thl last time (i.e. read cntgpt). the first 6 entries are sequentially stored while the last entry can have been overwritten whenever a message is newly transmitted because all buffer numbers are stored at position lopt-1 when tovf bit is set. thus the sequence of transmissions can not be recovered completely now.
778 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (b) cntgpt write 15 14 13 12 11 10 9 8 00000000 76543210 0000000 clear tovf clear tovf setting of tovf bit 0 tovf bit is not changed. 1 tovf bit is cleared to 0.
779 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (18) cnts - cann module time stamp register the cnts register is used to control the time stamp function. access this register can be read/written in 16-bit units. address + 066 h initial value 0000 h . the register is initialized by any reset. (a) cnts read note the lock function of the time stamp function must not be used when the can module is in the normal operation mode with abt. 15 14 13 12 11 10 9 8 00000000 76543210 0 0 0 0 0 tslock tssel tsen tslock time stamp lock function enable bit 0 time stamp lock function stopped. the tsout signal is toggled each time the selected time stamp capture event occurs. 1 time stamp lock function enabled. the tsout signal is toggled each time the selected time stamp capture event occurs. however, the tsout output signal is locked when a data frame has been correctly received to message buffer 0 a . a) the tsen bit is automatically cleared to 0. tssel time stamp capture event selection bit 0 the time capture event is sof. 1 the time stamp capture event is the last bit of eof. tsen tsout operation setting bit 0 tsout toggle operation is disabled. 1 tsout toggle operation is enabled.
780 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (b) cnts write 15 14 13 12 11 10 9 8 00000 set tslock set tssel set tsen 76543210 00000 clear tslock clear tssel clear tsen set tslock clear tslock setting of tslock bit 0 1 tslock bit is cleared to 0. 1 0 tslock bit is set to 1. other than above tslock bit is not changed. set tssel clear tssel setting of tssel bit 0 1 tssel bit is cleared to 0. 1 0 tssel bit is set to 1. other than above tssel bit is not changed. set tsen clear tsen setting of tsen bit 0 1 tsen bit is cleared to 0. 1 0 tsen bit is set to 1. other than above tsen bit is not changed.
781 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (19) cnmdataxm, cnmdatazm - cann message data byte register (x = 0 to 7, z = 01, 23, 45, 67) the cnmdataxm, cnmdatazm registers are used to store the data of a transmit/receive message. access the cnmdatazm registers can be read/written in 16-bit units. the cnmdataxm registers can be read/written in 8-bit units. address refer to ?can registers overview? on page 747. initial value undefined. cnmdata01m 15 14 13 12 11 10 9 8 mdata0115 mdata0114 mdata0113 mdata0112 mdata0111 mdata0110 mdata019 mdata018 76543210 m data 0 1 7 m data 0 1 6 m data 0 1 5 m data 0 1 4 m data 0 1 3 m data 0 1 2 m data 0 1 1 m data 0 1 0 cnmdata0m 76543210 m data 0 7 m data 0 6 m data 0 5 m data 0 4 m data 0 3 m data 0 2 m data 0 1 m data 0 0 cnmdata1m 76543210 m data 1 7 m data 1 6 m data 1 5 m data 1 4 m data 1 3 m data 1 2 m data 1 1 m data 1 cnmdata23m 15 14 13 12 11 10 9 8 mdata2315 mdata2314 mdata2313 mdata2312 mdata2311 mdata2310 mdata239 mdata238 76543210 m data 2 3 7 m data 2 3 6 m data 2 3 5 m data 2 3 4 m data 2 3 3 m data 2 3 2 m data 2 3 1 m data 2 3 0 cnmdata2m 76543210 m data 2 7 m data 2 6 m data 2 5 m data 2 4 m data 2 3 m data 2 2 m data 2 1 m data 2 0 cnmdata3m 76543210 m data 3 7 m data 3 6 m data 3 5 m data 3 4 m data 3 3 m data 3 2 m data 3 1 m data 3 0
782 chapter 20 can controller (can) user?s manual u17566ee5v1um00 cnmdata45m 15 14 13 12 11 10 9 8 mdata4515 mdata4514 mdata4513 mdata4512 mdata4511 mdata4510 mdata459 mdata458 76543210 m data 4 5 7 m data 4 5 6 m data 4 5 5 m data 4 5 4 m data 4 5 3 m data 4 5 2 m data 4 5 1 m data 4 5 0 cnmdata4m 76543210 m data 4 7 m data 4 6 m data 4 5 m data 4 4 m data 4 3 m data 4 2 m data 4 1 m data 4 0 cnmdata5m 76543210 m data 5 7 m data 5 6 m data 5 5 m data 5 4 m data 5 3 m data 5 2 m data 5 1 m data 5 0 cnmdata67m 15 14 13 12 11 10 9 8 mdata6715 mdata6714 mdata6713 mdata6712 mdata6711 mdata6710 mdata679 mdata678 76543210 m data 6 7 7 m data 6 7 6 m data 6 7 5 m data 6 7 4 m data 6 7 3 m data 6 7 2 m data 6 7 1 m data 6 7 0 cnmdata6m 76543210 m data 6 7 m data 6 6 m data 6 5 m data 6 4 m data 6 3 m data 6 2 m data 6 1 m data 6 0 cnmdata7m 76543210 m data 7 7 m data 7 6 m data 7 5 m data 7 4 m data 7 3 m data 7 2 m data 7 1 m data 7 0
783 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (20) cnmdlcm - cann message data length register m the cnmdlcm register is used to set the number of bytes of the data field of a message buffer. access this register can be read/written in 8-bit units. address refer to ?can registers overview? on page 747. initial value 0000xxxx b . the register is initialized by any reset. note the data and dlc value actually transmitted to can bus are as follows. caution 1. be sure to set bits 7 to 4 to 0000 b . 2. receive data is stored in as many cnmdataxm register as the number of bytes (however, the upper limit is 8) corresponding to dlc of the received frame. the cnmdataxm register in which no data is stored is undefined. 76543210 0 0 0 0 mdlc3 mdlc2 mdlc1 mdlc0 mdlc3 mdlc2 mdlc1 mdlc0 data length of transmit/receive message 00000 bytes 00011 byte 00102 bytes 00113 bytes 01004 bytes 01015 bytes 01106 bytes 01117 bytes 10008 bytes 1001setting prohibited (if these bits are set during transmission, 8- byte data is transmitted regardless of the set dlc value when a data frame is transmitted. however, the dlc actually transmitted to the can bus is the dlc value set to this register.) note 1010 1011 1100 1101 1110 1111 type of transmit frame length of transmit data dlc transmitted data frame number of bytes specified by dlc (however, 8 bytes if dlc  8) mdlc3 to mdlc0 bits remote frame 0 bytes
784 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (21) cnmconfm - cann message configuration register m the cnmconfm register is used to specify the type of the message buffer and to set a mask. access this register can be read/written in 8-bit units. address refer to ?can registers overview? on page 747. initial value undefined. note a remote frame is received and stored, regardless of the setting of ows and dn. a remote frame that satisfies the other conditions (id matches, rtr = 0, trq = 0) is always received and stored in the corresponding message buffer (interrupt generated, dn flag set, mdlc[3:0] updated, and recorded to the receive history list). 76543210 ows rtr mt2 mt1 mt0 0 0 ma0 ows overwrite control bit 0 the message buffer that has already received a data frame a is not overwritten by a newly received data frame. the newly received data frame is discarded. a) the ?message buffer that has already received a data frame? is a receive message buffer whose the cnmctrlm.dn bit has been set to 1. 1 the message buffer that has already received a data frame a is overwritten by a newly received data frame. rtr remote frame request bit a a) the rtr bit specifies the type of message frame that is transmitted from a mes- sage buffer defined as a transmit message buffer. even if a valid remote frame has been received, the rtr bit of the transmit message buffer that has received the frame remains cleared to 0. even if a remote frame whose id matches has been received from the can bus with the rtr bit of the transmit message buffer set to 1 to transmit a remote frame, that remote frame is not received or stored (interrupt generated, dn flag set, the mdlc0 to mdlc3 bits updated, and recorded to the receive history list). 0 transmit a data frame. 1 transmit a remote frame. mt2 mt1 mt0 message buffer type setting bit 0 0 0 transmit message buffer 0 0 1 receive message buffer (no mask setting) 0 1 0 receive message buffer (mask 1 set) 0 1 1 receive message buffer (mask 2 set) 1 0 0 receive message buffer (mask 3 set) 1 0 1 receive message buffer (mask 4 set) other than above setting prohibited
785 can controller (can) chapter 20 user?s manual u17566ee5v1um00 caution be sure to write 0 to bits 2 and 1. ma0 message buffer assignment bit 0 message buffer not used. 1 message buffer used.
786 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (22) cnmidlm, cnmidhm - cann message id register m the cnmidlm and cnmidhm registers are used to set an identifier (id). access these registers can be read/written in 16-bit units. address refer to ?can registers overview? on page 747. initial value undefined. caution 1. be sure to write 0 to bits 14 and 13 of the cnmidhm register. 2. be sure to align the id value according to the given bit positions into this registers. note that for standard id, the id value must be shifted to fit into id28 to id11 bit positions. cnmidlm 15 14 13 12 11 10 9 8 id15 id14 id13 id12 id11 id10 id9 id8 76543210 id7 id6 id5 id4 id3 id2 id1 id0 cnmidhm 15 14 13 12 11 10 9 8 ide 0 0 id28 id27 id26 id25 id24 76543210 id23 id22 id21 id20 id19 id18 id17 id16 ide format mode specification bit 0 standard format mode (id28 to id18: 11 bits) a a) the id17 to id0 bits are not used. 1 extended format mode (id28 to id0: 29 bits) id28 to id0 message id id28 to id18 standard id value of 11 bits (when ide = 0) id28 to id0 extended id value of 29 bits (when ide = 1)
787 can controller (can) chapter 20 user?s manual u17566ee5v1um00 (23) cnmctrlm - cann message control register m the cnmctrlm register is used to control the operation of the message buffer. access this register can be read/written in 16-bit units. address refer to ?can registers overview? on page 747. initial value 00x0 0000 0000 0000 b . the register is initialized by any reset. (a) cnmctrlm read 15 14 13 12 11 10 9 8 00muc00000 76543210 000mowiedntrqrdy muc a a) the muc bit is undefined until the first reception and storage is performed. bit indicating that message buffer data is being updated 0 the can module is not updating the message buffer (reception and storage). 1 the can module is updating the message buffer (reception and storage). mow a a) the mow bit is not set to 1 even if a remote frame is received and stored in the transmit message buffer with the dn bit = 1. message buffer overwrite status bit 0 the message buffer is not overwritten by a newly received data frame. 1 the message buffer is overwritten by a newly received data frame. ie message buffer interrupt request enable bit 0 receive message buffer: valid message reception completion interrupt disabled. transmit message buffer: normal message transmission completion interrupt disabled. 1 receive message buffer: valid message reception completion interrupt enabled. transmit message buffer: normal message transmission completion interrupt enabled. dn message buffer data update bit 0 a data frame or remote frame is not stored in the message buffer. 1 a data frame or remote frame is stored in the message buffer.
788 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (b) cnmctrlm write trq message buffer transmission request bit 0 no message frame transmitting request that is pending or being transmitted is in the message buffer. 1 the message buffer is holding transmission of a message frame pending or is transmitting a message frame. rdy message buffer ready bit 0 the message buffer can be written by software. the can module cannot write to the message buffer. 1 writing the message buffer by software is ignored (except a write access to the rdy, trq, dn, and mow bits). the can module can write to the message buffer. 15 14 13 12 11 10 9 8 0000 set ie 0 set trq set rdy 76543210 000 clear mow clear ie clear dn clear trq clear rdy clear mow setting of mow bit 0 mow bit is not changed. 1 mow bit is cleared to 0. set ie clear ie setting of ie bit 0 1 ie bit is cleared to 0. 1 0 ie bit is set to 1. other than above ie bit is not changed. clear dn setting of dn bit 1 dn bit is cleared to 0. 0 dn bit is not changed. set trq clear trq setting of trq bit 0 1 trq bit is cleared to 0. 1 0 trq bit is set to 1. other than above trq bit is not changed.
789 can controller (can) chapter 20 user?s manual u17566ee5v1um00 caution 1. set ie bit and rdy bit always separately. 2. do not set the dn bit to 1 by software. be sure to write 0 to bit 10. 3. do not set the trq bit and the rdy bit (1) at the same time. set the rdy bit (1) before setting the trq bit. 4. do not clear the rdy bit (0) during message transmission. follow the transmission abort process about clearing the rdy bit (0) for redefinition of the message buffer. 5. clear again when rdy bit is not cleared even if this bit is cleared. 6. be sure that rdy is cleared before writing to the other message buffer registers, by checking the status of the rdy bit. set rdy clear rdy setting of rdy bit 0 1 rdy bit is cleared to 0. 1 0 rdy bit is set to 1. other than above rdy bit is not changed.
790 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.8 can controller initialization 20.8.1 initialization of can module before can module operation is enabled, the can module system clock needs to be determined by setting the ccp[3:0] bits of the cngmcs register by software. do not change the setting of the can module system clock after can module operation is enabled. the can module is enabled by setting the gom bit of the cngmctrl register. for the procedure of initializing the can module, refer to ?operation of can controller? on page 829 . 20.8.2 initialization of message buffer after the can module is enabled, the message buffers contain undefined values. a minimum initialization for all the message buffers, even for those not used in the application, is necessary before switching the can module from the initialization mode to one of the operation modes. ? clear the rdy, trq, and dn bits of all cnmctrlm registers to 0. ? clear the ma0 bit of all cnmconfm registers to 0. 20.8.3 redefinition of message buffer redefining a message buffer means changing the id and control information of the message buffer while a message is being received or transmitted, without affecting other transmission/reception operations. (1) to redefine message buffer in initialization mode place the can module in the initialization mode once and then change the id and control information of the message buffer in the initialization mode. after changing the id and control information, set the can module to an operation mode. (2) to redefine message buffer during reception perform redefinition as shown in figure 20-38 . (3) to redefine message buffer during transmission to rewrite the contents of a transmit message buffer to which a transmission request has been set, perform transmission abort processing (see ?transmission abort process except for in normal operation mode with automatic block transmission (abt)? on page 808 and ?transmission abort process except for abt transmission in normal operation mode with automatic block transmission (abt)? on page 808 ). confirm that transmission has been aborted or completed, and then redefine the message buffer. after redefining the transmit message buffer, set a transmission request using the procedure described below. when setting a transmission request to a message buffer that has been redefined without aborting the transmission in progress, however, the 1-bit wait time is not necessary.
791 can controller (can) chapter 20 user?s manual u17566ee5v1um00 figure 20-26 setting transmission request (trq) to transmit message buffer after redefinition caution 1. when a message is received, reception filtering is performed in accordance with the id and mask set to each receive message buffer. if the procedure in figure 20-38 on page 832 is not observed, the contents of the message buffer after it has been redefined may contradict the result of reception (result of reception filtering). if this happens, check that the id and ide received first and stored in the message buffer following redefinition are those stored after the message buffer has been redefined. if no id and ide are stored after redefinition, redefine the message buffer again. 2. when a message is transmitted, the transmission priority is checked in accordance with the id, ide, and rtr bits set to each transmit message buffer to which a transmission request was set. the transmit message buffer having the highest priority is selected for transmission. if the procedure in figure 20-26 on page 791 is not observed, a message with an id not having the highest priority may be transmitted after redefinition. exec u te tr a n s mi ss ion? w a it for 1 b it of can d a t a . s et trq b it s et trq b it = 1 cle a r trq b it = 0 ye s no redefinition completed end
792 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.8.4 transition from initializ ation mode to operation mode the can module can be switched to the following operation modes. ? normal operation mode ? normal operation mode with abt ? receive-only mode ? single-shot mode ? self-test mode figure 20-27 transition to operation modes the transition from the initialization mode to an operation mode is controlled by the bit string opmode[2:0] in the cnctrl register. changing from one operation mode into another requires shifting to the initialization mode in between. do not change one operation mode to another directly; otherwise the operation will not be guaranteed. requests for transition from an operation mode to the initialization mode are held pending when the can bus is not in the interframe space (i.e., frame reception or transmission is in progress), and the can module enters the initialization mode at the first bit in the interframe space (the values of the opmode[2:0] bits are changed to 000 b ) . after issuing a request to change the mode to the initialization mode, read the opmode[2:0] bits until their value becomes 000 b to confirm that the module has entered the initialization mode (see figure 20-36 on page 830 ). can module channel invalid [receive-only mode] opmode[2:0]=03h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 03h [single-shot mode] opmode[2:0]=04h opmode[2:0] = 04h opmode[2:0] = 05h init mode opmode[2:0] = 00h efsd = 1 and gom = 0 all can modules are in init mode and gom = 0 gom = 1 reset reset released [normal operation mode with abt] opmode[2:0]=02h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 00h and interframe space opmode[2:0] = 02h opmode[2:0] = 01h opmode[2:0] = 00h and can bus is busy. [normal operation mode] opmode[2:0]=01h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and can bus is busy. [self-test mode] opmode[2:0]=05h
793 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.8.5 resetting error counter cnerc of can module if it is necessary to reset the can module error counter cnerc and can module information register cninfo when re-initialization or forced recovery from the bus-off status is made, set the ccerc bit of the cnctrl register to 1 in the initialization mode. when this bit is set to 1, the cnerc and cninfo registers are cleared to their default values.
794 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.9 message reception 20.9.1 message reception in all the operation modes, the complete message buffer area is analyzed to find a suitable buffer to store a newly received message. all message buffers satisfying the following conditions are included in that evaluation (rx-search process). ? used as a message buffer (ma0 bit of cnmconfm register set to 1.) ? set as a receive message buffer (mt[2:0] bits of cnmconfm register are set to 001 b , 010 b , 011 b , 100 b , or 101 b .) ? ready for reception (rdy bit of cnmctrlm register is set to 1.) when two or more message buffers of the can module receive a message, the message is stored according to the priority explained below. the message is always stored in the message buffer with the highest priority, not in a message buffer with a low priority. for example, when an unmasked receive message buffer and a receive message buffer linked to mask 1 have the same id, the received message is not stored in the message buffer linked to mask 1, even if that message buffer has not received a message and a message has already been received in the unmasked receive message buffer. in other words, when a condition has been set in two or more message buffers with different priorities, the message buffer with the highest priority always stores the message; the message is not stored in message buffers with a lower priority. this also applies when the message buffer with the highest priority is unable to store a message (i.e., when dn = 1 indicating that a message has already been received, but rewriting is disabled because ows = 0). in this case, the message is not actually stored in the candidate message buffer with the highest priority, but neither is it stored in a message buffer with a lower priority. table 20-24 mbrb priorities priority storing condition if same id is set 1 (high) unmasked message buffer dn bit = 0 dn bit = 1 and ows bit = 1 2 message buffer linked to mask 1 dn bit = 0 dn bit = 1 and ows bit = 1 3 message buffer linked to mask 2 dn bit = 0 dn bit = 1 and ows bit = 1 4 message buffer linked to mask 3 dn bit = 0 dn bit = 1 and ows bit = 1 5 (low) message buffer linked to mask 4 dn bit = 0 dn bit = 1 and ows bit = 1
795 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.9.2 receive data read to keep data consistency when reading can message buffers, perform the data reading according to figure 20-49 on page 843 to figure 20-52 on page 847 . during message reception, the can module sets dn of the cnmctrlm register two times: at the beginning of the storage process of data to the message buffer, and again at the end of this storage process. during this storage process, the muc bit of the cnmctrlm register of the message buffer is set. (refer to figure 20-28 on page 795 .) the receive history list is also updated just before the storgage process. in addition, during storage process (muc = 1), the rdy bit of the cnmctrl register of the message buffer is locked to avoid the coincidental data wr by cpu. note the storage process may be disturbed (delayed) when the cpu accesses the message buffer. figure 20-28 dn and muc bit setting period (for standard id format) sof (1) id ide rtr r0 dlc data0-data7 crc ack eof can std id format (11) (1) (1) (1) (4) (0-64) (16) (2) recessive dominant dn muc message store mdata,mdlc.midx- > mbuf (7) set dn & clear muc at the same timing cints1 set dn & muc at the same time ifs intrec1 operation of the can contoroller
796 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.9.3 receive hist ory list function the receive history list (rhl) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. the rhl consists of storage elements equivalent to up to 23 messages, the last in-message pointer (lipt) with the corresponding cnlipt register and the receive history list get pointer (rgpt) with the corresponding cnrgpt register. the rhl is undefined immediately after the transition of the can module from the initialization mode to one of the operation modes. the cnlipt register holds the contents of the rhl element indicated by the value of the lipt pointer minus 1. by reading the cnlipt register, therefore, the number of the message buffer that received and stored a data frame or remote frame first can be checked. the lipt pointer is utilized as a write pointer that indicates to what part of the rhl a message buffer number is recorded. any time a data frame or remote frame is received and stored, the corresponding message buffer number is recorded to the rhl element indicated by the lipt pointer. each time recording to the rhl has been completed, the lipt pointer is automatically incremented. in this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. the rgpt pointer is utilized as a read pointer that reads a recorded message buffer number from the rhl. this pointer indicates the first rhl element that the cpu has not read yet. by reading the cnrgpt register by software, the number of a message buffer that has received and stored a data frame or remote frame can be read. each time a message buffer number is read from the cnrgpt register, the rgpt pointer is automatically incremented. if the value of the rgpt pointer matches the value of the lipt pointer, the rhpm bit (receive history list pointer match) of the cnrgpt register is set to 1. this indicates that no message buffer number that has not been read remains in the rhl. if a new message buffer number is recorded, the lipt pointer is incremented and because its value no longer matches the value of the rgpt pointer, the rhpm bit is cleared. in other words, the numbers of the unread message buffers exist in the rhl. if the lipt pointer is incremented and matches the value of the rgpt pointer minus 1, the rovf bit (receive history list overflow) of the cnrgpt register is set to 1. this indicates that the rhl is full of numbers of message buffers that have not been read. when further message reception and storing occur, the last recorded message buffer number is overwritten by the number of the message buffer that received and stored the newly received message. in this case, after the rovf bit has been set (1), the recorded message buffer numbers in the rhl do not completely reflect the chronological order. however messages itself are not lost and can be located by cpu search in message buffer memory with the help of the dn-bit. caution if the history list is in the overflow condition (rovf is set), reading the history list contents is still possible, until the history list is empty (indicated by rhpm flag set). nevertheless, the history list remains in the overflow condition, until rovf is cleared by software. if rovf is not cleared, the rhpm flag will also not be updated (cleared) upon a message storage of newly received frame. this may lead to the situation, that rhpm indicates an empty history list, although a reception has taken place, while the history list is in the overflow state (rovf and rhpm are set).
797 can controller (can) chapter 20 user?s manual u17566ee5v1um00 as long as the rhl contains 23 or less entries the sequence of occurrence is maintained. if more receptions occur without reading the rhl by the host processor, complete sequence of receptions can not be recovered. figure 20-29 receive history list
798 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.9.4 mask function for any message buffer, which is used for reception, the assignment to one of four global reception masks (or no mask) can be selected. by using the mask function, the message id comparison can be reduced by masked bits, herewith allowing the reception of several different ids into one buffer. while the mask function is in effect, an identifier bit that is defined to be 1 by a mask in the received message is not compared with the corresponding identifier bit in the message buffer. however, this comparison is performed for any bit whose value is defined as 0 by the mask. for example, let us assume that all messages that have a standard-format id, in which bits id27 to id25 are 0 and bits id24 and id22 are 1, are to be stored in message buffer 14. the procedure for this example is shown below. 1. identifier to be stored in message buffer 2. identifier to be configured in message buffer 14 (example) (using cnmidl14 and cnmidh14 registers) note 1. id with the id27 to id25 bits cleared to 0 and the id24 and id22 bits set to 1 is registered (initialized) to message buffer 14. 2. message buffer 14 is set as a standard format identifier that is linked to mask 1 (mt[2:0] of cnmconf14 register are set to 010 b ). mask setting for can module 1 (mask 1) (example) (using can1 address mask 1 registers l and h (c1maskl1 and c1maskh1)) 1: not compared (masked) 0: compared id28 id27 id26 id25 id24 id 23 id22 id21 id20 id19 id18 x0001x1xxxx id28 id27 id26 id25 id24 id 23 id22 id21 id20 id19 id18 x0001x1xxxx id17 id16 id15 id14 id13 id 12 id11 id10 id9 id8 id7 xxxxxxxxxxx id6 id5 id4 id3 id2 id1 id0 xxxxxxx cmid28 cmid27 cmid26 cmid25 cmid24 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 10000101111 cmid17 cmid16 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 cmid7 11111111111 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 1111111
799 can controller (can) chapter 20 user?s manual u17566ee5v1um00 the cmid27 to cmid24 and cmid22 bits are cleared to 0, and the cmid28, cmid23, and cmid21 to cmid0 bits are set to 1.
800 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.9.5 multi buffer receive block function the multi buffer receive block (mbrb) function is used to store a block of data in two or more message buffers sequentially with no cpu interaction, by setting the same id to two or more message buffers with the same message buffer type. these message buffers can be allocated anywhere in the message buffer memory, they do not even have to follow each other adjacently. suppose, for example, the same message buffer type is set to 10 message buffers, message buffers 10 to 19, and the same id is set to each message buffer. if the first message whose id matches an id of the message buffers is received, it is stored in message buffer 10. at this point, the dn bit of message buffer 10 is set, prohibiting overwriting the message buffer when subsequent messages are received. when the next message with a matching id is received, it is received and stored in message buffer 11. each time a message with a matching id is received, it is sequentially (in the ascending order) stored in message buffers 12, 13, and so on. even when a data block consisting of multiple messages is received, the messages can be stored and received without overwriting the previously received matching-id data. whether a data block has been received and stored can be checked by setting the ie bit of the cnmctrlm register of each message buffer. for example, if a data block consists of k messages, k message buffers are initialized for reception of the data block. the ie bit in message buffers 0 to (k-2) is cleared to 0 (interrupts disabled), and the ie bit in message buffer k-1 is set to 1 (interrupts enabled). in this case, a reception completion interrupt occurs when a message has been received and stored in message buffer k-1, indicating that mbrb has become full. alternatively, by clearing the ie bit of message buffers 0 to (k-3) and setting the ie bit of message buffer k-2, a warning that mbrb is about to overflow can be issued. the basic conditions of storing receive data in each message buffer for the mbrb are the same as the conditions of storing data in a single message buffer. caution 1. mbrb can be configured for each of the same message buffer types. therefore, even if a message buffer of another mbrb whose id matches but whose message buffer type is different has a vacancy, the received message is not stored in that message buffer, but instead discarded. 2. mbrb does not have a ring buffer structure. therefore, after a message is stored in the message buffer having the highest number in the mbrb configuration, a newly received message will not be stored in the message buffer having the lowest message buffer number. 3. mbrb operates based on the reception and storage conditions; there are no settings dedicated to mbrb, such as function enable bits. by setting the same message buffer type and id to two or more message buffers, mbrb is automatically configured. 4. with mbrb, ?matching id? means ?matching id after mask?. even if the id set to each message buffer is not the same, if the id that is masked by the mask register matches, it is considered a matching id and the buffer that has this id is treated as the storage destination of a message. 5. the priority between mbrbs is mentioned in the table table 20-24 .
801 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.9.6 remote frame reception in all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. ? used as a message buffer (ma0 bit of cnmconfm register set to 1.) ? set as a transmit message buffer (mt[2:0] bits in cnmconfm register set to 000 b ) ? ready for reception (rdy bit of cnmctrlm register set to 1.) ? set to transmit message (rtr bit of cnmconfm register is cleared to 0.) ? transmission request is not set. (trq bit of cnmctrlm register is cleared to 0.) upon acceptance of a remote frame, the following actions are executed if the id of the received remote frame matches the id of a message buffer that satisfies the above conditions. ? the dlc[3:0] bit string in the cnmdlcm register store the received dlc value. ? the cnmdata0m to cnmdata7m registers in the data area are not updated (data before reception is saved). ? the dn bit of the cnmctrlm register is set to 1. ? the cints1 bit of the cnints register is set to 1 (if the ie bit in the cnmctrlm register of the message buffer that receives and stores the frame is set to 1). ? the receive completion interrupt (intcnrec) is output (if the ie bit of the message buffer that receives and stores the frame is set to 1 and if the cie1 bit of the cnie register is set to 1). ? the message buffer number is recorded in the receive history list. caution when a message buffer is searched for receiving and storing a remote frame, overwrite control by the ows bit of the cnmconfm register of the message buffer and the dn bit of the cnmctrlm register are not checked. the setting of ows is ignored, and dn is set in any case. if more than one transmit message buffer has the same id and the id of the received remote frame matches that id, the remote frame is stored in the transmit message buffer with the lowest message buffer number.
802 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.10 message transmission 20.10.1 message transmission a message buffer with its trq bit set to 1 participates in the search for the most high-prioritized message when the following conditions are fulfilled. this behavior is valid for all operational modes. ? used as a message buffer (ma0 bit of cnmconfm register set to 1.) ? set as a transmit message buffer (mt[2:0] bits of cnmconfm register set to 000 b .) ? ready for transmission (rdy bit of cnmctrlm register set to 1.) the can system is a multi-master communication system. in a system like this, the priority of message transmission is determined based on message identifiers (ids). to facilitate transmission processing by software when there are several messages awaiting transmission, the can module uses hardware to check the id of the message with the highest priority and automatically identifies that message. this eliminates the need for software-based priority control. transmission priority is controlled by the identifier (id). figure 20-30 message processing example after the transmit message search, the transmit message with the highest priority of the transmit message buffers that have a pending transmission request (message buffers with the trq bit set to 1 in advance) is transmitted. if a new transmission request is set, the transmit message buffer with the new transmission request is compared with the transmit message buffer with a pending transmission request. if the new transmission request has a higher priority, it is transmitted, unless transmission of a message with a low priority has already started. if transmission of a message with a low priority has already started, however, the new transmission request is transmitted later. to solve this priority inversion effect, the software can perform a transmission abort request for the lower priority message. the highest priority is determined according to the following rules. message no. the can module transmits messages in the following sequence. message waiting to be transmitted id = 120h id = 229h id = 223h id = 023h id = 123h 0 1 2 3 4 5 6 7 8 9 1. message 6 2. message 1 3. message 8 4. message 5 5. message 2
803 can controller (can) chapter 20 user?s manual u17566ee5v1um00 note 1. if the automatic block transmission request bit abttrg is set to 1 in the normal operation mode with abt, the trq bit is set to 1 only for one message buffer in the abt message buffer group. if the abt mode was triggered by abttrg bit (1), one trq bit is set to 1 in the abt area (buffer 0 through 7). beyond this trq bit, the application can request transmissions (set trq bit to 1) for other tx-message buffers that do not belong to the abt area. in that case an interval arbitration process (tx-search) evaluates all tx-message buffers with trq bit set to 1 and chooses the message buffer that contains the highest prioritized identifier for the next transmission. if there are 2 or more identifiers that have the highest priority (i.e. identical identifiers), the message located at the lowest message buffer number is transmitted at first. upon successful transmission of a message frame, the following operations are performed. ? the trq flag of the corresponding transmit message buffer is automatically cleared to 0. ? the transmission completion status bit cints0 of the cnints register is set to 1 (if the interrupt enable bit (ie) of the corresponding transmit message buffer is set to 1). ? an interrupt request signal intcntrx is output (if the cie0 bit of the cnie register is set to 1 and if the interrupt enable bit (ie) of the corresponding transmit message buffer is set to 1). 2. when changing the contents of a transmit buffer, the rdy flag of this buffer must be cleared before updating the buffer contents. as during internal transfer actions, the rdy flag may be locked temporarily, the status of rdy must be checked by software, after changing it. priority conditions description 1 (high) value of first 11 bits of id [id28 to id18]: the message frame with the lowest value represented by the first 11 bits of the id is transmitted first. if the value of an 11-bit standard id is equal to or smaller than the first 11 bits of a 29-bit extended id, the 11- bit standard id has a higher priority than a message frame with a 29-bit extended id. 2 frame type a data frame with an 11-bit standard id (rtr bit is cleared to 0) has a higher priority than a remote frame with a standard id and a message frame with an extended id. 3 id type a message frame with a standard id (ide bit is cleared to 0) has a higher priority than a message frame with an extended id. 4 value of lower 18 bits of id [id17 to id0]: if one or more transmission-pending extended id message frame has equal values in the first 11 bits of the id and the same frame type (equal rtr bit values), the message frame with the lowest value in the lower 18 bits of its extended id is transmitted first. 5 (low) message buffer number if two or more message buffers request transmission of message frames with the same id, the message from the message buffer with the lowest message buffer number is transmitted first.
804 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.10.2 transmit hist ory list function the transmit history list (thl) function records in the transmit history list the number of the transmit message buffer from which data or remote frames have been were sent. the thl consists of storage elements equivalent to up to seven messages, the last out-message pointer (lopt) with the corresponding cnlopt register, and the transmit history list get pointer (tgpt) with the corresponding cntgpt register. the thl is undefined immediately after the transition of the can module from the initialization mode to one of the operation modes. the cnlopt register holds the contents of the thl element indicated by the value of the lopt pointer minus 1. by reading the cnlopt register, therefore, the number of the message buffer that transmitted a data frame or remote frame first can be checked. the lopt pointer is utilized as a write pointer that indicates to what part of the thl a message buffer number is recorded. any time a data frame or remote frame is transmitted, the corresponding message buffer number is recorded to the thl element indicated by the lopt pointer. each time recording to the thl has been completed, the lopt pointer is automatically incremented. in this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. the tgpt pointer is utilized as a read pointer that reads a recorded message buffer number from the thl. this pointer indicates the first thl element that the cpu has not yet read. by reading the cntgpt register by software, the number of a message buffer that has completed transmission can be read. each time a message buffer number is read from the cntgpt register, the tgpt pointer is automatically incremented. if the value of the tgpt pointer matches the value of the lopt pointer, the thpm bit (transmit history list pointer match) of the cntgpt register is set to 1. this indicates that no message buffer numbers that have not been read remain in the thl. if a new message buffer number is recorded, the lopt pointer is incremented and because its value no longer matches the value of the tgpt pointer, the thpm bit is cleared. in other words, the numbers of the unread message buffers exist in the thl. if the lopt pointer is incremented and matches the value of the tgpt pointer minus 1, the tovf bit (transmit history list overflow) of the cntgpt register is set to 1. this indicates that the thl is full of message buffer numbers that have not been read. if a new message is received and stored, the message buffer number recorded last is overwritten by the message buffer number that transmitted its message afterwards. in this case, after the tovf bit has been set (1), therefore, the recorded message buffer numbers in the thl do not completely reflect the chronological order. however the other transmitted messages can be found by a cpu search applied to all transmit message buffers unless the cpu has not overwritten a transmit object in one of these buffers beforehand. in total up to six transmission completions can occur without overflowing the thl.
805 can controller (can) chapter 20 user?s manual u17566ee5v1um00 caution if the history list is in the overflow condition (tovf is set), reading the history list contents is still possible, until the history list is empty (indicated by thpm flag set). nevertheless, the history list remains in the overflow condition, until tovf is cleared by software. if tovf is not cleared, the thpm flag will also not be updated (cleared) upon successful transmission of a new message. this may lead to the situation, that thpm indicates an empty history list, although a successful transmission has taken place, while the history list is in the overflow state (tovf and thpm are set). figure 20-31 transmit history list last out- message pointer (lopt) - cpu confirms tx completion of message buffer 6, 9, and 2. - tx completion of message buffer 3, and 4. event: transmit history list get pointer (tgpt) - message buffer 8, 5, 6, and 10 completes transmission. - thl is full. - tovf is set. event: transmit history list (thl) message buffer 6 message buffer 9 message buffer 2 message buffer 7 0 1 2 3 4 5 6 7 - message buffer11, 13, and 14 completes transmission. - overflow situation occurs. event: tovf = 1 lopt is blocked tovf = 1 lopt is blocked tovf = 1 denotes that lopt equals tgpt - 1 while message buffer number stored to element indicated by lopt - 1. last out- message pointer (lopt) transmit history list get pointer (tgpt) transmit history list (thl) message buffer 7 message buffer 3 message buffer 4 0 1 2 3 4 5 6 7 transmit history list (thl) message buffer 6 message buffer 10 message buffer 7 message buffer 3 message buffer 4 message buffer 8 message buffer 5 0 1 2 3 4 5 6 7 last out- message pointer (lopt) transmit history list get pointer (tgpt) transmit history list (thl) message buffer 6 message buffer 14 message buffer 7 message buffer 3 message buffer 4 message buffer 8 message buffer 5 0 1 2 3 4 5 6 7 last out- message pointer (lopt) transmit history list get pointer (tgpt)
806 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.10.3 automatic block transmission (abt) the automatic block transmission (abt) function is used to transmit two or more data frames successively with no cpu interaction. the maximum number of transmit message buffers assigned to the abt function is eight (message buffer numbers 0 to 7). by setting the opmode[2:0] bits of the cnctrl register to 010 b , ?normal operation mode with automatic block transmission function? (hereafter referred to as abt mode) can be selected. to issue an abt transmission request, define the message buffers by software first. set the ma0 bit (1) in all the message buffers used for abt, and define all the buffers as transmit message buffers by setting the ma[2:0] bits to 000 b . be sure to set the same id for the message buffers for abt even when that id is being used for all the message buffers. to use two or more ids, set the id of each message buffer by using the cnmidlm and cnmidhm registers. set the cnmdlcm and cnmdata0m to cnmdata7m registers before issuing a transmission request for the abt function. after initialization of message buffers for abt is finished, the rdy bit needs to be set (1). in the abt mode, the trq bit does not have to be manipulated by software. after the data for the abt message buffers has been prepared, set the abttrg bit to 1. automatic block transmission is then started. when abt is started, the trq bit in the first message buffer (message buffer 0) is automatically set to 1. after transmission of the data of message buffer 0 is finished, the trq bit of the next message buffer, message buffer 1, is set automatically. in this way, transmission is executed successively. a delay time can be inserted by program in the interval in which the transmission request (trq ) is automatically set while successive transmission is being executed. the delay time to be inserted is defined by the cngmabtd register. the unit of the delay time is dbt (data bit time). dbt depends on the setting of the cnbrp and cnbtr registers. among transmit objects within the abt-area, the priority of the transmission id is not evaluated. the data of message buffers 0 to 7 are sequentially transmitted. when transmission of the data frame from message buffer 7 has been completed, the abttrg bit is automatically cleared to 0 and the abt operation is finished. if the rdy bit of an abt message buffer is cleared during abt, no data frame is transmitted from that buffer, abt is stopped, and the abttrg bit is cleared. after that, transmission can be resumed from the message buffer where abt stopped, by setting the rdy and abttrg bits to 1 by software. to not resume transmission from the message buffer where abt stopped, the internal abt engine can be reset by setting the abtclr bit to 1 while abt mode is stopped and the abttrg bit is cleared to 0. in this case, transmission is started from message buffer 0 if the abtclr bit is cleared to 0 and then the abttrg bit is set to 1. an interrupt can be used to check if data frames have been transmitted from all the message buffers for abt. to do so, the ie bit of the cnmctrlm register of each message buffer except the last message buffer needs to be cleared (0). if a transmit message buffer other than those used by the abt function (message buffers 8 to 31) is assigned to a transmit message buffer, the message to be transmitted next is determined by the priority of the transmission id of the abt message buffer whose transmission is currently
807 can controller (can) chapter 20 user?s manual u17566ee5v1um00 held pending and the transmission id of the message buffers other than those used by the abt function. transmission of a data frame from an abt message buffer is not recorded in the transmit history list (thl). caution 1. set the abtclr bit to 1 while the abttrg bit is cleared to 0 in order to resume abt operation at buffer no.0. if the abtclr bit is set to 1 while the abttrg bit is set to 1, the subsequent operation is not guaranteed. 2. if the automatic block transmission engine is cleared by setting the abtclr bit to 1, the abtclr bit is automatically cleared immediately after the processing of the clearing request is completed. 3. do not set the abttrg bit in the initialization mode. if the abttrg bit is set in the initialization mode, the proper operation is not guaranteed after the mode is changed from the initialization mode to the abt mode. 4. do not set the trq bit of the abt message buffers to 1 by software in the normal operation mode with abt. otherwise, the operation is not guaranteed. 5. the cngmabtd register is used to set the delay time that is inserted in the period from completion of the preceding abt message to setting of the trq bit for the next abt message when the transmission requests are set in the order of message numbers for each message for abt that is successively transmitted in the abt mode. the timing at which the messages are actually transmitted onto the can bus varies depending on the status of transmission from other stations and the status of the setting of the transmission request for messages other than the abt messages (message buffers 8 to 31). 6. if a transmission request is made for a message other than an abt message and if no delay time is inserted in the interval in which transmission requests for abt are automatically set (cngmabtd register = 00 h ), messages other than abt messages may be transmitted not depending on their priority compared to the priority of the abt message. 7. do not clear the rdy bit to 0 when the abttrg bit = 1. 8. if a message is received from another node while normal operation mode with abt is active, the tx-message from the abt-area may be transmitted with delay of one frame although cngmabtd register was set up with 00 h .
808 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.10.4 transmissi on abort process (1) transmission abort process except for in normal operation mode with automatic block transmission (abt) the user can clear the trq bit of the cnmctrlm register to 0 to abort a transmission request. the trq bit will be cleared immediately if the abort was successful. whether the transmission was successfully aborted or not can be checked using the tstat bit of the cnctrl register and the cntgpt register, which indicate the transmission status on the can bus (for details, refer to the processing in figure 20-45 on page 839 ). (2) transmission abort process except for abt transmission in normal operation mode with automatic block transmission (abt) the user can clear the abttrg bit of the cngmabt register to 0 to abort a transmission request. after checking the abttrg bit of the cngmabt register = 0, clear the trq bit of the cnmctrlm register to 0. the trq bit will be cleared immediately if the abort was successful. whether the transmission was successfully aborted or not can be checked using the tstat bit of the cnctrl register and the cntgpt register, which indicate the transmission status on the can bus (for details, refer to the processing in figure 20-46 on page 840 ). (3) transmission abort process for abt transmission in normal operation mode with automatic block transmission (abt) to abort abt that is already started, clear the abttrg bit of the cngmabt register to 0. in this case, the abttrg bit remains 1 if an abt message is currently being transmitted and until the transmission is completed (successfully or not), and is cleared to 0 as soon as transmission is finished. this aborts abt. if the last transmission (before abt) was successful, the normal operation mode with abt is left with the internal abt pointer pointing to the next message buffer to be transmitted. in the case of an erroneous transmission, the position of the internal abt pointer depends on the status of the trq bit in the last transmitted message buffer. if the trq bit is set to 1 when clearing the abttrg bit is requested, the internal abt pointer points to the last transmitted message buffer (for details, refer to the process in figure 20-47 on page 841 ). if the trq bit is cleared to 0 when clearing the abttrg bit is requested, the internal abt pointer is incremented (+1) and points to the next message buffer in the abt area (for details, refer to the process in figure 20-48 on page 842 ). caution be sure to abort abt by clearing abttrg bit to 0. the operation is not guaranteed if aborting transmission is requested by clearing rdy.
809 can controller (can) chapter 20 user?s manual u17566ee5v1um00 when the normal operation mode with abt is resumed after abt has been aborted and the abttrg bit is set to 1, the next abt message buffer to be transmitted can be determined from the following table. 20.10.5 remote frame transmission remote frames can be transmitted only from transmit message buffers. set whether a data frame or remote frame is transmitted via the rtr bit of the cnmconfm register. setting (1) the rtr bit sets remote frame transmission. status of trq of abt message buffer abort after successful transmission abort after erroneous transmission set (1) next message buffer in the abt area a a) the above resumption operation can be performed only if a message buffer ready for abt exists in the abt area. for example, an abort request that is issued while abt of message buffer 7 is in progress is regarded as completion of abt, rather than abort, if transmission of message buffer 7 has been successfully completed, even if the abttrg bit is cleared to 0. if the rdy bit in the next message buffer in the abt area is cleared to 0, the internal abt pointer is retained, but the resumption operation is not performed even if the abttrg bit is set to 1, and abt ends immediately. same message buffer in the abt area cleared (0) next message buffer in the abt area a next message buffer in the abt area a
810 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.11 power saving modes 20.11.1 can sleep mode the can sleep mode can be used to set the can controller to stand-by mode in order to reduce power consumption. the can module can enter the can sleep mode from all operation modes. release of the can sleep mode returns the can module to exactly the same operation mode from which the can sleep mode was entered. in the can sleep mode, the can module does not transmit messages, even when transmission requests are issued or pending. (1) entering can sleep mode the cpu issues a can sleep mode transition request by writing 01 b to the psmode[1:0] bits of the cnctrl register. this transition request is only acknowledged only under the following conditions. 3. the can module is already in one of the following operation modes ? normal operation mode ? normal operation mode with abt ? receive-only mode ? single-shot mode ? self-test mode ? can stop mode in all the above operation modes 4. the can bus state is bus idle (the 4th bit in the interframe space is reces- sive). if the can bus is fixed to dominant, the request for transition to the can sleep mode is held pending.also the transition from can stop mode to can sleep mode is independent of the can bus state. 5. no transmission request is pending note if a sleep mode request is pending, and at the same time a message is received in a message box, the sleep mode request is not cancelled, but is executed right after message storage has been finished. this may result in afcan being in sleep mode, while the cpu would execute the rx interrupt routine. therefore, the interrupt routine must check the access to the message buffers as well as reception history list registers by using the mbon flag, if sleep mode is used. if any one of the conditions mentioned above is not met, the can module will operate as follows. ? if the can sleep mode is requested from the initialization mode, the can sleep mode transition request is ignored and the can module remains in the initialization mode. ? if the can bus state is not bus idle (i.e., the can bus state is either transmitting or receiving) when the can sleep mode is requested in one of the operation modes, immediate transition to the can sleep mode is not possible. in this case, the can sleep mode transition request has to be held pending until the can bus state becomes bus idle (the 4th bit in the interframe space is recessive). in the time from the can sleep mode request to successful transition, the psmode[1:0] bits remain 00 b . when
811 can controller (can) chapter 20 user?s manual u17566ee5v1um00 the module has entered the can sleep mode, the psmode[1:0] bits are set to 01 b . ? if a request for transition to the initialization mode and a request for transition to the can sleep mode are made at the same time while the can module is in one of the operation modes, the request for the initialization mode is enabled. the can module enters the initialization mode at a predetermined timing. at this time, the can sleep mode request is not held pending and is ignored. ? even when initialization mode and sleep mode are not requested simultaneously (i.e the first request has not been granted while the second request is made), the request for initialization has priority over the sleep mode request. the sleep mode request is cancelled when the initialization mode is requested. when a pending request for initialization mode is present, a subsequent request for sleep mode request is cancelled right at the point in time where it was submitted. (2) status in can sleep mode the can module is in the following state after it enters the can sleep mode: ? the internal operating clock is stopped and the power consumption is minimized. ? the function to detect the falling edge of the can reception pin (crxdn) remains in effect to wake up the can module from the can bus. ? to wake up the can module from the cpu, data can be written to the psmode[1:0] bits of the can module control register (cnctrl), but nothing can be written to other can module registers or bits. ? the can module registers can be read, except for the cnlipt, cnrgpt, cnlopt, and cntgpt registers. ? the can message buffer registers cannot be written or read. ? mbon bit of the can global control register (cngmctrl) is cleared. ? a request for transition to the initialization mode is not acknowledged and is ignored.
812 chapter 20 can controller (can) user?s manual u17566ee5v1um00 (3) releasing can sleep mode the can sleep mode is released by the following events: ? when the cpu writes 00 b to the psmode[1:0] bits of the cnctrl register ? a falling edge at the can reception pin (crxdn) (i.e. the can bus level shifts from recessive to dominant) caution even if the falling edge belongs to the sof of a receive message, this message will not be received and stored. if the cpu has turned off the clock supply to the can module while the can module was in sleep mode, even subsequently the can sleep mode will not be released and psmode [1:0] will remain 01 b unless the clock to the can module is supplied again. in addition to this, the receive message will not be received after that. after releasing the sleep mode, the can module returns to the operation mode from which the can sleep mode was requested and the psmode[1:0] bits of the cnctrl register must be reset by software to 00 b . if the can sleep mode is released by a change in the can bus state, the cints5 bit of the cnints register is set to 1, regardless of the cie bit of the cnie register. after the can module is released from the can sleep mode, it participates in the can bus again by automatically detecting 11 consecutive recessive-level bits on the can bus. the user application has to wait until mbon = 1, before accessing message buffers again. when a request for transition to the initialization mode is made while the can module is in the can sleep mode, that request is ignored; the can module has to be released from sleep mode by software first before entering the initialization mode. caution 1. be aware that the release of can sleep mode by can bus event, and thus the wake up interrupt may happen at any time, even right after requesting sleep mode, if a can bus event occurs. 2. always reset the psmode[1:0] bits to 00 b , when waking up from can sleep mode, before accessing any other registers of the can module. 3. always clear the interrupt flag cints5, when waking up from can sleep mode.
813 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.11.2 can stop mode the can stop mode can be used to set the can controller to stand-by mode to reduce power consumption. the can module can enter the can stop mode only from the can sleep mode. release of the can stop mode puts the can module in the can sleep mode. the can stop mode can only be released (entering can sleep mode) by writing 01 b to the psmode[1:0] bits of the cnctrl register and not by a change in the can bus state. no message is transmitted even when transmission requests are issued or pending. (1) entering can stop mode a can stop mode transition request is issued by writing 11 b to the psmode[1:0] bits of the cnctrl register. a can stop mode request is only acknowledged when the can module is in the can sleep mode. in all other modes, the request is ignored. caution to set the can module to the can stop mode, the module must be in the can sleep mode. to confirm that the module is in the sleep mode, check that the psmode[1:0] bits = 01 b , and then request the can stop mode. if a bus change occurs at the can reception pin (crxdn) while this process is being performed, the can sleep mode is automatically released. in this case, the can stop mode transition request cannot be acknowledged. (2) status in can stop mode the can module is in the following state after it enters the can stop mode. ? the internal operating clock is stopped and the power consumption is minimized. ? to wake up the can module from the cpu, data can be written to the psmode[1:0] bits of the can module control register (cnctrl), but nothing can be written to other can module registers or bits. ? the can module registers can be read, except for the cnlipt, cnrgpt, cnlopt, and cntgpt registers. ? the can message buffer registers cannot be written or read. ? mbon bit of the can global control register (cngmctrl) is cleared. ? an initialization mode transition request is not acknowledged and is ignored. (3) releasing can stop mode the can stop mode can only be released by writing 01 b to the psmode[1:0] bits of the cnctrl register. after releasing the can stop mode, the can module enters the can sleep mode. when the initialization mode is requested while the can module is in the can stop mode, that request is ignored; the cpu has to release the stop mode and subsequently can sleep mode before entering the initialization mode. it is impossible to enter the other operation mode directly from the can stop mode not entering the can sleep mode, that request is ignored.
814 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.11.3 example of us ing power saving modes in some application systems, it may be necessary to place the cpu in a power saving mode to reduce the power consumption. by using the power saving mode specific to the can module and the power saving mode specific to the cpu in combination, the cpu can be woken up from the power saving status by the can bus. here is an example for using the power saving modes. ? first, put the can module in the can sleep mode (psmode[1:0] = 01 b ). next, put the cpu in the power saving mode. if an edge transition from recessive to dominant is detected at the can reception pin (crxdn) in this status, the cints5 bit in the can module is set to 1. if the cie5 bit of the cnctrl register is set to 1, a wakeup interrupt (intwupn) is generated. ? the can module is automatically released from can sleep mode (psmode = 00 b ) and returns to normal operation mode. ? the cpu, in response to intwupn, can release its own power saving mode and return to normal operation mode. to further reduce the power consumption of the cpu, the internal clock - including that of the can module - may be stopped. in this case, the operating clock supplied to the can module is stopped after the can module has been put in can sleep mode. then the cpu enters a power saving mode in which the clock supplied to the cpu is stopped. ? if an edge transition from recessive to dominant is detected at the can reception pin (crxdn) in this status, the can module can set the cints5 bit to 1 and generate the wakeup interrupt (intwupn) even if it is not supplied with the clock. ? the other functions, however, do not operate, because clock supply to the can module is stopped, and the module remains in can sleep mode. ? the cpu, in response to intwupn ? releases its power saving mode, ? resumes supply of the internal clocks - including the clock to the can module - after the oscillation stabilization time has elapsed, and ? starts instruction execution. ? the can module is immediately released from the can sleep mode when clock supply is resumed, and returns to the normal operation mode (psmode = 00 b ).
815 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.12 interrupt function the can module provides 6 different interrupt sources. the occurrence of these interrupt sources is stored in interrupt status registers. four separate interrupt request signals are generated from the six interrupt sources. when an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register. after an interrupt source has occurred, the corresponding interrupt status bit must be cleared to 0 by software. table 20-25 list of can module interrupt sources supplements 1. this interrupt is generated when the transmission/reception error counter is at the warning level, or in the error passive or bus-off state. 2. this interrupt is generated when a stuff error, form error, ack error, bit error, or crc error occurs. 3. this interrupt is generated when the can module is woken up from the can sleep mode because a falling edge is detected at the can reception pin (can bus transition from recessive to dominant). no. interrupt status bit interrupt enable bit interrupt request signal interrupt source description name register name register 1 cints0 cnints cie0 a a) the ie bit (message buffer interrupt enable bit) in the cnmctrl register of the corresponding message buffer has to be set to 1 for that message buffer to participate in the interrupt generation process . cnie intcntrx message frame successfully transmitted from message buffer m 2 cints1 cnints cie1 a cnie intcnrec valid message frame reception in message buffer m 3 cints2 cnints cie2 cnie intcnerr can module error state interrupt (supplement 1) 4 cints3 cnints cie3 cnie can module protocol error interrupt (supplement 2) 5 cints4 cnints cie4 cnie can module arbitration loss interrupt 6 cints5 cnints cie5 cnie intcnwup can module wakeup interrupt from can sleep mode (supplement 3)
816 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.13 diagnosis functions and special operational modes the can module provides a receive-only mode, single-shot mode, and self- test mode to support can bus diagnosis functions or the operation of special can communication methods. 20.13.1 receive-only mode the receive-only mode is used to monitor receive messages without causing any interference on the can bus and can be used for can bus analysis nodes. for example, this mode can be used for automatic baud-rate detection. the baud rate in the can module is changed until ?valid reception? is detected, so that the baud rates in the module match (?valid reception? means a message frame has been received in the can protocol layer without occurrence of an error and with an appropriate ack between nodes connected to the can bus). a valid reception does not require message frames to be stored in a receive message buffer (data frames) or transmit message buffer (remote frames). the event of valid reception is indicated by setting the valid bit of the cnctrl register (1). figure 20-32 can module terminal connection in receive-only mode in the receive-only mode, no message frames can be transmitted from the can module to the can bus. transmit requests issued for message buffers defined as transmit message buffers are held pending. in the receive-only mode, the can transmission pin (ctxdn) in the can module is fixed to the recessive level. therefore, no active error flag can be transmitted from the can module to the can bus even when a can bus error is detected while receiving a message frame. since no transmission can be issued from the can module, the transmission error counter the cnerc.tec7 to cnerc.tec0 bits are never updated. therefore, a can module in the receive-only mode does not enter the bus-off state. can macro rx tx ctxdn crxdn fixed to the recessive level
817 can controller (can) chapter 20 user?s manual u17566ee5v1um00 furthermore, in the receive-only mode ack is not returned to the can bus in this mode upon the valid reception of a message frame. internally, the local node recognizes that it has transmitted ack. an overload frame cannot be transmitted to the can bus. caution if only two can nodes are connected to the can bus and one of them is operating in the receive-only mode, there is no ack on the can bus. due to the missing ack, the transmitting node will transmit an active error flag, and repeat transmitting a message frame. the transmitting node becomes error passive after transmitting the message frame 16 times (assuming that the error counter was 0 in the beginning and no other errors have occurred). after the message frame for the 17th time is transmitted, the transmitting node generates a passive error flag. the receiving node in the receive-only mode detects the first valid message frame at this point, and the valid bit is set to 1 for the first time. 20.13.2 single-shot mode in the single-shot mode, automatic re-transmission as defined in the can protocol is switched off. (according to the can protocol, a message frame transmission that has been aborted by either arbitration loss or error occurrence has to be repeated without control by software.) all other behavior of single shot mode is identical to normal operation mode. features of single shot mode can not be used in combination with normal mode with abt. the single-shot mode disables the re-transmission of an aborted message frame transmission according to the setting of the al bit of the cnctrl register. when the al bit is cleared to 0, re-transmission upon arbitration loss and upon error occurrence is disabled. if the al bit is set to 1, re-transmission upon error occurrence is disabled, but re-transmission upon arbitration loss is enabled. as a consequence, the trq bit in a message buffer defined as a transmit message buffer is cleared to 0 by the following events: ? successful transmission of the message frame ? arbitration loss while sending the message frame ? error occurrence while sending the message frame the events arbitration loss and error occurrence can be distinguished by checking the cints4 and cints3 bits of the cnints register respectively, and the type of the error can be identified by reading the lec[2:0] bits of the cnlec register. upon successful transmission of the message frame, the transmit completion interrupt bit cints0 of the cnints register is set to 1. if the cie0 bit of the cnie register is set to 1 at this time, an interrupt request signal is output.
818 chapter 20 can controller (can) user?s manual u17566ee5v1um00 the single-shot mode can be used when emulating time-triggered communication methods (e.g., ttcan level 1). caution the al bit is only valid in single-shot mode. it does not influence the operation of re-transmission upon arbitration loss in the other operation modes. 20.13.3 self-test mode in the self-test mode, message frame transmission and message frame reception can be tested without connecting the can node to the can bus or without affecting the can bus. in the self-test mode, the can module is completely disconnected from the can bus, but transmission and reception are internally looped back. the can transmission pin (ctxdn) is fixed to the recessive level. if the falling edge on the can reception pin (crxdn) is detected after the can module has entered the can sleep mode from the self-test mode, however, the module is released from the can sleep mode in the same manner as the other operation modes. to keep the module in the can sleep mode, use the can reception pin (crxdn) as a port pin. figure 20-33 can module terminal connection in self-test mode can macro rx tx ctxdn crxdn fixed to the recessive level
819 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.13.4 receive/transmit ope ration in each operation mode the following table shows outline of the receive/transmit operation in each operation mode. table 20-26 outline of the receive/transmit in each operation mode operation mode transmis- sion of data/ remote frame transmis- sion of ack transmis- sion of error/ overload frame transmis- sion retry automatic block transmis- sion (abt) set of valid bit store data to message buffer initialization mode no no no no no no no normal operation mode yes yes yes yes no yes yes normal operation mode with abt yes yes yes yes yes yes yes receive only mode no no no no no yes yes single-shot mode ye s ye s ye s n o a a) when the arbitration lost occurs, control of re-transmission is possible by the al bit of cnctrl register. no yes yes self-test mode ye s b b) each signals are not generated to outside, but generated into the can module. ye s b ye s b ye s b no yes b ye s b
820 chapter 20 can controller (can) user?s manual u17566ee5v1um00 20.14 time stamp function can is an asynchronous, serial protocol. all nodes connected to the can bus have a local, autonomous clock. as a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may have different frequencies). in some applications, however, a common time base over the network (= global time base) is needed. in order to build up a global time base, a time stamp function is used. the essential mechanism of a time stamp function is the capture of timer values triggered by signals on the can bus. 20.14.1 time stamp function the can controller supports the capturing of timer values triggered by a specific frame. an on-chip 16-bit capture timer unit in a microcontroller system is used in addition to the can controller. the 16-bit capture timer unit captures the timer value according to a trigger signal (tsout) for capturing that is output when a data frame is received from the can controller. the cpu can retrieve the time of occurrence of the capture event, i.e., the time stamp of the message received from the can bus, by reading the captured value. the tsout signal can be selected from the following two event sources and is specified by the tssel bit of the cnts register. ? sof event (start of frame) (tssel = 0) ? eof event (last bit of end of frame) (tssel = 1) the tsout signal is enabled by setting the tsen bit of the cnts register to 1. figure 20-34 timing diagram of capture signal tsout the tsout signal toggles its level upon occurrence of the selected event during data frame reception (in figure 20-34 , the sof is used as the trigger event source). to capture a timer value by using the tsout signal, the capture timer unit must detect the capture signal at both the rising edge and falling edge. this time stamp function is controlled by the tslock bit of the cnts register. when tslock is cleared to 0, the tsout signal toggles upon occurrence of the selected event. if tslock is set to 1, the tsout signal toggles upon occurrence of the selected event, but the toggle is stopped as the tsen bit is automatically cleared to 0 as soon as the message storing to the message buffer 0 starts. this suppresses the subsequent toggle occurrence by the tsout signal, so that the time stamp value toggled last (= captured last) can be saved as the time stamp value of the time at which the data frame was received in message buffer 0. t tsout sof sof sof sof
821 can controller (can) chapter 20 user?s manual u17566ee5v1um00 caution the time stamp function using the tslock bit stops toggle of the tsout signal by receiving a data frame in message buffer 0. therefore, message buffer 0 must be set as a receive message buffer. since a receive message buffer cannot receive a remote frame, toggle of the tsout signal cannot be stopped by reception of a remote frame. toggle of the tsout signal does not stop when a data frame is received in a message buffer other than message buffer 0. for these reasons, a data frame cannot be received in message buffer 0 when the can module is in the normal operation mode with abt, because message buffer 0 must be set as a transmit message buffer. in this operation mode, therefore, the function to stop toggle of the tsout signal by the tslock bit cannot be used. 20.15 baud rate settings 20.15.1 baud rate setting conditions make sure that the settings are within the range of limit values for ensuring correct operation of the can controller, as follows. ?5tq  spt (sampling point)  17 tq spt = tseg1 + 1 ?8 tq  dbt (data bit time)  25 tq dbt = tseg1 + tseg2 + 1tq = tseg2 + spt ?1 tq  sjw (synchronization jump width)  4tq sjw  dbt ? spt ?4  tseg1  16 [3  setting value of tseg1[3:0]  15] ?1  tseg2  8 [0  setting value of tseg2[2:0]  7] note 1. tq = 1/f tq (f tq : can protocol layer basic system clock) 2. tseg1[3:0] (bits 3 to 0 of can bit rate register (cnbtr)) 3. tseg2[2:0] (bits 10 to 8 of can bit rate register (cnbtr))
822 chapter 20 can controller (can) user?s manual u17566ee5v1um00 table 20-27 shows the combinations of bit rates that satisfy the above conditions. table 20-27 settable bit rate combinations (1/3) valid bit rate setting cnbtr register setting value sampling point (unit %) dbt length sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0] 25 1 8 8 8 1111 111 68.0 24 1 7 8 8 1110 111 66.7 24 1 9 7 7 1111 110 70.8 23 1 6 8 8 1101 111 65.2 23 1 8 7 7 1110 110 69.6 23 1 10 6 6 1111 101 73.9 22 1 5 8 8 1100 111 63.6 22 1 7 7 7 1101 110 68.2 22 1 9 6 6 1110 101 72.7 22 1 11 5 5 1111 100 77.3 21 1 4 8 8 1011 111 61.9 21 1 6 7 7 1100 110 66.7 21 1 8 6 6 1101 101 71.4 21 1 10 5 5 1110 100 76.2 21 1 12 4 4 1111 011 81.0 20 1 3 8 8 1010 111 60.0 20 1 5 7 7 1011 110 65.0 20 1 7 6 6 1100 101 70.0 20 1 9 5 5 1101 100 75.0 20 1 11 4 4 1110 011 80.0 20 1 13 3 3 1111 010 85.0 19 1 2 8 8 1001 111 57.9 19 1 4 7 7 1010 110 63.2 19 1 6 6 6 1011 101 68.4 19 1 8 5 5 1100 100 73.7 19 1 10 4 4 1101 011 78.9 19 1 12 3 3 1110 010 84.2 19 1 14 2 2 1111 001 89.5 18 1 1 8 8 1000 111 55.6 18 1 3 7 7 1001 110 61.1 18 1 5 6 6 1010 101 66.7 18 1 7 5 5 1011 100 72.2 18 1 9 4 4 1100 011 77.8 18 1 11 3 3 1101 010 83.3 18 1 13 2 2 1110 001 88.9 18 1 15 1 1 1111 000 94.4 17 1 2 7 7 1000 110 58.8
823 can controller (can) chapter 20 user?s manual u17566ee5v1um00 17 1 4 6 6 1001 101 64.7 17 1 6 5 5 1010 100 70.6 17 1 8 4 4 1011 011 76.5 17 1 10 3 3 1100 010 82.4 17 1 12 2 2 1101 001 88.2 17 1 14 1 1 1110 000 94.1 16 1 1 7 7 0111 110 56.3 16 1 3 6 6 1000 101 62.5 16 1 5 5 5 1001 100 68.8 16 1 7 4 4 1010 011 75.0 16 1 9 3 3 1011 010 81.3 16 1 11 2 2 1100 001 87.5 16 1 13 1 1 1101 000 93.8 15 1 2 6 6 0111 101 60.0 15 1 4 5 5 1000 100 66.7 15 1 6 4 4 1001 011 73.3 15 1 8 3 3 1010 010 80.0 15 1 10 2 2 1011 001 86.7 15 1 12 1 1 1100 000 93.3 14 1 1 6 6 0110 101 57.1 14 1 3 5 5 0111 100 64.3 14 1 5 4 4 1000 011 71.4 14 1 7 3 3 1001 010 78.6 14 1 9 2 2 1010 001 85.7 14 1 11 1 1 1011 000 92.9 13 1 2 5 5 0110 100 61.5 13 1 4 4 4 0111 011 69.2 13 1 6 3 3 1000 010 76.9 13 1 8 2 2 1001 001 84.6 13 1 10 1 1 1010 000 92.3 12 1 1 5 5 0101 100 58.3 12 1 3 4 4 0110 011 66.7 12 1 5 3 3 0111 010 75.0 table 20-27 settable bit rate combinations (2/3) valid bit rate setting cnbtr register setting value sampling point (unit %) dbt length sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0]
824 chapter 20 can controller (can) user?s manual u17566ee5v1um00 caution the values in table 20-27 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. 12 1 7 2 2 1000 001 83.3 12 1 9 1 1 1001 000 91.7 11 1 2 4 4 0101 011 63.6 11 1 4 3 3 0110 010 72.7 11 1 6 2 2 0111 001 81.8 11 1 8 1 1 1000 000 90.9 10 1 1 4 4 0100 011 60.0 10 1 3 3 3 0101 010 70.0 10 1 5 2 2 0110 001 80.0 10 1 7 1 1 0111 000 90.0 9 1 2 3 3 0100 010 66.7 9 1 4 2 2 0101 001 77.8 9 1 6 1 1 0110 000 88.9 8 1 1 3 3 0011 010 62.5 8 1 3 2 2 0100 001 75.0 8 1 5 1 1 0101 000 87.5 7 a 1 2 2 2 0011 001 71.4 7 a 1 4 1 1 0100 000 85.7 6 a 1 1 2 2 0010 001 66.7 6 a 1 3 1 1 0011 000 83.3 5 a 1 2 1 1 0010 000 80.0 4 a 1 1 1 1 0001 000 75.0 a) setting with a dbt value of 7 or less is valid only when the value of the cnbrp register is other than 00 h . table 20-27 settable bit rate combinations (3/3) valid bit rate setting cnbtr register setting value sampling point (unit %) dbt length sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0]
825 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.15.2 representative examples of baud rate settings table 20-28 and table 20-29 show representative examples of baud rate settings. table 20-28 representative examples of baud rate settings (f canmod = 8 mhz) (1/2) set baud rate value (unit: kbps) division ratio of cnbrp register cnbrp register set value valid bit rate setting (unit: kbps) cnbtr register setting value sampling point (unit: %) length of dbt sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0] 100010000000081133001101062.5 100010000000081322010000175.0 100010000000081511010100087.5 500100000000161177011111056.3 500100000000161366100010162.5 500100000000161555100110068.8 500100000000161744101001175.0 500100000000161933101101081.3 500 1 00000000 16 1 11 2 2 1100 001 87.5 500 1 00000000 16 1 13 1 1 1101 000 93.8 50020000000181133001101062.5 50020000000181322010000175.0 50020000000181511010100087.5 250200000001161177011111056.3 250200000001161366100010162.5 250200000001161555100110068.8 250200000001161744101001175.0 250200000001161933101101081.3 250 2 00000001 16 1 11 2 2 1100 001 87.5 250 2 00000001 16 1 13 1 1 1101 000 93.8 25040000001181322010000175.0 25040000001181511010100087.5 125400000011161177011111056.3 125400000011161366100010162.5 125400000011161555100110068.8 125400000011161744101001175.0 125400000011161933101101081.3 125 4 00000011 16 1 11 2 2 1100 001 87.5 125 4 00000011 16 1 13 1 1 1101 000 93.8 12580000011181322010000175.0 12580000011181511010100087.5 100400000011201766110010170.0 100400000011201955110110075.0 100500000100161744101001175.0 100500000100161933101101081.3
826 chapter 20 can controller (can) user?s manual u17566ee5v1um00 caution the values in table 20-28 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. 100800000111101333010101070.0 100800000111101522011000180.0 100100000100181322010000175.0 100100000100181511010100087.5 83.3400000011241788111011166.7 83.3400000011241977111111070.8 83.3600000101161555100110068.8 83.3600000101161744101001175.0 83.3600000101161933101101081.3 83.3 6 00000101 16 1 11 2 2 1100 001 87.5 83.3800000111121533011101075.0 83.3800000111121722100000183.3 83.3120000101181322010000175.0 83.3120000101181511010100087.5 33.31000001001241788111011166.7 33.31000001001241977111111070.8 33.31200001011201766110010170.0 33.31200001011201955110110075.0 33.31500001110161744101001175.0 33.31500001110161933101101081.3 33.31600001111151644100101173.3 33.31600001111151833101001080.0 33.32000010011121533011101075.0 33.32000010011121722100000183.3 33.32400010111101333010101070.0 33.32400010111101522011000180.0 33.3300001110181322010000175.0 33.3300001110181511010100087.5 table 20-28 representative examples of baud rate settings (f canmod = 8 mhz) (2/2) set baud rate value (unit: kbps) division ratio of cnbrp register cnbrp register set value valid bit rate setting (unit: kbps) cnbtr register setting value sampling point (unit: %) length of dbt sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0]
827 can controller (can) chapter 20 user?s manual u17566ee5v1um00 table 20-29 representative examples of baud rate settings (f canmod = 16 mhz) (1/2) set baud rate value (unit: kbps) division ratio of cnbrp register cnbrp register set value valid bit rate setting (unit: kbps) cnbtr register setting value sampling point (unit: %) length of dbt sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0] 1000100000000161177011111056.3 1000100000000161366100010162.5 1000100000000161555100110068.8 1000100000000161744101001175.0 1000100000000161933101101081.3 1000 1 00000000 16 1 11 2 2 1100 001 87.5 1000 1 00000000 16 1 13 1 1 1101 000 93.8 100020000000181322010000175.0 100020000000181511010100087.5 500200000001161177011111056.3 500200000001161366100010162.5 500200000001161555100110068.8 500200000001161744101001175.0 500200000001161933101101081.3 500 2 00000001 16 1 11 2 2 1100 001 87.5 500 2 00000001 16 1 13 1 1 1101 000 93.8 50040000001181322010000175.0 50040000001181511010100087.5 250400000011161366100010162.5 250400000011161555100110068.8 250400000011161744101001175.0 250400000011161933101101081.3 250 4 00000011 16 1 11 2 2 1100 001 87.5 25080000011181322010000175.0 25080000011181511010100087.5 125800000111161366100010162.5 125800000111161744101001175.0 125800000111161933101101081.3 125 8 00000111 16 1 11 2 2 1100 001 87.5 125160000111181322010000175.0 125160000111181511010100087.5 100800000111201955110110075.0 100 8 00000111 20 1 11 4 4 1110 011 80.0 1001000001001161744101001175.0 1001000001001161933101101081.3 1001600001111101333010101070.0 1001600001111101522011000180.0 100200001001181322010000175.0
828 chapter 20 can controller (can) user?s manual u17566ee5v1um00 caution the values in table 20-29 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. 83.3800000111241788111011166.7 83.3800000111241977111111070.8 83.31200001011161744101001175.0 83.31200001011161933101101081.3 83.3 12 00001011 16 1 11 2 2 1100 001 87.5 83.31600001111121533011101075.0 83.31600001111121722100000183.3 83.3240001011181322010000175.0 83.3240001011181511010100087.5 33.33000011101241788111011166.7 33.33000011101241977111111070.8 33.32400010111201955110110075.0 33.3 24 00010111 20 1 11 4 4 1110 011 80.0 33.33000011101161744101001175.0 33.33000011101161933101101081.3 33.33200011111151833101001080.0 33.3 32 00011111 15 1 10 2 2 1011 001 86.7 33.33700100100131633100001076.9 33.33700100100131822100100184.6 33.34000100111121533011101075.0 33.34000100111121722100000183.3 33.34800101111101333010101070.0 33.34800101111101522011000180.0 33.3600011101181322010000175.0 33.3600011101181511010100087.5 table 20-29 representative examples of baud rate settings (f canmod = 16 mhz) (2/2) set baud rate value (unit: kbps) division ratio of cnbrp register cnbrp register set value valid bit rate setting (unit: kbps) cnbtr register setting value sampling point (unit: %) length of dbt sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0]
829 can controller (can) chapter 20 user?s manual u17566ee5v1um00 20.16 operation of can controller the processing procedure for showing in this chapter is recommended processing procedure to operate can controller. develop the program referring to recommended processing procedure in this chapter. figure 20-35 initialization start set cngmcs register. set cnbrp register, cnbtr register. set cnie register. set cnmask register. initialize message buffers. set cnctrl register (set opmode bit). end set cngmctrl register (set gom bit = 1) opmode: normal operation mode, normal operation mode with abt, receive-only mode, single-shot mode, self-test mode
830 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-36 re-initialization caution after setting the can module to the initialization mode, avoid setting the module to another operation mode immediately after. if it is necessary to immediately set the module to another operation mode, be sure to access registers other than the cnctrl and cngmctrl registers (e.g., set a message buffer). s tart s et cnbrp regi s ter, cnbtr regi s ter s et cnie regi s ter s et cnma s k regi s ter s et cnctrl regi s ter ( s et opmode) end cle a r opmode init mode? no ye s s et ccerc b it ye s no initi a lize me ssa ge bu ffer s cnerc a nd cninfo regi s ter cle a r? s tart s et cnbrp regi s ter, cnbtr regi s ter s et cnie regi s ter s et cnma s k regi s ter s et cnctrl regi s ter ( s et opmode) end cle a r opmode init mode? no s et ccerc b it ye s no initi a lize me ssa ge bu ffer s cnerc a nd cninfo regi s ter cle a r? opmode: normal operation mode, normal operation mode with abt, receive-only mode, single-shot mode, self-test mode
831 can controller (can) chapter 20 user?s manual u17566ee5v1um00 figure 20-37 message buffer initialization caution 1. before a message buffer is initialized, the rdy bit must be cleared. 2. make the following settings for message buffers not used by the application. ? clear the rdy, trq, and dn bits of the cnmctrlm register to 0. ? clear the ma0 bit of the cnmconfm register to 0. s tart s et cnmconfm regi s ter end rdy = 1? no ye s cle a r rdy b it rdy = 0? s et cnmidhm regi s ter, cnmidlm regi s ter tr a n s mit me ssa ge bu ffer? cle a r cnmdatam regi s ter s et cnmctrlm regi s ter s et rdy b it s et cnmdlcm regi s ter no no ye s ye s s tart s et cnmconfm regi s ter end rdy = 1? no ye s cle a r rdy b it rdy = 0? s et cnmidhm regi s ter, cnmidlm regi s ter tr a n s mit me ssa ge bu ffer? cle a r cnmdatam regi s ter s et cnmctrlm regi s ter s et rdy b it s et cnmdlcm regi s ter no no ye s ye s
832 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-38 shows the processing for a receive message buffer (mt[2:0] bits of cnmconfm register = 001 b to 101 b ). figure 20-38 message buffer redefinition s tart s et me ssa ge bu ffer s end rdy = 1? no ye s cle a r rdy b it rdy = 0? no cle a r valid b it s et rdy b it ye s ye s no w a it for 4 can d a t a b it s note2 r s tat = 0 or valid = 1? note1 note1: confirm th a t a me ssa ge i s b eing received b ec aus e rdy b it m us t b e s et a fter a me ssa ge i s completely received. note2: avoid me ssa ge bu ffer redefinition d u ring s tore oper a tion of me ssa ge reception b y w a iting a ddition a l 4 can d a t a b it s .
833 can controller (can) chapter 20 user?s manual u17566ee5v1um00 figure 20-39 shows the processing for a transmit message buffer during transmission (mt[2:0] bits of cnmconfm register = 000 b ). figure 20-39 message buffer redefinition during transmission s tart end rdy = 0? no ye s d a t a fr a me or remote fr a me? s et rdy b it s et cnmdataxm regi s ter s et cnmdlcm regi s ter cle a r rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s s et cnmdlcm regi s ter s et rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s remote fr a me d a t a fr a me tr a n s mit ab ort proce ss cle a r rdy b it tr a n s mit? s et trq b it ye s w a it for 1can d a t a b it s no s tart end rdy = 0? no ye s d a t a fr a me or remote fr a me? s et rdy b it s et cnmdataxm regi s ter s et cnmdlcm regi s ter cle a r rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s s et cnmdlcm regi s ter s et rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s remote fr a me d a t a fr a me tr a n s mit ab ort proce ss cle a r rdy b it tr a n s mit? s et trq b it ye s w a it for 1can d a t a b it s no
834 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-40 shows the processing for a transmit message buffer (mt[2:0] bits of cnmconfm register = 000 b ). figure 20-40 message transmit processing caution 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. s tart end trq = 0? no ye s cle a r rdy b it rdy = 0? d a t a fr a me or remote fr a me? s et rdy b it ye s no s et cnmdataxm regi s ter s et cnmdlcm regi s ter cle a r rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s s et cnmdlcm regi s ter s et rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s s et trq b it remote fr a me d a t a fr a me s tart end trq = 0? no ye s cle a r rdy b it rdy = 0? d a t a fr a me or remote fr a me? s et rdy b it ye s no s et cnmdataxm regi s ter s et cnmdlcm regi s ter cle a r rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s s et cnmdlcm regi s ter s et rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s s et trq b it remote fr a me d a t a fr a me
835 can controller (can) chapter 20 user?s manual u17566ee5v1um00 figure 20-41 shows the processing for a transmit message buffer (mt[2:0] bits of cnmconfm register = 000 b ) figure 20-41 abt message transmit processing note this processing (normal operation mode with abt) can only be applied to message buffers 0 to 7. for message buffers other than the abt message buffers, see figure 20-40 on page 834 . caution the abttrg bit should be set to 1 after the tstat bit is cleared to 0. checking the tstat bit and setting the abttrg bit to 1 must be processed consecutively. s tart s et cnmdataxm regi s ter s et cnmdlcm regi s ter cle a r rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s end abttrg = 0? no ye s cle a r rdy b it rdy = 0? s et rdy b it ye s no s et abttrg b it s et a ll abt tr a n s mit me ssa ge s ? t s tat = 0? ye s no ye s no s tart s et cnmdataxm regi s ter s et cnmdlcm regi s ter cle a r rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s end abttrg = 0? no ye s cle a r rdy b it rdy = 0? s et rdy b it ye s no s et abttrg b it s et a ll abt tr a n s mit me ssa ge s ? t s tat = 0? ye s no ye s no
836 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-42 transmission via interrupt (using cnlopt register) caution 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. note also check the mbon flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as tx history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. it is recommended to cancel any sleep mode requests, before processing tx interrupts. s tart end cle a r rdy b it rdy = 0? d a t a fr a me or remote fr a me? s et rdy b it ye s no s et cnmdataxm regi s ter s et cnmdlcm regi s ter, cle a r rtr b it of cnmconfm regi s ter. s et cnmidlm a nd cnmidhm regi s ter s s et cnmdlcm regi s ter s et rtr b it of cnmconfm regi s ter. s et cnmidlm a nd cnmidhm regi s ter s s et trq b it remote fr a me d a t a fr a me tr a n s mit completion interr u pt proce ss ing re a d cnlopt regi s ter s tart end cle a r rdy b it rdy = 0? d a t a fr a me or remote fr a me? s et rdy b it ye s no s et cnmdataxm regi s ter s et cnmdlcm regi s ter, cle a r rtr b it of cnmconfm regi s ter. s et cnmidlm a nd cnmidhm regi s ter s s et cnmdlcm regi s ter s et rtr b it of cnmconfm regi s ter. s et cnmidlm a nd cnmidhm regi s ter s s et trq b it remote fr a me d a t a fr a me tr a n s mit completion interr u pt proce ss ing tr a n s mit completion interr u pt proce ss ing re a d cnlopt regi s ter
837 can controller (can) chapter 20 user?s manual u17566ee5v1um00 figure 20-43 transmission via interrupt (using cntgpt register) caution 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. note 1. also check the mbon flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as tx history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of s tart end tovf = 1? d a t a fr a me or remote fr a me? s et rdy b it ye s s et cnmdataxm regi s ter s et cnmdlcm regi s ter cle a r rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s s et cnmdlcm regi s ter s et rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s s et trq b it remote fr a me d a t a fr a me tr a n s mit completion interr u pt proce ss ing re a d cntgpt regi s ter cle a r tovf b it cle a r rdy b it rdy = 0? thpm = 1? no ye s no ye s s tart end tovf = 1? d a t a fr a me or remote fr a me? s et rdy b it no s et cnmdataxm regi s ter s et cnmdlcm regi s ter cle a r rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s s et cnmdlcm regi s ter s et rtr b it of cnmconfm regi s ter s et cnmidlm a nd cnmidhm regi s ter s s et trq b it remote fr a me d a t a fr a me tr a n s mit completion interr u pt proce ss ing tr a n s mit completion interr u pt proce ss ing re a d cntgpt regi s ter cle a r tovf b it cle a r rdy b it rdy = 0? thpm = 1? no ye s no ye s
838 chapter 20 can controller (can) user?s manual u17566ee5v1um00 the processing have to be discarded and processed again, after mbon is set again. it is recommended to cancel any sleep mode requests, before processing tx interrupts. 2. if tovf was set once, the transmit history list is inconsistent. consider to scan all configured transmit buffers for completed transmissions. figure 20-44 transmission via software polling caution 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. s tart end tovf = 1? d a t a fr a me or remote fr a me? s et rdy b it ye s no s et cnmdataxm regi s ter s et cnmdlcm regi s ter cle a r rtr b it of cnmconfm regi s ter. s et cnmidlm a nd cnmidhm regi s ter s s et cnmdlcm regi s ter s et rtr b it of cnmconfm s et cnmidlm a nd cnmidhm regi s ter s s et trq b it remote fr a me d a t a fr a me re a d cntgpt regi s ter cle a r tovf b it cle a r rdy b it rdy = 0? thpm = 1? no ye s no ye s cint s 0 = 1? no cle a r cint s 0 b it ye s s tart end tovf = 1? d a t a fr a me or remote fr a me? s et rdy b it ye s no s et cnmdataxm regi s ter s et cnmdlcm regi s ter cle a r rtr b it of cnmconfm regi s ter. s et cnmidlm a nd cnmidhm regi s ter s s et cnmdlcm regi s ter s et rtr b it of cnmconfm s et cnmidlm a nd cnmidhm regi s ter s s et trq b it remote fr a me d a t a fr a me re a d cntgpt regi s ter cle a r tovf b it cle a r rdy b it rdy = 0? thpm = 1? no ye s no ye s cint s 0 = 1? no cle a r cint s 0 b it ye s
839 can controller (can) chapter 20 user?s manual u17566ee5v1um00 note 1. also check the mbon flag at the beginning and at the end of the polling routine, in order to check the access to the message buffers as well as tx history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. 2. if tovf was set once, the transmit history list is inconsistent. consider to scan all configured transmit buffers for completed transmissions. figure 20-45 transmission abort processing (except normal operation mode with abt) note there is a possibility of starting the transmission without being aborted even if trq bit is cleared, because the transmission request to protocol layer might already been accepted between 11 bits, total of interframe space (3 bits) and suspend transmission (8 bits). caution 1. clear the trq bit for aborting transmission request, not the rdy bit. 2. before making a sleep mode transition request, confirm that there is no transmission request left using this processing. 3. the tstat bit can be periodically checked by a user application or can be checked after the transmit completion interrupt. 4. do not execute any new transmission request including in the other message buffers while transmission abort processing is in progress. s tart re a d cnlopt regi s ter end no ye s cle a r trq b it t s tat = 0? me ssa ge bu ffer to b e ab orted m a tche s cnlopt regi s ter? no w a it for 11 can d a t a b it s note tr a n s mi ss ion su cce ss f u l tr a n s mit ab ort re qu e s t w as su cce ss f u l ye s s tart re a d cnlopt regi s ter end no ye s cle a r trq b it t s tat = 0? me ssa ge bu ffer to b e ab orted m a tche s cnlopt regi s ter? no w a it for 11 can d a t a b it s note tr a n s mi ss ion su cce ss f u l tr a n s mi ss ion su cce ss f u l tr a n s mit ab ort re qu e s t w as su cce ss f u l tr a n s mit ab ort re qu e s t w as su cce ss f u l ye s
840 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-46 transmission abort processing except for abt transmission (normal operation mode with abt) caution 1. clear the trq bit for aborting transmission request, not the rdy bit. 2. before making a sleep mode transition request, confirm that there is no transmission request left using this processing. 3. the tstat bit can be periodically checked by a user application or can be checked after the transmit completion interrupt. 4. do not execute any new transmission request including in the other message buffers while transmission abort processing is in progress. s tart re a d cnlopt regi s ter end no ye s cle a r trq b it t s tat = 0? me ssa ge bu ffer to b e ab orted m a tche s cnlopt regi s ter? no w a it for 11 can d a t a b it s tr a n s mi ss ion su cce ss f u l tr a n s mit ab ort re qu e s t w as su cce ss f u l ye s no abttrg = 0? cle a r abttrg b it ye s s tart re a d cnlopt regi s ter end no ye s cle a r trq b it t s tat = 0? me ssa ge bu ffer to b e ab orted m a tche s cnlopt regi s ter? no w a it for 11 can d a t a b it s tr a n s mi ss ion su cce ss f u l tr a n s mi ss ion su cce ss f u l tr a n s mit ab ort re qu e s t w as su cce ss f u l tr a n s mit ab ort re qu e s t w as su cce ss f u l ye s no abttrg = 0? cle a r abttrg b it ye s
841 can controller (can) chapter 20 user?s manual u17566ee5v1um00 figure 20-47 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an abt message buffer was aborted. figure 20-47 transmission abort processing (normal operation mode with abt) caution 1. do not set any transmission requests while abt transmission abort processing is in progress. 2. make a can sleep mode/can stop mode transition request after the abttrg bit is cleared (after abt mode is aborted) following the procedure shown in figure 20-47 or figure 20-48 . when clearing a transmission request in an area other than the abt area, follow the procedure shown in figure 20-45 on page 839 . s tart end no cle a r abttrg b it abttrg = 0? tr a n s mi ss ion s t a rt no cle a r trq b it of me ssa ge bu ffer who s e tr a n s mi ss ion w as ab orted tr a n s mit ab ort ye s s et abtclr b it ye s no t s tat = 0? ye s s tart end no cle a r abttrg b it abttrg = 0? tr a n s mi ss ion s t a rt no cle a r trq b it of me ssa ge bu ffer who s e tr a n s mi ss ion w as ab orted tr a n s mit ab ort tr a n s mit ab ort ye s s et abtclr b it ye s no t s tat = 0? ye s
842 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-48 shows the processing to not skip resumption of transmitting a message that was stopped when transmission of an abt message buffer was aborted. figure 20-48 abt transmission request abort processing (normal operation mode with abt) caution 1. do not set any transmission requests while abt transmission abort processing is in progress. 2. make a can sleep mode/can stop mode request after the abttrg bit is cleared (after abt mode is stopped) following the procedure shown in figure 20-47 or figure 20-48 . when clearing a transmission request in an area other than the abt area, follow the procedure shown in figure 20-45 on page 839 . s tart end no cle a r abttrg b it abttrg = 0? tr a n s mi ss ion s t a rt pointer cle a r? no tr a n s mit ab ort ye s s et abtclr b it ye s cle a r trq b it of me ssa ge bu ffer u ndergoing tr a n s mi ss ion s tart end no cle a r abttrg b it abttrg = 0? tr a n s mi ss ion s t a rt pointer cle a r? no tr a n s mit ab ort tr a n s mit ab ort ye s s et abtclr b it ye s cle a r trq b it of me ssa ge bu ffer u ndergoing tr a n s mi ss ion
843 can controller (can) chapter 20 user?s manual u17566ee5v1um00 figure 20-49 reception via interrupt (using cnlipt register) note also check the mbon flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. it is recommended to cancel any sleep mode requests, before processing rx interrupts. s tart end no re a d cnmdataxm, cnmdlcm, cnmidlm, a nd cnmidhm regi s ter s dn = 0 and muc = 0 re a d cnlipt regi s ter ye s gener a tion of receive completion interr u pt cle a r dn b it note s tart end no re a d cnmdataxm, cnmdlcm, cnmidlm, a nd cnmidhm regi s ter s dn = 0 and muc = 0 re a d cnlipt regi s ter ye s gener a tion of receive completion interr u pt cle a r dn b it note note check the muc and dn bits using one read access.
844 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-50 reception via interrupt (using cnrgpt register) note 1. check the muc and dn bits using one read access. 2. depending of the processing target of the application, two ways are possible: ? way a: the message is not processed within this pass, but with the next pass, depending on the timing this can happen latest with the next receive interrupt. other messages will be processed earlier. ? way b: the message is processed within this pass, the loop waits on this message. other messages will be processed later. s tart cle a r rovf b it no rovf = 1? re a d cnrgpt regi s ter ye s gener a tion of receive completion interr u pt cle a r dn b it re a d cnmdataxm, cnmdlcm, cnmidlm, cnmidhm regi s ter s dn = 0 and muc = 0 note 1 rhpm = 1? end ye s ye s no correct d a t a i s re a dilleg a l d a t a i s re a d no b a a b or note 2 s tart cle a r rovf b it no rovf = 1? re a d cnrgpt regi s ter ye s gener a tion of receive completion interr u pt cle a r dn b it re a d cnmdataxm, cnmdlcm, cnmidlm, cnmidhm regi s ter s dn = 0 and muc = 0 note 1 rhpm = 1? end ye s ye s no correct d a t a i s re a dilleg a l d a t a i s re a d no b a a b or note 2
845 can controller (can) chapter 20 user?s manual u17566ee5v1um00 3. also check the mbon flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. it is recommended to cancel any sleep mode requests, before processing rx interrupts. 4. if rovf was set once, the receive history list is inconsistent. consider to scan all configured receive buffers for receptions. figure 20-51 reception via interrupt (using cnrgpt register), alternative way note 1. also check the mbon flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. it is recommended to cancel any sleep mode requests, before processing rx interrupts. 2. if rovf was set once, the receive history list is inconsistent. consider to scan all configured receive buffers for receptions. s tart cle a r rovf b it rovf = 1? re a d cnrgpt regi s ter ye s gener a tion of receive completion interr u pt cle a r dn b it re a d cnmdataxm, cnmdlcm, cnmidlm, cnmidhm regi s ter s rhpm = 1? end ye s no no s tart cle a r rovf b it rovf = 1? re a d cnrgpt regi s ter ye s gener a tion of receive completion interr u pt cle a r dn b it re a d cnmdataxm, cnmdlcm, cnmidlm, cnmidhm regi s ter s rhpm = 1? end ye s no no
846 chapter 20 can controller (can) user?s manual u17566ee5v1um00 3. this flow will not provide most recently received data for the application. however, due to less effort on processing, it reduces interrupt load. 4. the overwrite function (cnmconfm.ows=1) must not be used with this flow - data inconsistency could occur. 5. it can be used alternatively to figure 20-50 on page 844 .
847 can controller (can) chapter 20 user?s manual u17566ee5v1um00 figure 20-52 reception via software polling note 1. also check the mbon flag at the beginning and at the end of the polling routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. 2. if rovf was set once, the receive history list is inconsistent. consider to scan all configured receive buffers for receptions. s tart cint s 1 = 1? ye s no cle a r cint s 1 b it cle a r rovf b it no rovf = 1? re a d cnrgpt regi s ter ye s cle a r dn b it re a d cnmdataxm, cnmdlcm, cnmidlm, cnmidhm regi s ter s end ye s ye s no correct d a t a i s re a d illeg a l d a t a i s re a d s tart cint s 1 = 1? ye s no cle a r cint s 1 b it cle a r rovf b it rovf = 1? re a d cnrgpt regi s ter cle a r dn b it re a d cnmdataxm, cnmdlcm, cnmidlm, cnmidhm regi s ter s dn = 0 and muc = 0 note rhpm = 1? end ye s no correct d a t a i s re a d illeg a l d a t a i s re a d no note check the muc and dn bits using one read access.
848 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-53 setting can sleep mode/stop mode caution to abort transmission before making a request for the can sleep mode, perform processing according to figure 20-45 on page 839 and figure 20-47 on page 841 . s tart (when p s mode[1:0] = 00b) p s mode0 = 1? s et p s mode0 b it can s leep mode end ye s no s et p s mode1 b it p s mode1 = 1? can s top mode re qu e s t can s leep mode a g a in? cle a r opmode ye s no ye s no acce ss to regi s ter s other th a n the cnctrl a nd cngmctrl regi s ter s init mode? ye s no cle a r cint s 5 b it s et cnctrl regi s ter ( s et opmode) s tart (when p s mode[1:0] = 00b) p s mode0 = 1? s et p s mode0 b it can s leep mode can s leep mode end ye s no s et p s mode1 b it p s mode1 = 1? can s top mode can s top mode re qu e s t can s leep mode a g a in? no ye s no cle a r cint s 5 b it
849 can controller (can) chapter 20 user?s manual u17566ee5v1um00 figure 20-54 clear can sleep/stop mode s tart end rele as ing can s leep mode b y us er cle a r p s mode0 b it can s top mode cle a r p s mode1 b it can s leep mode cle a r cint s 5 b it cle a r p s mode0 b it rele as ing can s leep mode b y can bus a ctivity domin a nt edge on can detected end cle a r p s mode0 b it
850 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-55 bus-off recovery (except normal operation mode with abt) caution when the transmission from the initialization mode to any operation modes is requested to execute bus-off recovery sequence again in the bus-off recovery sequence, reception error counter is cleared. therefore it is necessary to detect 11 consecutive recessive-level bits 128 times on the bus again. s tart forced recovery from bus off? end boff = 1? ye s no s et ccerc b it s et cnctrl regi s ter ( s et opmode) ye s no cle a r a ll trq b it s note acce ss to regi s ter s other th a n cnctrl a nd cngmctrl regi s ter s s et cnctrl regi s ter (cle a r opmode) s et cnctrl regi s ter ( s et opmode) w a it for recovery from bus off note: clear all trq bits when re-initialization of message buffer is executed by clearing rdy bit before bus-off recovery sequence is started. opmode: normal operation mode, normal operation mode with abt, receive-only mode, single-shot mode, self-test mode
851 can controller (can) chapter 20 user?s manual u17566ee5v1um00 figure 20-56 bus-off recovery (normal operation mode with abt) caution when the transmission from the initialization mode to any operation modes is requested to execute bus-off recovery sequence again in the bus-off recovery sequence, reception error counter is cleared. therefore it is necessary to detect 11 consecutive recessive-level bits 128 times on the bus again. note: clear all trq bits when re-initialization of message buffer is executed by clearing rdy bit before bus-off recovery sequence is started. opmode: normal operation mode, normal operation mode with abt, receive-only mode, single-shot mode, self-test mode s tart forced recovery from bus off? end boff = 1? ye s no s et ccerc b it s et cnctrl regi s ter ( s et opmode) ye s no cle a r a ll trq b it s note cle a r abttrg b it acce ss to regi s ter s other th a n cnctrl a nd cngmctrl regi s ter s s et cnctrl regi s ter (cle a r opmode) s et cnctrl regi s ter ( s et opmode) w a it for recovery from bus off s et cnctrl regi s ter ( s et opmode)
852 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-57 normal shutdown process s tart gom = 0? cle a r gom b it end ye s no init mode s tart end s h u tdown su cce ss f u l gom = 0, ef s d = 0
853 can controller (can) chapter 20 user?s manual u17566ee5v1um00 figure 20-58 forced shutdown process caution do not read- or write-access any registers by software between setting the efsd bit and clearing the gom bit. s tart gom = 0? cle a r gom b it end ye s no s et ef s d b it m us t b e a subs e qu ent write gom = 0? cle a r gom b it end s h u tdown su cce ss f u l gom = 0, ef s d = 0
854 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-59 error handling s tart cint s 2 = 1? cint s3 = 1? end ye s no ye s no error interr u pt cle a r cint s3 b it cle a r cint s 2 b it cint s 4 = 1? cle a r cint s 4 b it no ye s cint s3 = 1? check can mod u le s t a te (re a d cninfo regi s ter) check can protocol error s t a te (re a d cnlec regi s ter)
855 can controller (can) chapter 20 user?s manual u17566ee5v1um00 figure 20-60 setting cpu stand-by (from can sleep mode) caution before the cpu is set in the cpu standby mode, please check if the can sleep mode has been reached. however, after check of the can sleep mode, until the cpu is set in the cpu standby mode, the can sleep mode may be cancelled by wakeup from can bus. start end set psmode0 bit. set psmode0 bit = 1 clear psmode0 bit = 0 ye s no cints5 bit = 1? psmode0 bit = 1? mbon bit = 0? no ye s ye s no clear cints5 bit. clear cints5 bit = 1 can sleep mode set cpu standby mode.
856 chapter 20 can controller (can) user?s manual u17566ee5v1um00 figure 20-61 setting cpu stand-by (from can stop mode) caution the can stop mode can only be released by writing 01 b to the psmode[1:0] bit of the cnctrl register and not by a change in the can bus state. start end set psmode0 bit. set psmode0 bit = 1 clear psmode0 bit = 0 psmode0 bit = 1? mbon bit = 0? ye s no psmode1 bit = 1? no ye s can stop mode ye s no set psmode1 bit. set psmode1 bit = 1 clear psmode1 bit = 0 clear cints5 bit. clear cints5 bit = 1 set cpu standby mode. can sleep mode
857 user?s manual u17566ee5v1um00 chapter 21 a/d converter (adc) these microcontrollers contain an n-channel 10-bit a/d converter. the v850e/dx3 microcontrollers feature the following number of analog input channels: throughout this chapter, the individual channels of the a/d converter are identified by ?n?, for example adcr0n for the a/d conversion result register of channel n. 21.1 functions the a/d converter converts analog input signals into digital values. the a/d converter has the following features. ? 10-bit resolution ? successive approximation method ? the following functions are provided as operation modes. ? continuous select mode ? continuous scan mode ? the following functions are provided as trigger modes. ? software trigger mode ? timer trigger mode ? power-fail monitor function (conversion result compare function) adc pd70f3427, pd70f3426a, pd70f3425, pd70f3424 pd70f3423, pd70f3422, pd70f3421 instances 16 12
858 chapter 21 a/d converter (adc) user?s manual u17566ee5v1um00 the block diagram of the a/d converter is shown below. figure 21-1 block diagram of a/d converter ani0 ani1 ani2 anin ada0m0 ada0m1 ada0m2 ada0s sar adcr00 adcr01 adcr0n av ref av dd ada0ce bit ada0ce bit av ss ada0ce bit inttz5uv spclk0 (16 mhz) voltage comparator controller sample & hold circuit ta p selector selector internal bus intad
859 a/d converter (adc) chapter 21 user?s manual u17566ee5v1um00 21.2 configuration the a/d converter includes the following hardware. caution it is mandatory to enable the a/d converter after any reset and to perform a first conversion within a time period of maximum 1 s after reset release. with the execution of the first conversion, the a/d converter circuit is initialized. the execution of a first conversion is mandatory independently of whether the a/d converter is used later on by the user application. (1) successive approximation register (sar) the sar register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value from the series resistor string, and holds the comparison result starting from the most significant bit (msb). when the comparison result has been held down to the least significant bit (lsb) (i.e., when a/d conversion is complete), the contents of the sar register are transferred to the adcr0n register. (2) a/d conversion result register n (adcr0n), a/d conversion result register hn (adcr0hn) the adcr0n register is a 16-bit register that stores the a/d conversion result. adcr0n consist of 16 registers and the a/d conversion result is stored in the 10 higher bits of the adcr0n register corresponding to analog input. (the lower 6 bits are fixed to 0.) the adcr0n register is read-only, in 16-bit units. when using only the higher 8 bits of the a/d conversion result, the adcr0hn register is read-only, in 8-bit units. caution a write operation to the ada0m0 and ada0s registers may cause the contents of the adcr0n register to become undefined. after the conversion, read the conversion result before writing to the ada0m0 and ada0s registers. correct conversion results may not be read if a sequence other than the above is used. table 21-1 configuration of a/d converter item configuration analog inputs ani0 to anin pins registers successive approximation register (sar) a/d conversion result registers adcr00 to adcr0n a/d conversion result registers adcr0h0 to adcr0hn: only higher 8 bits can be read control registers a/d converter mode registers 0 to 2 (ada0m0 to ada0m2) a/d converter channel specification register 0 (ada0s)
860 chapter 21 a/d converter (adc) user?s manual u17566ee5v1um00 (3) power-fail compare threshold value register (ada0pft) the ada0pft register sets a threshold value that is compared with the value of a/d conversion result register nh (adcr0hn). the 8-bit data set to the ada0pft register is compared with the higher 8 bits of the a/d conversion result register (adcr0hn). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00 h . (4) sample & hold circuit the sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. this circuit also holds the sampled analog input signal voltage during a/d conversion. (5) voltage comparator the voltage comparator compares a voltage value that has been sampled and held with the voltage value of the series resistor string. (6) series resistor string this series resistor string is connected between av ref and av ss and generates a voltage for comparison with the analog input signal. (7) anin pins these are analog input pins for the 16 a/d converter channels and are used to input analog signals to be converted into digital signals. pins other than the one selected as the analog input by the ada0s register can be used as input port pins. caution 1. make sure that the voltages input to the anin pins do not exceed the rated values. in particular if a voltage of av ref or higher is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected. 2. the analog input pins anin function also as input port pins. if any of anin is selected and a/d converted, do not execute an input instruction this ports during conversion. if executed, the conversion resolution may be degraded. (8) av ref pin this is the pin used to input the reference voltage of the a/d converter. the signals input to the anin pins are converted to digital signals based on the voltage applied between the av ref and av ss pins. (9) av ss pin this is the ground pin of the a/d converter. always make the potential at this pin the same as that at the v ss pin even when the a/d converter is not used.
861 a/d converter (adc) chapter 21 user?s manual u17566ee5v1um00 21.3 adc registers the a/d converter is controlled by the following registers: ? adc mode registers 0, 1, 2 (ada0m0, ada0m1, ada0m2) ? adc channel specification register 0 (ada0s) ? power-fail compare mode register (ada0pfm) the following registers are also used: ? a/d conversion result register n (adcr0n) ? a/d conversion result register nh (adcr0hn) ? power-fail compare threshold value register (ada0pft)
862 chapter 21 a/d converter (adc) user?s manual u17566ee5v1um00 (1) ada0m0 - adc mode register 0 the ada0m0 register is an 8-bit register that specifies the operation mode and controls conversion operations. access this register can be read/written in 8-bit or 1-bit units. however, bit 0 is read- only. address ffff f200 h initial value 00 h . this register is cleared by any reset. caution 1. if ada0ef bit (bit 0) is written, this is ignored. 2. changing the ada0fr3 to ada0fr0 bits of the ada0m1 register during conversion (ada0ce0 bit = 1) is prohibited. 3. when the a/d converter is not used, stop the operation by setting the ada0ce bit to 0 to reduce the current consumption. 76543210 ada0ce 0 ada0md1 ada0md0 00 ada0tmd ada0ef r/w r/w r/w r/w r/w r/w r/w r table 21-2 ada0m0 register contents bit position bit name function 7 ad0ce a/d conversion control: 0: stops conversion 1: starts conversion 5, 4 ada0md[1:0] specification of a/d conversion operation mode 1 ada0tmd trigger mode specification: 0: software trigger mode 1: timer trigger mode 0 ada0ef a/d converter status display: 0: a/d conversion stopped 1: a/d conversion in progress ada0md1 ada0md0 a/d conversion operation mode 0 0 continuous select mode 0 1 continuous scan mode others setting prohibited
863 a/d converter (adc) chapter 21 user?s manual u17566ee5v1um00 (2) ada0m1 - adc mode register 1 the ada0m1 register is an 8-bit register that controls the conversion time specification. access this register can be read/written in 8-bit or 1-bit units. address ffff f201 h initial value 00 h . this register is cleared by any reset. caution 1. the bit 7 must be changed to ?1? after reset and must not be changed afterwards. 2. be sure to clear bits 5 and 4 to 0. note note that the given times in ta bl e 2 1 - 4 do not regard the dithering of the a/d converter supply clock. using a dithering supply clock does not impact the a/d converter?s operation. 76543210 1 0 0 0 ada0fr3 ada0fr2 ada0fr1 ada0fr0 r/w r/w r/w r/w r/w r/w r/w r/w table 21-3 ada0m1 register contents bit position bit name function 3 to 0 ad0fr[3:0] a/d conversion time settings, see ta bl e 2 1 - 4 table 21-4 conversion time settings ada0fr divi- der f spclk0 = 16 mhz f spclk0 = 4 mhz stabilization time a a) when a/d conversion is started by ada0m0.ada0ce = 0  1 the first sampling of the anin input is de- layed by the given stabilization time. this ensures compliance with the necessary stabilization time. the stabilization time applies only prior to the first sampling. 3 2 1 0 div conversion time b b) the conversion time is calculated by (31 x div) / f spclk0. sampling time c c) the sampling time is calculated by (16.5 x div) / f spclk0. conversion time b sampling time c 0 0 0 0 1 prohibited 7.75 s 4.13 s 16/f spclk0 0001 2 3.88 s 2.06 s 15.50 s 8.25 s 31/f spclk0 0010 3 5.81 s 3.09 s prohibited 47/f spclk0 0011 4 7.75 s 4.13 s prohibited 50/f spclk0 0100 5 9.69 s 5.16 s prohibited 50/f spclk0 0101 6 11.63 s 6.12 s prohibited 50/f spclk0 0110 7 13.56 s 7.22 s prohibited 50/f spclk0 0111 8 15.50 s 8.25 s prohibited 50/f spclk0 1 x x x prohibited
864 chapter 21 a/d converter (adc) user?s manual u17566ee5v1um00 (3) ada0m2 - adc mode register 2 the ada0m2 register specifies the hardware trigger mode. access this register can be read/written in 8-bit or 1-bit units. address ffff f203 h initial value 00 h . this register is cleared by any reset. caution be sure to clear bits 7 to 1. 76543210 000000 ada0tmd1 ada0tmd0 r/w r/w r/w r/w r/w r/w r/w r/w table 21-5 ada0m2 register contents bit position bit name function 1, 0 ada0tmd[1:0] specification of hardware trigger mode ada0tmd1 ada0tmd0 trigger mode 00no trigger 0 1 inttz5uv trigger others setting prohibited
865 a/d converter (adc) chapter 21 user?s manual u17566ee5v1um00 (4) ada0s - adc channel specification register 0 the ada0s register specifies the pin that inputs the analog voltage to be converted into a digital signal. access this register can be read/written in 8-bit or 1-bit units. address ffff f202 h initial value 00 h . this register is cleared by any reset. 76543210 0 0 0 ada0s4 ada0s3 ada0s2 ada0s1 ada0s0 r/w r/w r/w r/w r/w r/w r/w r/w table 21-6 ada0s register contents bit position bit name function 4 to 0 ada0s[4:0] a/d converter channel specification: ada0s4 ada0s3 ada0s2 ada0s1 ada0s0 select mode scan mode 00000 ani0 ani0 00001 ani1 ani0, ani1 00010 ani2 ani0 to ani2 00011 ani3 ani0 to ani3 00100 ani4 ani0 to ani4 00101 ani5 ani0 to ani5 00110 ani6 ani0 to ani6 00111 ani7 ani0 to ani7 01000 ani8 ani0 to ani8 01001 ani9 ani0 to ani9 01010 ani10 ani0 to ani10 01011 ani11 ani0 to ani11 01100 ani12 ani0 to ani12 01101 ani13 ani0 to ani13 01110 ani14 ani0 to ani14 01111 ani15 ani0 to ani15 other than above setting prohibited
866 chapter 21 a/d converter (adc) user?s manual u17566ee5v1um00 (5) adcr0n, adcr0hn - adc conversion result registers the adcr0n and adcr0hn registers store the a/d conversion results. access these registers are read-only, in 16-bit or 8-bit units. however, specify the adcr0n register for 16-bit access and th e adcr0hn register for 8-bit access. the 10 bits of the conversion result are read from the higher 10 bits of the adcr0n register, and 0 is read from the lower 6 bits. the higher 8 bits of the conversion result are read from the adcr0hn register. address adcr00: ffff f210 h adcr0h0: ffff f211 h adcr01: ffff f212 h adcr0h1: ffff f213 h adcr02: ffff f214 h adcr0h2: ffff f215 h adcr03: ffff f216 h adcr0h3: ffff f217 h adcr04: ffff f218 h adcr0h4: ffff f219 h adcr05: ffff f21a h adcr0h5: ffff f21b h adcr06: ffff f21c h adcr0h6: ffff f21d h adcr07: ffff f21e h adcr0h7: ffff f21f h adcr08: ffff f220 h adcr0h8: ffff f221 h adcr09: ffff f222 h adcr0h9: ffff f223 h adcr010: ffff f224 h adcr0h10: ffff f225 h adcr011: ffff f226 h adcr0h11: ffff f227 h adcr012: ffff f228 h adcr0h12: ffff f229 h adcr013: ffff f22a h adcr0h13: ffff f22b h adcr014: ffff f22c h adcr0h14: ffff f22d h adcr015: ffff f22e h adcr0h15: ffff f22f h initial value undefined 1514131211109876543210 adcr0n ad9ad8ad7ad6ad5ad4ad3ad2ad1ad0000000 rrrrrrrrrrrrrrrr 76543210 adcr0hn ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 rrrrrrrr
867 a/d converter (adc) chapter 21 user?s manual u17566ee5v1um00 the relationship between the analog voltage input to the analog input pins (ani0 to ani11) and the a/d conversion result (of a/d conversion result register n (adcr0n)) is as follows: or int( ): function that returns the integer of the value in ( ) v in : analog input voltage av ref :av ref pin voltage adcr0: value of a/d conversion result register n (adcr0n) figure 21-2 shows the relationship between the analog input voltage and the a/d conversion results. figure 21-2 relationship between analog input voltage and a/d conversion results adcr0 int v in av ref ------------------ 1024 ? 0,5 + () = adcr0 0,5 ? () av ref 1024 ------------------ ? v in adcr0 0,5 + () av ref 1024 ------------------ ? <  1,02 3 1,022 1,021 3 2 1 0 inp u t volt a ge/av ref 1 2,04 8 1 1,024 3 2,04 8 2 1,024 5 2,04 8 3 1,024 2,04 3 2,04 8 1,022 1,024 2,045 2,04 8 1,02 3 1,024 2,047 2,04 8 1 a/d conver s ion re su lt s adcr0n s ar ffc0h ff 8 0h ff40h 00c0h 00 8 0h 0040h 0000h
868 chapter 21 a/d converter (adc) user?s manual u17566ee5v1um00 (6) ada0pfm - adc power-fail compare mode register the ada0pfm register is an 8-bit register that sets the power-fail compare mode. access this register can be read/written in 8-bit or 1-bit units. address ffff f204 h initial value 00 h . this register is cleared by any reset. note in continuous select mode the conversion result of adc channel anin, selected by ada0s, is observed. in continuous scan mode the conversion result of adc channel ani0 is observed. for further details, refer to ?power-fail compare mode? on page 873 . (7) ada0pft - adc power-fail compare threshold value register the ada0pft register sets the compare value in the power-fail compare mode. access this register can be read/written in 8-bit or 1-bit units. address ffff f204 h initial value 00 h . this register is cleared by any reset. 76543210 ada0pfeada0pfc0000000 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 ada0pft7 ada0pft6 ada0pft5 ada0pft4 ada0pft3 ada0pft2 ada0pft1 ada0pft0 r/w r/w r/w r/w r/w r/w r/w r/w
869 a/d converter (adc) chapter 21 user?s manual u17566ee5v1um00 21.4 operation 21.4.1 basic operation 1. set the operation mode, trigger mode, and conversion time for executing a/ d conversion by using the ada0m0, ada0m1, ada0m2, and ada0s registers. when the ada0ce bit of the ada0m0 register is set, conversion is started in the software trigger mode and the a/d converter waits for a trigger in the external or timer trigger mode. 2. when a/d conversion is started, the voltage input to the selected analog input channel is sampled by the sample & hold circuit. 3. when the sample & hold circuit samples the input channel for a specific time, it enters the hold status, and holds the input analog voltage until a/d conversion is complete. 4. set bit 9 of the successive approximation register (sar). the tap selector selects (1/2) av ref as the voltage tap of the series resistor string. 5. the voltage difference between the voltage of the series resistor string and the analog input voltage is compared by the voltage comparator. if the analog input voltage is higher than (1/2) av ref , the msb of the sar register remains set. if it is lower than (1/2) av ref , the msb is reset. 6. next, bit 8 of the sar register is automatically set and the next comparison is started. depending on the value of bit 9, to which a result has been already set, the voltage tap of the series resistor string is selected as follows: ?bit 9 = 1: (3/4) av ref ?bit 9 = 0: (1/4) av ref this voltage tap and the analog input voltage are compared and, depending on the result, bit 8 is manipulated as follows. analog input voltage  voltage tap: bit 8 = 1 analog input voltage  voltage tap: bit 8 = 0 7. this comparison is continued to bit 0 of the sar register. 8. when comparison of the 10 bits is complete, the valid digital result is stored in the sar register, which is then transferred to and stored in the adcr0n register. at the same time, an a/d conversion end interrupt request signal (intad) is generated. figure 21-3 a/d converter basic operation sar adcr0n intad conversion time sampling time sampling a/d converter operation a/d conversion undefined conversion result conversion result
870 chapter 21 a/d converter (adc) user?s manual u17566ee5v1um00 21.4.2 trigger mode the timing of starting the conversion operation is specified by setting a trigger mode. the trigger mode includes a software trigger mode and hardware trigger modes. the hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode. the ada0tmd bit of the ada0m0 register is used to set the trigger mode. in timer trigger mode set ada0m2.ada0tmd[1:0] = 01. (1) software trigger mode when the ada0ce bit of the ada0m0 register is set to 1, the signal of the analog input pin anin specified by the ada0s register is converted. when conversion is complete, the result is stored in the adcr0n register. at the same time, the a/d conversion end interrupt request signal (intad) is generated. if the operation mode specified by the ada0md1 and ada0md0 bits of the ada0m0 register is the continuous select/scan mode, the next conversion is started, unless the ada0ce bit is cleared to 0 after completion of the first conversion. when conversion is started, the ada0ef bit is set to 1 (indicating that conversion is in progress). if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft register is written during conversion, the conversion is aborted and started again from the beginning. (2) timer trigger mode in this mode, converting the signal of the analog input pin anin specified by the ada0s register is started by the timer z underflow interrupt signal. make sure to set ada0m2.ada0tmd[1:0] = 01 b . when conversion is completed, the result of the conversion is stored in the adcr0n register. at the same time, the a/d conversion end interrupt request signal (intad) is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (indicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that conversion is stopped). if the valid trigger is input during the conversion operation, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft register is written during conversion, the conversion is stopped and the a/d converter waits for the trigger again.
871 a/d converter (adc) chapter 21 user?s manual u17566ee5v1um00 21.4.3 operation modes two operation modes are available as the modes in which to set the anin pins: continuous select mode and continuous scan mode. the operation mode is selected by the ada0md1 and ada0md0 bits of the ada0m0 register. (1) continuous select mode in this mode, the voltage of one analog input pin selected by the ada0s register is continuously converted into a digital value. the conversion result is stored in the adcr0n register corresponding to the analog input pin. in this mode, an analog input pin corresponds to an adcr0n register on a one-to-one basis. each time a/d conversion is completed, the a/ d conversion end interrupt request signal (intad) is generated. after completion of conversion, the next conversion is started, unless the ada0ce bit of the ada0m0 register is cleared to 0. figure 21-4 timing example of continuous select mode operation (ada0s = 01 h ) (2) continuous scan mode in this mode, analog input pins are sequentially selected, from the ani0 pin to the pin specified by the ada0s register, and their values are converted into digital values. the result of each conversion is stored in the adcr0n register corresponding to the analog input pin. when conversion of the analog input pin specified by the ada0s register is complete, the a/d conversion end interrupt request signal (intad) is generated, and a/d conversion is started again from the ani0 pin, unless the ada0ce bit of the ada0m0 register is cleared to 0. ani1 a/d conver s ion d a t a 1 ( ani1) d a t a 2 (ani1) d a t a 3 (ani1) d a t a 4 (ani1) d a t a 5 ( ani1) d a t a 6 (ani1) d a t a 1 d a t a 2 d a t a 3 d a t a 4 d a t a 5 d a t a 6 d a t a 1 (ani1) d a t a 2 (ani1) d a t a 3 (ani1) d a t a 4 (ani1) d a t a 5 (ani1) adcr01 intad conver s ion s t a rt s et ada0m0.ada0ce = 1 d a t a 6 (ani1)
872 chapter 21 a/d converter (adc) user?s manual u17566ee5v1um00 figure 21-5 timing example of continuous scan mode operation (ada0s register = 03 h ) a /d conversion data 1 ( ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) data 7 (ani2) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) adcr0n intad conversion start set ada0ce bit = 1 ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter adcr0n registers analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani15 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 adcr015 . . . . . . . (a) timing example
873 a/d converter (adc) chapter 21 user?s manual u17566ee5v1um00 21.4.4 power-fail compare mode the a/d conversion end interrupt request signal (intad) can be controlled as follows by the ada0pfm and ada0pft registers. ? if the power-fail compare mode is disabled (ada0pfm.ada0pfe = 0), the intad signal is generated each time conversion is completed. ? if the power-fail compare mode is enabled (ada0pfm.ada0pfe = 1) and ada0pfm.ada0pfc = 0, the value of the adcr0hn register is compared with the value of the ada0pft register when conversion is completed, and the intad signal is generated only if adcr0h0  ada0pft. ? if the power-fail compare mode is enabled (ada0pfm.ada0pfe = 1) and ada0pfm.ada0pfc = 1, the value of the adcr0hn register is compared with the value of the ada0pft register when conversion is completed, and the intad signal is generated only if adcr0h0 < ada0pft. in the power-fail compare mode, two modes are available as modes in which to set the anin pins: continuous select mode and continuous scan mode. (1) continuous select mode in this mode, the higher 8 bits of conversion result of the anin channel in ada0cr0hn, specified by ada0s, is compared with the value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfm.ada0pfc bit, intad is generated. in any case the next conversion is started. figure 21-6 timing example of continuous select mode operation whit power-fail comparison (2) continuous scan mode in this mode, the adc channels starting from ani0 to the one specified by the ada0s register are sequentially converted and the conversion results are stored in the adcr0n registers. adcr0n a/d conver s ion anin intad data 1 data 2 data 3 data 4 data 5 data 6 data 1 data 2 data 3 data 4 data 5 ada0pft match ada0pft unmatch ada0pft match ada0pft match ada0pft unmatch ada0pft unmatch
874 chapter 21 a/d converter (adc) user?s manual u17566ee5v1um00 note in continuous scan mode power-fail comparison is performed only on ani0. after each conversion of ani0, the higher 8 bits of conversion result in ada0cr0h0 is compared with the value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfm.ada0pfc bit, intad is generated. in any case conversion of the remaining adc channels continuous. thus it is possible to catch a snapshot of the other analog inputs anin in case of power-fail.
875 a/d converter (adc) chapter 21 user?s manual u17566ee5v1um00 figure 21-7 timing example of continuous scan mode operation with power-fail comparison (ada0s = 03 h ) (a) timing example (b) block diagram a/d converter adcr0n registers analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani15 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 adcr015 . . . . . . . adcr0n a/d conver s ion ani 3 intad ani0 ada0pft match ada0pft unmatch ani1 ani2 ani3 ani0 ani1 ani2 ani1 ani0 ani0 ani1 ani2 ani3 ani0 ani1 ani3
876 chapter 21 a/d converter (adc) user?s manual u17566ee5v1um00 21.5 cautions (1) when a/d converter is not used when the a/d converter is not used, the power consumption can be reduced by clearing the ada0ce bit of the ada0m0 register to 0. (2) input range of anin pins input the voltage within the specified range to the anin pins. if a voltage equal to or higher than av ref or equal to or lower than av ss (even within the range of the absolute maximum ratings) is input to any of these pins, the conversion value of that channel is undefined. (3) countermeasures against noise to maintain the 10-bit resolution, the anin pins must be effectively protected from noise. the influence of noise increases as the output impedance of the analog input source becomes higher. to lower the noise, connecting an external capacitor as shown in figure 21-8 is recommended. figure 21-8 processing of analog input pin (4) alternate i/o the analog input pins anin function alternately as port pins. when selecting one of the anin pins to execute a/d conversion, do not execute an instruction to read an input port or write to an output port during conversion as the conversion resolution may drop. if a digital pulse is applied to a pin adjacent to the pin whose input signal is being converted, the a/d conversion value may not be as expected due to the influence of coupling noise. therefore, do not apply a pulse to a pin adjacent to the pin undergoing a/d conversion. av ref v dd v ss av ss cl a mp with a diode with a low v f (0. 3 v or le ss ) if noi s e e qua l to or higher th a n av ref or e qua l to or lower th a n av ss m a y b e gener a ted. c = 100 to 1,000 pf ani0 to ani15
877 a/d converter (adc) chapter 21 user?s manual u17566ee5v1um00 (5) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the contents of the ada0s register are changed. if the analog input pin is changed during a/d conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ada0s register is rewritten. if the adif flag is read immediately after the ada0s register is rewritten, the adif flag may be set even though the a/d conversion of the newly selected analog input pin has not been completed. when a/d conversion is stopped, clear the adif flag before resuming conversion. figure 21-9 generation timing of a/d conversion end interrupt request (6) reading adcr0n register when the ada0m0 to ada0m2 or ada0s register is written, the contents of the adcr0n register may be undefined. read the conversion result after completion of conversion and before writing to the ada0m0 to ada0m2 and ada0s registers. the correct conversion result may not be read at a timing different from the above. ada0s rewriting (anin conversion start) ada0s rewriting (anim conversion start) adif is set, but anim conversion does not end a/d conversion adcr0n intad anin anin anim anim anim anin anin anim
878 chapter 21 a/d converter (adc) user?s manual u17566ee5v1um00 21.6 how to read a/d converter characteristics table this section describes the terms related to the a/d converter. (1) resolution the minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 lsb (least significant bit). the ratio of 1 lsb to the full scale is expressed as %fsr (full-scale range). %fsr is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as follows, independently of the resolution. 1%fsr = (maximum value of convertible analog input voltage ? minimum value of convertible analog input voltage)/100 = (av ref ? 0)/100 = av ref /100 when the resolution is 10 bits, 1 lsb is as follows: 1 lsb = 1/2 10 = 1/1,024 = 0.098%fsr the accuracy is determined by the overall error, independently of the resolution. (2) overall error this is the maximum value of the difference between an actually measured value and a theoretical value. it is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. the overall error in the characteristics table does not include the quantization error. figure 21-10 overall error ide a l line over a ll error 1 ...... 1 0 ...... 0 0av ref an a log inp u t digit a l o u tp u t
879 a/d converter (adc) chapter 21 user?s manual u17566ee5v1um00 (3) quantization error this is an error of 1/2 lsb that inevitably occurs when an analog value is converted into a digital value. because the a/d converter converts analog input voltages in a range of 1/2 lsb into the same digital codes, a quantization error is unavoidable. this error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or differential linearity error in the characteristics table. figure 21-11 quantization error (4) zero-scale error this is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 0?000 to 0?001 (1/2 lsb). figure 21-12 zero-scale error q ua ntiz a tion error 1 ...... 1 0 ...... 0 0av ref an a log inp u t digit a l o u tp u t 1/2 l s b 1/2 l s b av ref an a log inp u t (l s b) digit a l o u tp u t (lower 3 b it s ) ide a l line 111 ? 10 1 2 3 100 011 010 001 000 zero- s c a le error
880 chapter 21 a/d converter (adc) user?s manual u17566ee5v1um00 (5) full-scale error this is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1?110 to 0?111 (full scale - 3/2 lsb). figure 21-13 full-scale error (6) differential linearity error ideally, the width to output a specific code is 1 lsb. this error indicates the difference between the actually measured value and its theoretical value when a specific code is output. figure 21-14 differential linearity error av ref an a log inp u t (l s b) digit a l o u tp u t (lower 3 b it s ) 111 av ref ? 3 0 av ref ? 2av ref ? 1 110 101 100 000 f u ll- s c a le error ide a l width of 1 l s b differenti a l line a rity error 1 ...... 1 0 ...... 0 av ref an a log inp u t digit a l o u tp u t
881 a/d converter (adc) chapter 21 user?s manual u17566ee5v1um00 (7) integral linearity error this error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. it indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. figure 21-15 integral linearity error (8) conversion time this is the time required to obtain a digital output after an analog input voltage has been assigned. the conversion time in the characteristics table includes the sampling time. (9) sampling time this is the time for which the analog switch is on to load an analog voltage to the sample & hold circuit. figure 21-16 sampling time 1 ...... 1 0 ...... 0 0av ref an a log inp u t digit a l o u tp u t ide a l line integr a l line a rity error sa mpling time conver s ion time
882 chapter 21 a/d converter (adc) user?s manual u17566ee5v1um00
883 user?s manual u17566ee5v1um00 chapter 22 stepper moto r controller/driver (stepper-c/d) the stepper motor controller/driver module is comprised of six drivers (k = 1 to 6) for external 360 type meters or for bipolar and unipolar stepper motors. the v850e/dx3 microcontrollers have following instances of the stepper motor controller/driver: throughout this chapter, the individual instances of stepper-c/d are identified by ?n?, for example mcntcn0, or mcntcn1 for the timer mode control registers. the stepper motor controller/driver module can be separated into two sub- modules. throughout this chapter, the individual sub-modules are identified by ?m? (m = 0, 1). 22.1 overview the stepper motor controller/driver module generates pulse width modulated (pwm) output signals. each driver generates up to four output signals. features summary the generated output signals have the following features: ? pulse width of 8 bits precision ? 1-bit addition function enables an average pulse width precision of 1/2 bit, resulting in a pseudo 9-bit precision ? pwm frequency up to 32 khz ? automatic pwm phase shift for reducing fluctuation on power supply and for reducing the susceptibility to electromagnetic interference 22.1.1 driver overview a stepper motor is driven by pwm signals. the pwm signals are generated by comparing the contents of compare registers with the actual value of a free running up counter. the stepper motor controller/driver module can be separated into two sub- modules - each sub-module contains one counter and assigned compare registers and control registers. in the following, the two sub-modules are called stepper motor controller/driver 0 sub-module and stepper motor controller/ driver 1 sub-module. stepper-c/d all devices instances 1
884 chapter 22 stepper motor controller/driver (stepper-c/d) user?s manual u17566ee5v1um00 the following figures show the main components of the stepper motor controller/driver 0 sub-module ( figure 22-1 ) and of the stepper motor controller/driver 1 sub-module ( figure 22-2 ). the stepper motor controller/driver 0 sub-module is comprised of 4 drivers (k = 1 to 4), stepper motor controller/driver 1 sub-module is comprised of 2 drivers (k = 5 to 6). each stepper motor controller/driver sub-module includes a free running up counter (cntm). the counter is controlled by a timer mode control register (mcntcnm). each of the six drivers consists of two compare registers, mcmpnk0 and mcmpnk1, respectively. their contents define the pulse widths for the sine and the cosine side of the meters. the mcmpnk0/mcmpnk1 registers comprise a master-slave register combination. this allows to re-write the master register while the slave register is currently used for comparison with the counter cntm. the compare control register mcmpcnk defines whether or not enhanced pulse width precision by one-bit addition is enabled, and it routes the output signals to the corresponding output pins (smk1 to smk4). figure 22-1 stepper motor controller/driver 0 block diagram s m11 ( s in1+) 8 - b it comp a re regi s ter mcpmn10 ovf o u tp u t control s q r s q r s q r s q r s q r s q r s q r s q r s elector pre s c a ler f mc0 1- b it a dd. circ u it 8 - b it comp a re regi s ter mcpmn11 8 - b it comp a re regi s ter mcpmn20 8 - b it comp a re regi s ter mcpmn21 8 - b it comp a re regi s ter mcpmn 3 0 8 - b it comp a re regi s ter mcpmn 3 1 8 - b it comp a re regi s ter mcpmn40 8 - b it comp a re regi s ter mcpmn41 1- b it a dd. circ u it 1- b it a dd. circ u it 1- b it a dd. circ u it 1- b it a dd. circ u it 1- b it a dd. circ u it 1- b it a dd. circ u it 1- b it a dd. circ u it 8 - b it free-r u nning co u nter cnt0 o u tp u t control o u tp u t control o u tp u t control o u tp u t control o u tp u t control o u tp u t control o u tp u t control s m12 ( s in1-) s m1 3 (co s 1+) s m14 (co s 1-) s m21 ( s in2+) s m22 ( s in2-) s m2 3 (co s 2+) s m24 (co s 2-) s m 3 1 ( s in 3 +) s m 3 2 ( s in 3 -) s m 33 (co s3 +) s m 3 4 (co s3 -) s m41 ( s in4+) s m42 ( s in4-) s m4 3 (co s 4+) s m44 (co s 4-) s pclk1 ( 8 mhz) s pclk1 s pclk1/2 s pclk1/4 s pclk1/ 8 s pclk1/16 s pclk1/ 3 2 s pclk1/64 s pclk1/12 8
885 stepper motor controller/driver (stepper-c/d) chapter 22 user?s manual u17566ee5v1um00 figure 22-2 stepper motor controller/driver 1 block diagram the external signals are listed in the following table. sm51 (sin5+) 8-bit compare register mcpmn50 ovf output control s q r s q r s q r s q r spclk1 spclk1/2 spclk1/4 spclk1/8 spclk1/16 spclk1/32 spclk1/64 spclk1/128 selector prescaler f mc1 1-bit add. circuit 8-bit compare register mcpmn51 8-bit compare register mcpmn60 8-bit compare register mcpmn61 1-bit add. circuit 1-bit add. circuit 1-bit add. circuit 8-bit free-running counter cnt1 output control output control output control sm52 (sin5-) sm53 (cos5+) sm54 (cos5-) sm61 (sin6+) sm62 (sin6-) sm63 (cos6+) sm64 (cos6-) spclk1 (8mhz) table 22-1 stepper motor controller/driver external connections signal name i/o active level reset level pins function sm[1:6]1 o ? l sm11 to sm61 driver signal, sine side (+) sm[1:6]2 o ? l sm12 to sm62 driver signal, sine side (?) sm[1:6]3 o ? l sm13 to sm63 driver signal, cosine side (+) sm[1:6]4 o ? l sm14 to sm64 driver signal, cosine side (?)
886 chapter 22 stepper motor controller/driver (stepper-c/d) user?s manual u17566ee5v1um00 22.2 stepper motor controller/driver registers the stepper motor controller/driver is controlled and operated by means of the following registers: the base address of the stepper motor controller/driver is = ffff f5c0 h . table 22-2 stepper motor controller/driver registers overview register name shortcut address timer mode control registers mcntcn0 mcntcn1 + 14 h compare registers mcmpnk0 (k = 1 to 6) + 2 h , 4 h , 6 h , 8 h , 16 h , 18 h mcmpnk1 (k = 1 to 6) + 3 h , 5 h , 7 h , 9 h , 17 h , 19 h mcmpnkhw (k = 1 to 6) + 2 h , 4 h , 6 h , 8 h , 16 h , 18 h compare control registers mcmpcnk (k = 1 to 6) + a h , c h , e h , 10 h , 1a h , 1c h
887 stepper motor controller/driver (stepper-c/d) chapter 22 user?s manual u17566ee5v1um00 (1) mcntcn0, mcntcn1 - timer mode control registers the 8-bit mcntcnm registers control the operation of the free running up counters cntm. access these registers can be read/written in 8-bit or 1-bit units. address mcntcn0: mcntcn1: + 14 h initial value 00 h . this register is cleared by any reset. 76543210 cae a a) bit cae refers only to register mcntcn0. in register mcntcn1, this bit is set to 0. 0 full pce 0 smcl2 smcl1 smcl0 r/w b b) in register mcntcn1, this bit is read only (r) r r/w r/w r r/w r/w r/w table 22-3 mcntcnm register contents bit position bit name function 7cae a a) bit cae refers only to register mcntcn0. in register mcntcn1, this bit is set to 0. stepper motor controller/driver control 0: stepper motor controller/driver operation is disabled. 1: stepper motor controller/driver operation is enabled. this bit switches both stepper motor controller/driver 0 and stepper motor controller/driver 1. 5 full sets the count range of the timer counter 0: count range from 01 h to ff h 1: count range from 00 h to ff h the initial start value is 00 h in both cases. for the impact of this bit on duty factor and pwm cycle time, see also ?duty factor? on page 892 . 4 pce timer operation control 0: timer counter is stopped. 1: timer counter is enabled. 2 to 0 smcl[2:0] sets the timer count clock for the timer counter smcl2 smcl1 smcl0 selected timer count clock 00 0 spclk1 00 1 spclk1 / 2 01 0 spclk1 / 4 01 1 spclk1 / 8 10 0 spclk1 / 16 10 1 spclk1 / 32 11 0 spclk1 / 64 11 1 spclk1 / 128
888 chapter 22 stepper motor controller/driver (stepper-c/d) user?s manual u17566ee5v1um00 caution in register mcntcn0, bits 3 and 6 must be 0. in register mcntcn1, bits 3, 6 and 7 must be 0. power save mode preparation before entering any power save mode the stepper-c/d must be shut down in advance in order to minimize power consumption. apply following sequence to shut down the stepper-c/d: 1. stop the counter cnt1 by setting mcntcn1.pce = 0. 2. stop the counter cnt0 by setting mcntcn0.pce = 0. 3. disable the stepper-c/d operation by setting mcntcn0.cae = 0. note that the mcntcn0.pce and mcntcn0.cae bits must not be cleared to 0 by a single write instruction. perform two write instructions as shown above. (2) mcmpnk0 - compare registers for sine side (k = 1 to 6) the 8-bit mcmpnk0 registers hold the values that define the pwm pulse width for the sine side of the connected meters. the contents of the registers are continuously compared to the timer counter value: ? registers mcmpn10 to mcmpn40 are compared to cnt0. ? registers mcmpn50 to mcmpn60 are compared to cnt1. when the register contents match the timer counter contents, a match signal is generated. thus a pwm pulse with a pulse width corresponding to the mcmpnk0 register contents is output to the sine side of the connected meter. access these registers can be read/written in 8-bit units. address + 2 h , 4 h , 6 h , 8 h , 16 h , 18 h initial value 00 h . this register is cleared by any reset. note 1. new data must only be written to registers mcmpnk0 if the corresponding bit mcmpcnk.ten = 0. 2. don't write to the compare register mcmpnk0, until the corresponding bit mcmpcnk.ten has been reset to 0 automatically. 3. to enable master-to-slave register copy upon next cntm overflow set mcmpcnk.ten = 1. 76543210 sine data r/w
889 stepper motor controller/driver (stepper-c/d) chapter 22 user?s manual u17566ee5v1um00 (3) mcmpnk1 - compare registers for cosine side (k = 1 to 6) the 8-bit mcmpnk1 registers hold the values that define the pwm pulse width for the cosine side of the connected meters. the contents of the registers are continuously compared to the timer counter value: ? registers mcmpn11 to mcmpn41 are compared to cnt0. ? registers mcmpn51 to mcmpn61 are compared to cnt1. when the register contents match the timer counter contents, a match signal is generated. thus a pwm pulse with a pulse width corresponding to the mcmpnk1 register contents is output to the sine side of the connected meter. access these registers can be read/written in 8-bit units. address + 3 h , 5 h , 7 h , 9 h , 17 h , 19 h initial value 00 h . this register is cleared by any reset. note 1. new data must only be written to registers mcmpnk1 if the corresponding bit mcmpcnk.ten = 0. 2. don't write to the compare register mcmpnk1, until the corresponding bit mcmpcnk.ten has been reset to 0 automatically. 3. to enable master-to-slave register copy upon next cntm overflow set mcmpcnk.ten = 1. (4) mcmpnkhw - combined compare registers (k = 1 to 6) the 16-bit mcpmnkhw registers combine the sine and cosine registers mcmpnk0 and mcmpnk1. via these registers it is possible to read or write the contents of mcmpnk0 and mcmpnk1 in a single instruction. access these registers can be read/written in 16-bit units. address + 2 h , 4 h , 6 h , 8 h , 16 h , 18 h initial value 0000 h . this register is cleared by any reset. note 1. new data must only be written to registers mcmpnk1 if the corresponding bit mcmpcnk.ten = 0. 2. don't write to the compare register mcmpnk1, until the corresponding bit mcmpcnk.ten has been reset to 0 automatically. 3. to enable master-to-slave register copy upon next cntm overflow set mcmpcnk.ten = 1. 76543210 cosine data r/w 1514131211109876543210 cosine data sine data r/w
890 chapter 22 stepper motor controller/driver (stepper-c/d) user?s manual u17566ee5v1um00 (5) mcmpcnk - compare control registers (k = 1 to 6) the 8-bit mcmpcnk registers control the operation of the corresponding compare registers and the output direction of the pwm pin. access these registers can be read/written in 8-bit units. address + a h , c h , e h , 10 h , 1a h , 1c h initial value 00 h . this register is cleared by any reset. 76543210 aout 0 a a) do not change this bit. 0 b b) this bit may be written, but writing is ignored. ten adb1 adb0 dir1 dir0 r/w r/w r r/w r/w r/w r/w r/w table 22-4 mcmpcnk register contents bit position bit name function 7 aout selects the output pins for sine and cosine signals 0: the pwm signals for sine and cosine side are output to those pins that are selected by bits dir0 and dir1. at all other pins, the output signal is 0 (smv ss level). 1: the pwm signal for the sine side is output to pins smk1 and smk2. the pwm signal for the cosine side is output to pins smk3 and smk4. 4 ten transfer enable control bit 0: mcmpnk0/mcmpnk1 master-to-slave register copy is disabled. new data can be written to compare registers mcmpnk0 or mcmpnk1. 1: mcmpnk0/mcmpnk1 master-to-slave register copy is enabled. the copy process will take place when cnt0 or cnt1, respectively, overflows. don't write to compare registers mcmpnk0 or mcmpnk1 while mcmpcnk.ten = 1. note: this bit functions as a control bit and status flag. it is automatically reset to zero upon the next timer counter overflow. 3 adb1 sets 1-bit addition function for cosine side 0: no 1-bit addition to pwm signal 1: 1-bit addition to pwm signal 2 adb0 sets 1-bit addition function for sine side 0: no 1-bit addition to pwm signal 1: 1-bit addition to pwm signal 1 to 0 dir[1:0] selects the output pins for the pwm signals. bits dir1 and dir0 address the quadrant to be activated by sine and cosine. the pwm signal is routed to the specific pin with respect to the sin/cos of each quadrant. dir1 dir0 selected output pins 00 quadrant 1: smk1 (sin +), smk3 (cos +) 01 quadrant 2: smk1 (sin +), smk4 (cos ?) 10 quadrant 3: smk2 (sin ?), smk4 (cos ?) 11 quadrant 4: smk2 (sin ?), smk3 (cos +) at the other output pins, the output level is smv ss . note: these bits are only considered if bit aout is set to 0.
891 stepper motor controller/driver (stepper-c/d) chapter 22 user?s manual u17566ee5v1um00 22.3 operation in the following, the operation of the stepper motor controller/driver module as a driver for external meters is described. 22.3.1 stepper motor controller/driver operation this section describes the generation of pwm signals of the driver k for driving external meters. further, the achievable duty factor is explained and how advanced precision can be gained by 1-bit addition. (1) driving meters external meters can be driven both in h-bridge configuration and in half bridge configuration: ? driving meters in h-bridge configuration deflection of the needle of a meter in h-bridge configuration is determined by the sine and cosine value of its desired angle. since the pwm signals do not inherit a sign, separate signals for positive and negative sine and cosine values are generated. the four signals at pins smk1 to smk4 of the driver k are: ? sine side, positive (sin +) ? sine side, negative (sin ?) ? cosine side, positive (cos +) ? cosine side, negative (cos ?) two output control circuits select which signal (sign) for sine side and cosine side is output (bits mcmpcnk.dir[1:0]). at the remaining two output pins, the signal is set to low level. to drive meter k in full bridge mode, set bit mcmpcnk.aout to 0. ? driving meters in half bridge configuration in this mode, the same signal is sent to both sine pins (smk1 and smk2) and both cosine pins (smk3 and smk4), respectively. the setting of output control bits mcmpcnk.dir[1:0] is neglected. to drive meter k in half bridge mode, set bit mcmpcnk.aout to 1. (2) generation of pwm signals bit data corresponding to the length of the pwm pulses has to be written to the compare registers mcmpnk0 (sine side) and mcmpnk1 (cosine side). a timer counter is counting up. the rising edge of the pwm pulse is initiated at the overflow of the counter. the falling edge of the pwm pulse is initiated when the counter value equals the contents of the compare register. the absolute pulse length in seconds is defined by the timer count clock (f mc0 and f mc1 , respectively). various cycle times can be set via the timer mode control registers mcntcn0 and mcntcn1.
892 chapter 22 stepper motor controller/driver (stepper-c/d) user?s manual u17566ee5v1um00 instruction when writing data to compare registers, proceed as follows: 1. confirm that mcmpcnk.ten = 0. 2. write 8-bit pwm data to mcmpnk0 and mcmpnk1. 3. set mcmpcnk.adb0 and mcmpcnk.adb1 as desired. 4. set mcmpcnk.ten = 1 to start the counting operation. the data in mcmpnk0/mcmpnk1 will automatically be copied to the compare slave register when the counter overflows. the new pulse width is valid immediately. bit mcmpcnk.ten is automatically cleared to 0 by hardware. (3) duty factor the minimum pulse width that can be generated is zero (output signal is low) and the maximum pulse width is 255 clock cycles (maximum value of 8-bit compare registers). the count range of the timer counter defines the duty factor. it can be set by bit mcntcnm.full: ? count range 01 h to ff h (mcntcnm.full = 0) formula for the duty cycle: pwm duty = mcmpki / 255 with k = 1 to 6 and i = 0, 1 one count cycle is comprised of 255 clock cycles. a pwm signal with maximum pulse length is a steady high level signal. the duty factor is 100%. ? count range 00 h to ff h (mcntcnm.full = 1) formula for the duty cycle: pwm duty = mcmpki / 256 with k = 1 to 6 and i = 0, 1 one count cycle is comprised of 256 clock cycles. a pwm signal with maximum pulse length is comprised of 255 clock cycles at high level and one clock cycle at low level. the duty factor is 255/256 *100% = 99.6%. (4) advanced precision by 1-bit addition the precision of the angle of a needle is implicitly defined by the number of bits of the compare registers mcmpnk0 and mcmpnk1 (8 bit). if the 1-bit addition circuit is enabled, every second pulse of the pwm signal is extended by one bit (one clock cycle). in average, a pulse width precision of 1/2 bit (1/2 clock) can be achieved. the following figures show the timing of pwm output signals with 1-bit addition disabled and enabled. note 1. the pwm pulse is not generated until the first overflow occurs after the counting operation has been started. 2. the pwm signal is two cycle counts delayed compared to the overflow signal and the match signal. this is not depicted in the figures.
893 stepper motor controller/driver (stepper-c/d) chapter 22 user?s manual u17566ee5v1um00 figure 22-3 output timing without 1-bit addition figure 22-4 output timing with 1-bit addition sequence 1. start of counting (mcntcnm.pce is set to 1) 2. generation of overflow signal (start of pwm pulse) 3. generation of match signal (timer counter cntm matches compare register, end of pwm pulse) ovf (overflow) cntm match signal pwm output 00h ffh mcmpnkm value n (2) (3) (2) (3) (2) (3) (2) (1) ffh mcmpnkm value n n+1 00h cntm ovf (overflow) match signal pwm output adb0 / adb1 (1) (2) (3) (2) (3) (2) (3) (2) one bit is added
894 chapter 22 stepper motor controller/driver (stepper-c/d) user?s manual u17566ee5v1um00 22.4 timing this section starts with the timing of the timer counter and general output timing behaviour. then, examples of output signal generation with and without 1-bit addition are presented. 22.4.1 timer counter the free running up counter is clocked by the timer count clock selected in register mcntcnm. the counting operation is enabled or disabled by the mcntcnm.pce bit. figure 22-5 restart timing after count stop (count start?count stop?count start) sequence ? count start: ? enable counting operation (mcntcnm.pce = 1) ? timer counter starts with value 00 h . depending on bit mcntcnm.full, all following counter cycles start with 00 h or 01 h , respectively. ? count stop: ? disable counting operation (mcntcnm.pce = 0) ? counting is stopped and timer counter is set to 00 h . clk cntm pce 0h 1h 2h 1h 2h 3h 4h 7h 8h 00h count start count stop count start
895 stepper motor controller/driver (stepper-c/d) chapter 22 user?s manual u17566ee5v1um00 22.4.2 automatic pwm phase shift simultaneous switching of sine and cosine output could lead to a fluctuation of the power supply and increase the susceptibility to electromagnetic interference. to prevent this for drivers 1 to 4, the output signals are automatically shifted by one timer count clock cycle defined in mcntcn0. the same accounts for the output signals of drivers 5 and 6. they are controlled by the timer count clock defined in mcntcn1. figure 22-6 output timing of signals sm11 to sm44 figure 22-7 output timing of signals sm51 to sm64 cnt0 driver 1 s in ( s m11, s m12) driver 1 co s ( s m1 3 , s m14) driver 4 co s ( s m4 3 , s m44) driver 2 s in ( s m21, s m22) driver 2 co s ( s m2 3 , s m24) driver 3 s in ( s m 3 1, s m 3 2) driver 3 co s ( s m 33 , s m 3 4) driver 4 s in ( s m41, s m42) cnt1 driver 5 s in ( s m51, s m52) driver 5 co s ( s m5 3 , s m54) driver 6 s in ( s m61, s m62) driver 6 co s ( s m6 3 , s m64)
896 chapter 22 stepper motor controller/driver (stepper-c/d) user?s manual u17566ee5v1um00
897 user?s manual u17566ee5v1um00 chapter 23 lcd controller/driver (lcd-c/d) only the pd70f3421, pd70f3422, and pd70f3423 microcontrollers are provided with the lcd controller/driver. this lcd controller/driver is suitable for lc displays with up to 160 segments. the supported addressing method of the lcd is multiplex addressing. 23.1 overview the lcd controller/driver generates the signals that are necessary for driving an lcd panel. features summary the lcd controller/driver provides: ? maximum of 40 segment signal outputs (seg0 to seg39) ? 4 common signal outputs (com0 to com3) ? display mode: 1/4 duty (1/3 bias) ? wide range of selectable frame frequencies ? edge enhancement
898 chapter 23 lcd controller/driver (lcd-c/d) user?s manual u17566ee5v1um00 23.1.1 description the following figure shows the main components of the lcd controller/driver: figure 23-1 lcd controller/driver block diagram the pattern that is to be displayed on the lcd panel has to be mapped to bit data. the bit data is stored in the display control registers segregk (k = 0 to 39). the lcd controller/driver generates the corresponding output signals for driving the lcd panel. the update rate of the lc display is determined by the frame frequency. it can be adjusted via the clock control register lcdc. the external signals are listed in the following table. segment driver timing controller common driver seg0 ... seg20 seg39 ... seg10 ... seg30 ... com0 com1 com2 com3 lcd drive voltage generator segment data selector display data memory internal bus selector selector prescaler f lcd0 2 9 f lcd0 2 8 f lcd0 2 7 f lcd0 2 6 f spclk7 (125 khz) spclk9 (31.25 khz) lcdclk lcd0 f lcd1 lcd frame frequency selection lcd clock selection table 23-1 lcd controller/driver external connections signal name i/o pins function seg[0:39] o seg0 to seg39 segment signals com[0:3] o com0 to com3 common signals
899 lcd controller/driver (lcd-c/d) chapter 23 user?s manual u17566ee5v1um00 23.1.2 lcd panel addressing each individual segment of an lcd panel is addressed by a signal pair: a segment signal and a common signal. the segment becomes visible when the potential difference of the corresponding common signal and the segment signal reaches or exceeds the lcd drive voltage v lcd . example figure 23-2 shows how the eight lcd segments of a digit are allocated to ? two segment signals (seg 2n and seg 2n+1, n = 0 to 19) ? four common signals figure 23-2 allocation of segment signals and common signals to lcd segments (4-time-division) every combination of a segment and a common signal addresses a single element. the middle horizontal bar, for example, becomes visible if the potential difference of signals seg 2n+1 and com1 exceeds v lcd . to display a desired pattern on the lcd panel: 1. check what combination of segment and common signals form the desired display pattern. 2. write bit data with the pattern to be displayed to registers segregk. the lcd controller/driver generates the corresponding segment and common signals. see also the ?display example? on page 906 . connections at the lcd panel, the signals are connected as follows: caution the lcd panel is driven by ac voltage. the performance of the lcd deteriorates if dc voltage is applied in the common and segment signals. that means contrast and brightness of the display may decrease. the display may even be damaged. com0 seg 2n com1 seg 2n + 1 com2 com3 table 23-2 signals and connections of lcd controller/driver signals connection at lcd panel segment signals front surface electrodes common signals rear surface electrodes
900 chapter 23 lcd controller/driver (lcd-c/d) user?s manual u17566ee5v1um00 23.2 lcd-c/d registers the lcd controller/driver is controlled by means of the following registers: table 23-3 lcd controller/driver registers overview register name shortcut address lcd clock control register lcdc0 ffff fb00 h lcd mode control register lcdm0 ffff fb01 h lcd display control registers segreg0k, k= 0 to 39 ffff fb20 h to ffff fb47 h
901 lcd controller/driver (lcd-c/d) chapter 23 user?s manual u17566ee5v1um00 (1) lcdc0 - lcd clock control register the 8-bit lcdc0 register determines the duty cycle frequency f lcd1 . access this register can be read/written in 8-bit or 1-bit units. address ffff fb00 h initial value 00 h . this register is cleared by any reset. caution 1. bit 4 must always be 0. 2. changing the root clock source for lcdlck will also change the watch timer clock wtclk. for details refer to the ?tcc - watch timer clock control register? on page 163 . note the frequency of lcdclk is determined in the clock generator. the root clock for lcdclk can be selected from the main, sub, or internal oscillator. it can be identical with the clock source or it can be a fraction thereof. 76543210 0 0 0 0 lcdc03 lcdc02 lcdc01 lcdc00 r r r r/w r/w r/w r/w r/w table 23-4 lcdc0 register contents bit position bit name function 3 to 2 lcdc0[3:2] selects the lcd clock lcdc03 lcdc02 selected lcd clock (f lcd0 ) 0 0 lcdclk 0 1 spclk7 1 0 spclk9 11reserved 1 to 0 lcdc0[1:0] selects the duty cycle frequency lcdc01 lcdc00 selected duty cycle frequency (f lcd1 ) 0 0 lcd clock (f lcd0 ) divided by 2 6 0 1 lcd clock (f lcd0 ) divided by 2 7 1 0 lcd clock (f lcd0 ) divided by 2 8 1 1 lcd clock (f lcd0 ) divided by 2 9
902 chapter 23 lcd controller/driver (lcd-c/d) user?s manual u17566ee5v1um00 possible frame frequencies table 23-5 lists the possible frame frequencies. the values in ta bl e 2 3 - 5 are only examples. check ?clock generator? on page 139 for details. selection of the following lcd clocks is provided: ? lcdc0.lcdc0[3:2] = 00 b lcd clock (f lcd0 ) = lcdclk = f 0 / d, with ?f 0 = root clock for lcdclk can be selected from main oscillator ( (f moclk = 4 mhz), sub oscillator (f soclk = 32.768 khz), or internal oscillator (f roclk ~ 240 khz). ?d = divider lcdclk is gained by dividing the root clock by d. divider d can be selected from 2 0 to 2 7 . for details refer to the ?tcc - watch timer clock control register? on page 163 . ? lcdc0.lcdc0[3:2] = 01 b lcd clock (f lcd0 ) = spclk7 = spclk0 / 2 7 = 125 khz ? lcdc0.lcdc0[3:2] = 10 b lcd clock (f lcd0 ) = spclk9 = spclk0 / 2 9 = 31.25 khz table 23-5 example settings for frame frequency and duty cycle lcdc03 lcdc02 lcdc01 lcdc00 lcd clock (f lcd0 ) a a) the frequency of the lcd clock (f lcd0 ) is determined bv the setting of the clock generator. for details refer to the ?clock generator? on page 139 . duty cycle frequency (f lcd1) frame frequency 0101spclk7 = 125 khz 977 hz 244 hz 0110 488 hz 122 hz 0111 244 hz 61 hz 1000spclk9 = 31.25 khz 488 hz 122 hz 1001 244 hz 61 hz 0000l cdclk = 32.768 khz (with f 0 = f soclk and d = 2 0 ) 512 hz 128 hz 0001 256 hz 64 hz 0001l cdclk ~ 120 khz (with f 0 = f roclk and d = 2 1 ) ~938 hz ~234 hz 0010 ~469 hz~117 hz
903 lcd controller/driver (lcd-c/d) chapter 23 user?s manual u17566ee5v1um00 (2) lcdm0 - lcd mode control register the 8-bit lcdm0 register enables/disables the lcd operation, activates edge enhancement and selects the power supply. access this register can be read/written in 8-bit or 1-bit units. address ffff fb01 h initial value 00 h . this register is cleared by any reset. caution bits 0, 1, 2, 3, 5, 6 must always be 0. (3) segreg0k - lcd display control register (k = 0 to 39) the 8-bit registers contain the data that is displayed on the lcd. each register contains the data for one of the 40 segments. access these registers can be read/written in 8-bit or 1-bit units. address ffff fb20 h to ffff fb47 h initial value 00 h . this register is cleared by any reset. the bits 4 to 7 are ignored. they should be set to zero. 76543210 lcdon0 0 0 lips0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w table 23-6 lcdm0 register contents bit position bit name function 7 lcdon0 enables/disables lcd display 0: display disabled no segment of the display is visible. the contents of the segreg0k registers are disregarded. the output is at non-selection level. 1: display enabled 4 lips0 selects the power supply 0: lcd controller/driver is not powered 1: lcd controller/driver is powered 76543210 0000 data r/w table 23-7 segreg0k register contents (k = 0 to 39) bit position bit name function 3 to 0 segreg0k[3:0] status of the lcd segment that is controlled by segment signal k and the common signal, that corresponds to the bit position. 0: display off 1: display on, if corresponding common signal is active
904 chapter 23 lcd controller/driver (lcd-c/d) user?s manual u17566ee5v1um00 23.3 operation the following describes the timing of common and segment signals, the activation of an lcd segment and how edge enhancement can be applied. 23.3.1 common signals and segment signals this section describes the timing of common signals and segment signals and at which conditions an individual lcd segment becomes visible. (1) common signals common signals com0 to com3 are generated internally. together with the segment signals, they define which lcd segment is activated in the current cycle. figure 23-3 shows the common signal wave form for com0, 1/4 duty (1/3 bias). 1/4 duty means each signal comn is in selection level for one quarter of a frame. figure 23-3 common signal wave form (1/4 duty, 1/3 bias) ?t f = frame cycle time. t f = 4 x t t corresponds to the duty cycle frequency f lcd1 and is thus determined by register lcdc. ? t = duty cycle time. each frame cycle t f is comprised of 4 duty cycles (1/4 duty), one duty cycle for each signal comn. each lcd segment is allocated to one of the common signals. the lcd segment can only be activated in a duty cycle, in which the common signal is at selection level. figure 23-4 shows the selection and non-selection level of common signals. figure 23-4 selection level and non-selection level of common signals t = duty cycle time. t f = 4 x t com0 (divided by 4) v lc0 v ss1 v lcd v lc1 v lc2 s elected not s elected common s ign a l v lc0 v ss 1 v lcd v lc2 v lc1 tt
905 lcd controller/driver (lcd-c/d) chapter 23 user?s manual u17566ee5v1um00 (2) segment signals segment signals correspond to the contents of the 40 lcd display control registers segreg0k. bits 0 to 3 of these registers are read in synchronization with the common signals com0 to com3, this means bit 0 is read in synchronization with common signal com0 and so on. ? if the value of the bit is 1 while the common signal is at selection level, the corresponding segment signal is set to selection level. ? if the value of the bit is 0 while the common signal is at selection level, the corresponding segment signal is set to non-selection level. figure 23-5 shows the selection and non-selection level of segment signals. figure 23-5 selection level and non-selection level of segment signals t = duty cycle time. the table below shows the relation of the bits in registers segreg0k (k = 0 to 39) with common signals com0 to com3 and segment output signals seg00 to seg39. each of the bits 0 to 4 represents the status of one lcd segment. setting the bit to 1 will make the lcd segment visible. for example, setting bit segreg02[3] to 1 will make the lcd segment visible, that is controlled by the signal pair seg2 and com3. s egment s ign a l v lc0 v ss 1 v lcd tt v lc2 v lc1 76543210 segreg00 0  seg0 segreg00 1  seg1 segreg00 2  seg2 ?? ? ?? ? ?? ? segreg03 8  seg38 segreg03 9  seg39  com3 com2 com1 com0
906 chapter 23 lcd controller/driver (lcd-c/d) user?s manual u17566ee5v1um00 23.3.2 activation of lcd segments an lcd segment becomes visible when the potential difference of the corresponding common signal and segment signal reaches or exceeds the lcd drive voltage v lcd . this is achieved if common and segment signal are at their selection levels. within one frame cycle t f , each lcd segment can be activated once. activation lasts for one duty cycle t. lcd segments corresponding to common signals com0 to com3 are not activated simultaneously, but consecutively. 23.4 display example as a display example, register contents and output signals for a 20-digit lcd display are presented in this section. (1) lcd panel the display pattern of a single digit is given below. each digit is addressed by two segment signals and four common signals. figure 23-6 4-time-division lcd pattern and electrode connections figure 23-7 on page 908 shows the whole lcd panel and its connection to the segment signals and common signals. the display example is ?123456.78901234567890,? and the register contents of segreg0k (k = 0 to 39) correspond to this. an explanation is given here taking the example of the 6th digit with point: ?6.?. the corresponding segment signals are output to pins seg28 and seg29 with the selection levels at the com0 to com3 common signal timings as shown in the table below: com0 seg 2n com1 seg 2n + 1 com2 com3 table 23-8 selection and non-selection levels of example common signal segment signal seg28 segment signal seg29 com0 selected selected com1 not selected selected com2 selected selected com3 selected selected
907 lcd controller/driver (lcd-c/d) chapter 23 user?s manual u17566ee5v1um00 from this, it can be seen that 1101 b must be prepared in the display control register segreg028 and 1111 b must be prepared in segreg029. examples of the lcd drive waveforms between seg28 and the com0 and com1 signals are shown in figure 23-8 on page 909 (for the sake of simplicity, waveforms for com2 and com3 have been omitted). when seg28 is at the selection level at the com0 selection timing, it can be seen that the +v lcd /?v lcd ac square wave, which is the lcd illumination (on) level, is generated.
908 chapter 23 lcd controller/driver (lcd-c/d) user?s manual u17566ee5v1um00 figure 23-7 4-time-division lcd panel connection example timing s tro b e s com 3 com2 com1 com0 bit0 bit1 bit2 bit 3 s eg0 s eg1 s eg2 1 1 0 1 1 1 1 1 0 1 0 0 s eg 3 s eg4 s eg5 s eg6 1 1 0 1 1 1 1 1 0 1 0 0 s eg7 s eg 8 s eg9 s eg10 1 1 0 1 1 1 1 1 0 1 0 1 s eg11 s eg12 s eg1 3 s eg14 0 1 0 1 0 0 1 1 0 0 0 1 s eg15 s eg16 s eg17 s eg1 8 1 0 0 0 1 1 1 0 0 0 0 lcd p a nel 1 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 0 timing s tro b e s s eg20 s eg19 s eg21 1 1 0 1 1 0 1 0 0 s eg22 s eg2 3 s eg24 s eg25 1 1 0 1 1 1 1 1 0 1 0 0 s eg26 s eg27 s eg2 8 s eg29 1 1 0 1 1 1 1 1 1 1 0 1 s eg 3 0 s eg 3 1 s eg 3 2 s eg 33 0 1 0 1 0 0 1 1 0 0 0 1 s eg 3 4 s eg 3 5 1 0 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 1 1 0 s eg 3 6 s eg 3 7 s eg 38 s eg 3 9 s egreg000 s egreg0 3 9
909 lcd controller/driver (lcd-c/d) chapter 23 user?s manual u17566ee5v1um00 figure 23-8 4-time-division lcd drive waveforms ? examples t f v lc0 v lc2 com0 +v lcd 0 com0-seg28 ?v lcd v lc1 +1/3v lcd ?1/3v lcd v ss1 v lc0 v lc2 com1 v lc1 v ss1 v lc0 v lc2 com2 v lc1 v ss1 v lc0 v lc2 com3 v lc1 v ss1 +v lcd 0 com1-seg28 ?v lcd +1/3v lcd ?1/3v lcd v lc0 v lc2 seg28 v lc1 v ss1
910 chapter 23 lcd controller/driver (lcd-c/d) user?s manual u17566ee5v1um00
911 user?s manual u17566ee5v1um00 chapter 24 lcd bus interface (lcd-i/f) the lcd bus interface connects the internal peripheral bus to an external lcd controller. it provides an asynchronous 8-bit parallel data bus and two control lines. the lcd bus interface supports bidirectional communication. you can send data to and query data from the lcd controller. only the pd70f3424, pd70f3425, pd70f3426a and pd70f3427 microcontrollers are provided with the lcd bus interface. 24.1 overview the lcd bus interface transmits or receives data bytes. two control lines specify the read/write timing and the transfer direction. the lcd bus interface suits lcd controllers that feature automatic generation of display memory addresses. the interface does not generate or interpret specific signals that may be required by the lcd controller, like address, chip select, hold, and so on. if necessary, such signals can be provided by general purpose i/os. features summary the lcd bus interface provides: ? support of two different control signals modes: ? mod80 with separate read and write strobe ? mod68 with read/write signal and data strobe ?e? with selectable level ? dma for read and write operations ? 8/16/32-bit write and read operations ? programmable transfer speed (100 khz ? 3.2 mhz) through ? selectable clock input ? programmable transfer time ? programmable wait states ? interrupt generation selectable upon two events ? internal data transfer allowed ? external bus access completed ? flags that indicate the status of the data register and the progress of data transfer to or from the lcd controller
912 chapter 24 lcd bus interface (lcd-i/f) user?s manual u17566ee5v1um00 note 1. the programmer has to make sure that the timing requirements of the external lcd controller are met. 2. for electrical characteristics please refer to the data sheet. 3. if the concerned pins are configured as lcd bus interface pins change between input and output is performed automatically by lcd bus interface read and write operations. refer also to ?port group 9? on page 86 . 24.1.1 description data can be read from and written to the lcd bus interface by either involving the dma controller or by directly accessing the interface from the cpu. the timing of the external bus signals is determined by register settings (wst and cyc). the lcd bus interface is 8 bits wide. in order to improve performance, the interface is equipped with a 32-bit register that allows the cpu or dma to access the data register with 8-, 16-, or 32-bit data accesses. the interface automatically generates 1, 2, or 4 consecutive (8-bit) accesses on the external bus. the lcd bus interface has an internal 32-bit write buffer that allows the next data to be written to the data register (lbdata0) while a transfer on the external bus interface is in progress. the following figure shows the main components of the lcd bus interface. figure 24-1 lcd bus interface block diagram as shown in the figure, the result of a read operation is directly available in the lbdata0 and lbdatar0 registers. for data output, the contents of the lbdata0 register is copied to the 32-bit write buffer. internal bus spclk0 (16 mhz) spclk1 (8 mhz) spclk2 (4 mhz) spclk5 (500 khz) lbctl0 lbcyc0 lbwst0 lbdata0 lbdatar0 re g ister set clock selector write buffer dbd[7:0] mod80/ mod68 selector control dbwr ( r/w ) dbrd ( e ) intlcd timin g generator
913 lcd bus interface (lcd-i/f) chapter 24 user?s manual u17566ee5v1um00 the external signals are listed in the following table. 24.1.2 lcd bus interface access modes the lcd bus interface can access the external lcd controller/driver in two different modes. the mode is selected by the bit lbctl0.imd. ? mod80 the control signals wr (dbwr ) and rd (dbrd ) are used to control the external lcd controller/driver. ? mod68 the control signals r/w (dbwr ) and e (dbrd ) are used to control the external component. the level of e depends on the setting of the bit lbctl0.el0: ? el0=0: e is active high; data is read/written on the falling edge. ? el0=1: e is active low; data is read/written on the rising edge. 24.1.3 access types to the lbdata0 register access to the lbdata0 register can be performed as: ? byte access (8-bit) ? halfword access (16-bit) ? word access (32-bit) note 1. every access must address the base address of the lbdata0 register. access to the individual bytes within the register is prohibited. 2. before writing to or reading from the lbdata0 register or reading the lbdatar0 register, always make sure that the busy flag lbctl0.byf is zero. (1) write operation if there is no transfer in progress on the external bus interface, the new data is immediately transferred to the external lcd controller. if there is a transfer in progress, the new data is transferred after the current transfer has completed. one, two or four bytes are transferred through the bus interface, depending on how lbdata0 was accessed (byte, halfword, or word). the write timing on the external bus interface is determined by the number of wait cycles (lbwst0.wst[4:0]), the cycle time (lbcyc0.cyc[5:0]) and the selected clock (lbctl0.lbc00 and lbctl0.lbc01). table 24-1 lcd bus interface external connections signal name i/o active level reset level function dbwr o l h mod80: write strobe (wr ) mod68: read/write (r/w ) dbrd ol a a) the active level of e in mod68 is controlled by the bit lbctl0.el0. h mod80: read strobe (rd ) mod68: e strobe (e) dbd[7:0] i/o l lcd data bus
914 chapter 24 lcd bus interface (lcd-i/f) user?s manual u17566ee5v1um00 (2) read operation when the cpu or the dma reads the lbdata0 register, the read operation on the lcd bus interface is started. if there is a write transfer in progress while the lbdata0 register shall be read, the read transfer is stalled and started after the write transfer has completed. the value read from the register is the data from the previous transfer. therefore, an initial dummy read operation is required to update the register. as soon as the data of the actual transfer is available in the lbdata0 register, the busy flag lbctl0.byf0 is cleared and the data can be retrieved with the next read operation. successive reads from the lbdata0 register provide the desired data. the read timing on the external bus interface is determined by the number of wait cycles (lbwst0.wst0[4:0]), the cycle time (lbcyc0.cyc0[5:0]) and the selected clock (lbctl0.lbc0 and lbctl00.lbc01). (3) read operation without initiating a bus transfer data can be read from the lbdatar0 register without initiating a new read transfer via the lcd bus interface. the read access to the lbdatar0 register is useful when previous read accesses to the lbdata0 register have been performed and only the last transferred data shall be read without starting a new lcd bus transfer. 24.1.4 interrupt generation an interrupt is generated on write and read accesses to the lcd bus interface. depending on the setting of the bit lbctl0.tcis0, the interrupt is generated differently. table 24-2 controlling interrupt generation of the lcd bus interface access tcis0 = 0 tcis0 = 1 write an interrupt is generated as soon as data is transferred from lbdata0 to the write buffer. then lbdata0 is ready to accept next data. the write buffer is filled whenever the external bus interface is idle (no transfer in progress) and data is available in lbdata0. an interrupt is generated as soon as the write transfer via the bus interface has completed. the transfer can consist of 1, 2, or 4 bytes dependent on the access to lbdata0. read an interrupt is generated as soon as the data is available in the lbdata0 or lbdatar0 register. depending on the read access to lbdata0 (byte, halfword or word) 1, 2, or 4 bytes are transferred and placed in the lbdata0 and lbdatar0 register. finally, the interrupt is generated in order to indicate that new data is available. an interrupt is generated as soon as the read transfer via the bus interface has completed. the transfer can consist of 1, 2, or 4 bytes depending on the access to lbdata0 or lbdatar0.
915 lcd bus interface (lcd-i/f) chapter 24 user?s manual u17566ee5v1um00 24.2 lcd bus interface registers the lcd bus interface is controlled and operated by means of the following registers: table 24-3 lcd bus interface registers overview register name shortcut address lcd bus interface control register lbctl0 ffff fb60 h lcd bus interface cycle time register lbcyc0 ffff fb61 h lcd bus interface wait states register lbwst0 ffff fb62 h lcd bus interface data register lbdata0w ffff fb70 h lbdata0 lbdata0l lcd bus interface data (read) register lbdatar0w ffff fb74 h lbdatar0 lbdatar0l
916 chapter 24 lcd bus interface (lcd-i/f) user?s manual u17566ee5v1um00 (1) lbctl0 - lcd bus interface control register the 8-bit lbctl0 register controls the operation of the lcd bus interface. access this register can be read/written in 8-bit or 1-bit units. address ffff fb60 h initial value 00 h . this register is cleared by any reset. 76543210 el0 imd0 lbc01 lbc00 tcis0 0 tpf0 byf0 r/w r/w r/w r/w r/w r r r table 24-4 lbctl0 register contents bit position bit name function 7 el0 level of signal ?e? in mod68 mode 0: e is active high; data is read/written on the falling edge. 1: e is active low, data is read/written on the rising edge. 6 imd0 mode of external bus interface access 0: mod80 mode - control signals are wr and rd 1: mod68 mode - control signals are e and r/w 5 to 4 lbc0[1:0] selects the internal clock lbc01 lbc00 selected clock 00 spclk0 01 spclk1 10 spclk2 11 spclk5 3 tcis0 select interrupt generation 0: during write access to the bus interface, an interrupt is generated as soon as data is transferred from lbdata0 to the write buffer. during read access from the bus interface, an interrupt is generated as soon as data is available in the lbdata0 and lbdatar0 registers. that means the interrupt is generated when the ?data register busy? flag byf0 is reset to 0. 1: an interrupt is generated as soon as the read or write transfer via the bus interface has completed. that means the interrupt is generated when the ?transfer in progress? flag tpf0 is reset to 0. as for read operations, in both cases the data is available in the data register lbdata(r)0 when the interrupt is generated. 1 tpf0 transfer in progress on external bus interface 0: the external bus interface is idle 1: data is transferred on the external bus interface 0 byf0 data register busy 0: data can be read or written from/to lbdata0 data can be read from lbdatar0 1: register lbdata0 (lbdatar0) is busy
917 lcd bus interface (lcd-i/f) chapter 24 user?s manual u17566ee5v1um00 (2) lbcyc0 - lcd bus interface cycle time register the 8-bit lbcyc0 register determines the cycle time of the lcd bus interface. the cycle time is the duration of one bus access for transferring one byte. access this register can be read/written in 8-bit or 1-bit units. address ffff fb61 h initial value 02 h . this register is initialized by any reset. note 1. t is the clock period of the selected spclk. 2. always keep lbcyc0 > 2. 76543210 0 0 cyc05 cyc04 cyc03 cyc02 cyc01 cyc00 r r r/w r/w r/w r/w r/w r/w table 24-5 lbcyc0 register contents bit position bit name function 5 to 0 cyc0[5:0] sets the cycle time of the lcd bus interface. cyc0[5:0] cycle time 000000 b setting prohibited 000001 b setting prohibited 000010 b cycle time is 2*t 000011 b cycle time is 3*t ... ... 111111 b cycle time is 63*t
918 chapter 24 lcd bus interface (lcd-i/f) user?s manual u17566ee5v1um00 (3) lbwst0 - lcd bus interface wait state register the 8-bit lbwst0 register determines the number of wait states of the lcd bus interface. the number of wait states defines the duration of the dbwr and dbrd signals. this duration must remain below the cycle time. access this register can be read/written in 8-bit or 1-bit units. address ffff fb62 h initial value 00 h . this register is cleared by any reset. note always keep lbwst0.wst0 < lbcyc0.cyc0 ? 2. 76543210 0 0 0 wst04 wst03 wst02 wst01 wst00 r r r r/w r/w r/w r/w r/w table 24-6 lbwst0 register contents bit position bit name function 4 to 0 wst0[4:0] sets the number of wait states of the lcd bus interface. wst0[4:0] wait states 00000 b no wait state inserted 00001 b 1 wait state 00010 b 2 wait states 00011 b 3 wait states ... ... 11111 b 31 wait states
919 lcd bus interface (lcd-i/f) chapter 24 user?s manual u17566ee5v1um00 (4) lbdata0 - lcd bus interface data register the 32-bit lbdata0 register contains the data that is transferred via the lcd bus interface. access this register can be read/written in 3 different units under following names: ? lbdata0w: 32-bit access ? lbdata0: 16-bit access ? lbdata0l: 8-bit access address ffff fb70 h initial value 0000 0000 h . this register is cleared by any reset. access types depending on the access to this register (byte, halfword or word), a defined number of transfers via the external bus interface are performed: ?byte: the byte is transferred via the bus interface. ? halfword: the halfword is split into 2 bytes that are transferred consecutively via the bus interface. ? word: the word is split into 4 bytes that are transferred consecutively via the bus interface. when the data is split into bytes and transferred consecutively, the byte order is as follows: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 data 1514131211109876543210 data table 24-7 lbdata0w register contents bit position bit name function 31 to 0 data[31:0] data that is written to or read from the lcd bus interface table 24-8 lbdata0 register contents bit position bit name function 15 to 0 data[15:0] data that is written to or read from the lcd bus interface table 24-9 lbdata0l register contents bit position bit name function 7 to 0 data[7:0] data that is written to or read from the lcd bus interface 31 24 23 16 15 8 7 0 4 th byte 3 rd byte 2 nd byte 1 st byte
920 chapter 24 lcd bus interface (lcd-i/f) user?s manual u17566ee5v1um00 write to this register a write operation to this register sets the busy flag lbctl0.byf0 immediately. if there is no lcd bus transfer in progress (lbctl0.tpf0 = 0), the data is copied to the write buffer and lbctl0.byf0 is cleared. if there is a transfer going on (lbctl0.tpf0 = 1), the data is not copied to the write buffer until the transfer has completed. as soon as the transfer is complete, the data is copied to the write buffer and lbctl0.byf0 is cleared. a transfer via the lcd bus interface starts as soon as the lbdata0 register is copied to the write buffer. this is indicated by the interrupt intlcd that becomes active, provided that lbctl0.tcis0 = 0. read from this register a read operation from this register initiates a read transfer via the lcd bus interface. the data that is read from the register is always the data that was received during the previous transfer from the lcd bus interface. note 1. every access must address the base address of the lbdata0 register. access to the individual bytes within the register is prohibited. 2. lbctl0.byf0 must be zero when accessing this register.
921 lcd bus interface (lcd-i/f) chapter 24 user?s manual u17566ee5v1um00 (5) lbdatar0 - lcd bus interface data register the lbdatar0 register is read-only. it contains the data of the last previous read transfer via the lcd bus interface. reading this register does not start a new read transfer on the lcd bus interface. access this register can be read/written in 3 different units under following names: ? lbdatar0w: 32-bit access ? lbdatar0: 16-bit access ? lbdatar0l: 8-bit access address ffff fb74 h initial value 0000 0000 h . this register is cleared by any reset. this register can be read to obtain data that was transferred during a previous read operation to the lbdata0 register?without initiating a further lcd bus transfer. reading the lbdatar0 register does not change the status of the lbctl0.byf0 and lbctl0.tpf0 flags. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 data 1514131211109876543210 data table 24-10 lbdatar0w register contents bit position bit name function 31 to 0 data[31:0] data that was previously read from the lcd bus interface table 24-11 lbdatar0 register contents bit position bit name function 15 to 0 data[15:0] data that was previously read from the lcd bus interface table 24-12 lbdatar0l register contents bit position bit name function 7 to 0 data[7:0] data that was previously read from the lcd bus interface
922 chapter 24 lcd bus interface (lcd-i/f) user?s manual u17566ee5v1um00 24.3 timing this section starts with the general timing and then presents examples of consecutive write and read operations. 24.3.1 timing dependencies the following figure shows the general timing when the mod80 mode is used. it illustrates the effect of the lbcyc0 and lbwst0 register settings. it explains also the impact of lbctl0.tcis on the interrupt generation. figure 24-2 lcd bus interface timing (mod80 mode) in mod80 mode, dbwr provides the write strobe wr and dbrd the read strobe rd . note 1. t is the clock period of the selected spclk. 2. cyc is the chosen number of clock cycles (lbcyc0.cyc0). always keep lbcyc0.cyc0 > 2. 3. wst is the chosen number of wait states (lbwst0). always keep lbwst0.swst0 < (lbcyc0.cyc0 ? 2). the only difference in mod68 mode is, that dbwr provides the read/write r/w strobe and dbrd the e strobe. the active edge of the e strobe is defined by lbctl0.el0. dbwr dbrd dbd[7:0] internal interrupt (tcis=0) on write on read (tcis=1) (write) data (wst+1) * t cyc * t data dbd[7:0] (read) read or write byte from/to lbdata register by cpu or dma next byte
923 lcd bus interface (lcd-i/f) chapter 24 user?s manual u17566ee5v1um00 24.3.2 lcd bus i/f states during and after accesses changing between input and output mode of the lcd bus pins db[7:0] is done automatically after they are configured as lcd bus interface pins via the port configuration registers. after the pins are configured as db[7:0] they are operating in input mode. during and after a bus read access db[7:0] are operating in input mode and retain this mode also after the read access is completed. during and after a bus write access db[7:0] are operating in output mode and retain this mode also after the write access is completed. 24.3.3 writing to the lcd bus this section shows typical sequences of writing words, halfwords and bytes to the lcd bus. (1) writing words writing a word transmits four bytes to the external lcd controller/driver. figure 24-3 timing (mod80: lbtctl0.imd0 = 0): write word, lbwst0.wst0 = 5, lbcyc0.cyc0 = 8, lbctl0.tcis0 = 0 note the timing diagrams are for functional explanation purposes only without any relevance to the real hardware implementation. sequence 1. a word of lcd data is written to the lbdata0 register. the internal bus transfer takes some clocks until the register is updated. then the busy flag lbctl0.byf0 is set until the data is copied to the write buffer. 2. the lbdata0 register contents is copied to the write buffer. this clears lbctl0.byf0 and causes the interrupt output to become active for one clock cycle. transfer on the external bus interface starts with byte 0. the ?transfer in progress? flag lbctl0.tpf0 is set to indicate that a transfer is in progress. write word to lbdata0 register byte0 byte1 dbwr spclk dbrd dbd[7:0] lbctl0.byf0 lbdata0 word (consists of byte0 ? byte3) byte2 byte3 internal write buffer word lbctl0.tpf0 intlcd (lbctl0.tcis0=0) intlcd (lbctl0.tcis0=1)
924 chapter 24 lcd bus interface (lcd-i/f) user?s manual u17566ee5v1um00 3. all four bytes of the word are transferred back-to-back via the external bus interface. 4. after the transfer on the external bus interface has been completed, the lbctl0.tpf0 is cleared. (2) writing halfwords writing a halfword transmits two bytes to the external lcd controller/driver. figure 24-4 timing (mod80: lbtctl0.imd0 = 0): write consecutive halfwords, lbwst0.wst0 = 5, lbcyc0.cyc0 = 8, lbctl0.tcis0 = 0 note the timing diagrams are for functional explanation purposes only without any relevance to the real hardware implementation. sequence 1. the first halfword of lcd data is written to the lbdata0 register. the internal bus transfer takes some clocks until the interface register is written. then the busy flag lbctl0.byf0 is set until the data is copied to the write buffer. 2. the lbdata0 register contents is copied to the write buffer. this clears lbctl0.byf0 and causes the interrupt output to become active for one clock cycle. transfer on the external bus interface starts with byte 0. the flag lbctl0.tpf0 is set to indicate that a transfer is in progress. 3. caused by the interrupt, the dma writes a second halfword to lbdata0. the cpu can write this halfword as well after it has checked the busy flag lbctl0.byf0. the internal bus transfer again takes some clock cycles until the lbdata0 register is written and lbctl0.byf0 is set. 4. because the transfer (two bytes) on the external bus interface is still going on and the lbdata0 register contents can not be copied to the write buffer immediately, lbctl0.byf0 is set. 5. after the transfer over the external bus interface has been completed, the write buffer is filled with the contents of lbdata0. the busy flag lbctl0.byf0 is cleared, and the interrupt output intlcd becomes active for one clock cycle. filling the write buffer starts a new transfer to the external lcd controller. write 1 st halfword to lbdata0 register byte0 byte1 dbwr spclk dbrd dbd[7:0] lbctl0.byf0 intlcd lbdata0 1 st halfword (consists of byte0 and byte1) byte0 byte1 internal write buffer 1 st halfword 2 nd halfword (consists of byte0 and byte1) 2 nd halfword lbctl0.tpf0 write 2 nd halfword to lbdata0 register
925 lcd bus interface (lcd-i/f) chapter 24 user?s manual u17566ee5v1um00 (3) writing bytes writing consecutive bytes transmits these bytes to the external lcd controller/ driver. figure 24-5 timing (mod68 mode: lbtctl0.imd0 = 1): write consecutive bytes, lbwst0.wst0 = 5, lbcyc0.cyc0 = 8, , lbctl0.tcis0 = 0 note the timing diagrams are for functional explanation purposes only without any relevance to the real hardware implementation. sequence 1. the first byte of lcd data is written to the lbdata0 register. the internal bus transfer takes some clocks until the register of the interface is written. then the busy flag lbctl0.byf0 is set until the data is copied to the write buffer. 2. the lbdata0 register contents is copied to the write buffer. this clears lbctl0.byf0 and causes the interrupt output to become active for one clock cycle. transfer on the external bus interface is started. the flag lbctl0.tpf0 is set to indicate that a transfer is in progress. 3. caused by the interrupt, the dma writes a second byte to lbdata0. the cpu can write this byte as well after it has checked the busy flag lbctl0.byf0. the internal bus transfer again takes some clock cycles until the lbdata0 register is written and lbctl0.byf0 is set. 4. since the transfer (one byte) on the external bus interface is still going on and the lbdata0 register contents can not be copied to the write buffer immediately, the busy flag lbctl0.byf0 remains set. 5. after the transfer on the external bus interface has been completed, the write buffer is filled with the contents of lbdata0. the busy flag lbctl0.byf0 is cleared and the interrupt output intlcd becomes active for one clock cycle. filling the write buffer starts a new transfer to the external lcd controller. write 1st byte to lbdata0 register spclk dbwr(r/w) dbd[7:0] lbdata0 internal write buffer dbrd(e) lbctl.el=0 lbctl0.tpf0 lbctl0.byf0 intlcd dbrd(e) lbctl.el=1 1st byte 3rd byte 2nd byte 1st byte 2nd byte 3rd byte 1st byte 2nd byte 3rd byte write 2nd byte to lbdata0 register write 3rd byte to lbdata0 register
926 chapter 24 lcd bus interface (lcd-i/f) user?s manual u17566ee5v1um00 24.3.4 reading from the lcd bus you can read from the lcd bus in word, halfword, or byte format. the following shows typical sequences of reading words and bytes. (1) reading words reading a word requires the transmission of four bytes. figure 24-6 timing (mod80: lbtctl0.imd0 = 0): read word, lbwst0.wst0 = 5, lbcyc0.cyc0 = 8, lbctl0.tcis0 = 0 and 1 note the timing diagrams are for functional explanation purposes only without any relevance to the real hardware implementation. sequence 1. a dummy read to the lbdata0 register starts the transfer of four bytes from the external lcd controller. the busy flag lbctl0.byf0 is set immediately. the ?transfer in progress? flag lbctl0.tpf0 is set on the rising edge of the clock. the data that is read from lbdata0 belongs to a previous transfer and may be ignored. 2. when the last of the four bytes is sampled and the complete word is available in the lbdata0 register, the busy flag lbctl0.byf0 is cleared. the lbctl0.tpf0 flag remains set until the cycle time of the last byte has elapsed. 3. a following read to the lbdata0 register provides the lcd controller data and initiates a new transfer. dummy read word from lbdata0 register byte0 dbwr spclk dbrd dbd[7:0] l bctl0.byf0 intlcd (lbctl0.tcis0=0) intlcd (lbctl0.tcis0=1) lbdata0 word (byte0..byte3) byte1 byte2 byte3 read word from lbdata0 register lbctl0.tpf0 sample point
927 lcd bus interface (lcd-i/f) chapter 24 user?s manual u17566ee5v1um00 (2) reading bytes the following figure shows a byte read operation in mod68 mode. figure 24-7 timing (mod68: lbtctl0.imd0 = 1): read consecutive bytes, lbwst0.wst0 = 4, lbcyc0.cyc0 = 7, lbctl0.tcis0 = 0 note the timing diagrams are for functional explanation purposes only without any relevance to the real hardware implementation. sequence 1. a dummy read to the lbdata0 register starts the transfer of one byte from the external lcd controller. the busy flag lbctl0.byf0 is set immediately. the ?transfer in progress? flag lbctl0.tpf0 is set on the rising edge of the clock. the data that is read from lbdata0 belongs to a previous transfer and may be ignored. 2. when the data on the lcd bus interface is sampled, lbctl0.byf0 is cleared and the data is available in lbdata0. the interrupt output intlcd becomes active for one clock cycle. 3. a new read to lbdata0 is performed while the previous transfer has not been finished (cycle time not elapsed). the busy flag lbctl0.byf0 is set immediately, but the new transfer is started after the previous one is complete. the ?transfer in progress flag? lbctl0.tpf0 remains set. the data that is read from lbdata0 is the first lcd data byte. 4. again, the data that has been sampled is available in lbdata0 and the busy flag lbctl0.byf0 is cleared. 5. steps 2 to 4 are repeated until the last byte to be read has been sampled. 6. the last byte is not read from the lbdata0 register but from lbdatar0 in order to avoid a further read transfer on the lcd bus. dummy read byte from lbdata0 register spclk dbd[7:0] lbctl0.byf0 intlcd lbdata0 1 st byte 2 nd byte 3 rd byte read 1 st byte from lbdata0 register lbctl0.tpf0 2 nd byte read 2 nd byte from lbdata0 register 3 rd byte sample point dbwr(r/w) 1 st byte dbrd(e) lbctl .el=0 dbrd(e) lbctl .el=1 read 3 rd byte from lbdata0 r register without initiating a new transfer
928 chapter 24 lcd bus interface (lcd-i/f) user?s manual u17566ee5v1um00 24.3.5 write-read-write sequence on the lcd bus figure 24-8 shows an example when a write access to the lcd bus is immediately followed by a read access and vice versa. the example is given in mod80 mode (lbctl0.imd0 = 0) with byte transfers. in mode68 mode (lbctl0.imd0 = 1) the timing is equivalent, when the the rd strobe is considered as the low active e signal (lbctl0.el0 = 1) figure 24-8 timing (mod80: lbtctl0.imd0 = 0): byte write-read-write, lbwst0.wst = 4, lbcyc0.cyc = 7, lbctl0.tcis = 0 lbdata0 lbctl0.byf0 lbctl0.tpf0 dbd[7:0] write w1 lbdata0l read lbdatal w1 read r1 lbdatar0l w1 r1 r1 write w2 lbdata0l w2 w2 cyc tcyc tcyc t wr rd
929 user?s manual u17566ee5v1um00 chapter 25 sound generator (sg) the sound generator (sg0) generates an audio-frequency tone signal and a high-frequency pulse-width modulated (pwm) signal. the duty cycle of the pwm signal defines the volume. by default, the two signal components are routed to separate pins. but both signals can also be combined to generate a composite signal that can be used to drive a loudspeaker circuit. 25.1 overview the sound generator consists of a programmable square wave tone generator and a programmable pulse-width modulator. the pwm includes an internal automatic logarithmic decrement unit (ald). the ald can be used to reduce the tone volume over time without cpu intervention. features summary special features of the sound generator are: ? programmable tone frequency (100 hz to 6 khz with a minimum step size of 20 hz) ? programmable volume level (9 bit resolution) ? automatic logarithmic volume decrement function (ald): ? volume reduction without cpu interaction ? programmable sound duration (256 steps) ? sound duration associated with tone frequency (gong effect) ? interrupt generation when programmable volume low level is reached ? wide range of pwm signal frequency (32 khz to 64 khz) ? sound can be stopped or retriggered (even if the ald is switched on) ? composite or separated frequency/volume output for external circuitry variation ? hardware-optimized update of frequency and volume to avoid audible artifacts
930 chapter 25 sound generator (sg) user?s manual u17566ee5v1um00 25.1.1 description the following figure provides a functional block diagram of the sound generator. figure 25-1 sound generator block diagram the sound generator's input clock sg0clk is the 16 mhz clock pclk0. tone generator the tone generator consists of two up-counters with compare registers. the values written to the frequency registers are automatically copied to compare buffers. the counters are reset to zero when their values match the contents of the associated compare buffers. the 9-bit counter sg0fl generates a clock with a frequency between 32 khz and 64 khz. this clock constitutes the pwm frequency. it is also the input of the second 9-bit counter sg0fh. the resulting tone signal behind the by-two-divider has a frequency between 100 hz and 6 khz and a 50 % duty cycle. pwm the pwm modulates the duty cycle according to the desired volume. it is controlled by the volume register sg0pwm. the value written to this register is automatically copied to the associated volume compare buffer. the pwm continually compares the value of the counter sg0fl with the contents of its volume compare buffer. the rs flipflop of the pwm is set by the pulses generated by the counter sg0fl. it is reset when the sg0fl counter value matches the contents of the volume buffer. thus, the pwm output signal can have a duty cycle between 0 % (null volume) and 100 % (maximum volume). the pwm frequency is above 32 khz and hence outside the audible range. outputs the sound generator is connected to the pins sgo and sgoa. by default, pin sgo provides the tone signal sg0of and pin sgoa the pwm signal sg0oa that holds the volume (?amplitude?) information. if bit sg0ctl.os is set, pin sgo provides the composite signal sg0o that can directly control a speaker circuit. & f pwm (min. 32 khz) f tone (100 hz to 6 khz) sg0pwm auto logarithmic decrement sg0pwm volume compare buffer 8-bit sg0sdf auto-decrement counter f decrement sg0ith ? sg0a sgo sg0fh tone compare buffer 9-bit s0gfh tone 9-bit sg0fh tone counter sg0fl frequency compare buffer 9-bit s0gfl frequency counter clear f pwm (32 to 64 khz) s r & pwm tone /2 match load match load clear load match rs-ff sg0ctl.alds 0 0 1 1 sg0ctl.pwr 0 1 sg0ctl.os 0 1 cpu write to sg0pwm sg0clk = pclk0 (16mhz) intsg0 sg0fl frequency low register sg0fh frequency high register sg0ith interrupt threshold register sg0pwm volume register sg0sdf sound duration register = 0? reset & sg0of sg0 sg0oa 2 x f tone (200 hz to 12 khz) y y y f pwm (32 to 64 khz)
931 sound generator (sg) chapter 25 user?s manual u17566ee5v1um00 25.1.2 principle of operation the software-controlled registers sg0fl, sg0fh, and sg0pwm are equipped with hardware buffers. the sound generator operates on these buffers. this approach eliminates audible artifacts, because the buffers are only updated in synchronization with the generated tone waveform. note this section provides an overview. for details please refer to ?sound generator operation? on page 939 . (1) generation of the tone frequency the tone frequency is determined by two counters and their associated compare register values. two counters are necessary to keep the tone pulse and the pwm signal synchronized. the first counter (sg0fl) provides the input to the second (sg0fh) and also to the pwm. it is used to keep the pwm frequency outside the audio range (above 30 khz) and within the signal bandwidth of the external sound system (usually below 64 khz). its match value defines also the 100 % volume level. the second counter (sg0fh) generates the tone frequency (100 hz to 6khz). note if the target values of the counters sg0fl/sg0fh are changed to generate a different tone frequency, the volume register sg0pwm has to be adjusted to keep the same volume. (2) generation of the volume information the volume information (the ?amplitude? of the audible signal) is provided as a high-frequency pwm signal. in composite mode, the pwm signal is anded with the tone signal, as illustrated in the following figure. figure 25-2 generation of the composite output signal after low-pass filtering, the analog signal amplitude corresponds to the duty cycle of the pwm signal. low-pass filtering (averaging) is an inherent characteristic of a loudspeaker system. the duty cycle can vary between 0 % and 100 %. its generation is controlled by the counter register sg0fl and the volume register sg0pwm. tone signal pwm signal, duty cycle 66 % composite signal analog audio signal 100% 66% 0%
932 chapter 25 sound generator (sg) user?s manual u17566ee5v1um00 when the volume register sg0pwm is cleared, the sound stops immediately. (3) automatic fading the automatic logarithmic decrement function (ald) provides an automatic volume reduction without cpu interaction. in regular intervals (related to the tone frequency, selectable via register sg0sdf), the ald divides the present contents of the volume buffer by 32 (truncated) and subtracts the result from the buffer value. the logarithmic reduction creates the impression of a linear volume reduction in the human ear. the initial volume that is defined by the contents of the volume register sg0pwm remains unchanged. (4) interrupt generation when the ald is switched on, the sound generator generates the interrupt request intsg0. this interrupt signals that the sound volume has decreased to a certain level (set in register sg0ith). because the sound duration depends on the tone frequency and the contents of the sound duration register sg0sdf, intsg0 can be used to indicate ?sound is low? or ?sound has ended?. this interrupt is generated only once after the start volume level has been written to sg0pwm. 25.2 sound generator registers the sound generator is controlled by means of the following registers: table 25-1 sound generator registers overview register name shortcut address sg0 frequency low register sg0fl sg0 frequency high register sg0fh + 2 h sg0 volume register sg0pwm + 4 h sg0 sound duration factor register sg0sdf + 6 h sg0 control register sg0ctl + 7 h sg0 interrupt threshold register sg0ith + 8 h table 25-2 sound generator register base address module base address sg0 ffff f5a0 h
933 sound generator (sg) chapter 25 user?s manual u17566ee5v1um00 (1) sg0ctl - sg0 control register the 8-bit sg0ctl register controls the operation of the sound generator. access this register can be read/written in 8-bit or 1-bit units. address + 7 h initial value 00 h . this register is cleared by any reset. note change the contents of this register only when the sound is stopped (register sg0pwm cleared). 76543 2 1 0 000pwr0 0 osalds rrrr/wr r r/wr/w table 25-3 sg0ctl register contents bit position bit name function 4 pwr power save mode selection: 0: clock input switched off ( the sound generator is disabled and does not operate). 1: clock input switched on ( the sound generator is enabled and ready to use). 1 os sg0 output mode selection: 0: selects sgof and sgoa outputs (frequency and amplitude separated). 1: selects sgo output (frequency and amplitude mixed). 0 alds automatic logarithmic decrement of volume (ald) selection: 0: ald switched off. 1: ald activated.
934 chapter 25 sound generator (sg) user?s manual u17566ee5v1um00 (2) sg0fl - sg0 frequency low register the 16-bit sg0fl register is used to specify the target value for the pwm frequency. it holds the target value for the 9-bit counter sg0fl. access this register is can be read/written in 16-bit units. it cannot be written if bit sg0ctl.pwr = 0. the sg0fl register can also be read/written together with the sg0fh register by 32-bit access via the sg0f register. address initial value 0000 h . this register is cleared by any reset. for the calculation of the resulting pwm frequency refer to ?pwm calculations? on page 942 . the value written to sg0fl defines also the reference value for the maximum sound amplitude (100% pwm duty cycle). a 100 % duty cycle (continually high) will be generated if the sg0pwm value is higher than the sg0fl value. for details see ?pwm calculations? on page 942 ). note 1. the bits sg0fl[15:9] are not used. 2. the maximum value to be written is 510 (01fe h ). this yields a pwm frequency of 31.3 khz. the minimum value to be written depends on the capability of the external circuit. a value of 255 (00ff h ) would yield a pwm frequency of 62.5 khz. 3. the value read from this register does not necessarily reflect the current pwm frequency, because this frequency is determined by the frequency compare buffer value. the buffer might not be updated yet. for details see ?updating the frequency buffer values? on page 939 . 1514131211109876543210 0000000 counter sg0fl target value rrrrrrr r/w
935 sound generator (sg) chapter 25 user?s manual u17566ee5v1um00 (3) sg0fh - sg0 frequency high register the 16-bit sg0fh register is used to specify the final tone frequency. it holds the target value for the 9-bit counter sg0fh. access this register is can be read/written in 16-bit units. it cannot be written if bit sg0ctl.pwr = 0. the sg0fh register can also be read/written together with the sg0fl register by 32-bit access to the sg0fl register via the sg0f register. address + 2 h initial value 0000 h . this register is cleared by any reset. for the calculation of the resulting tone frequency refer to ?tone frequency calculation? on page 940 . note 1. the bits sg0fh[15:9] are not used. 2. legal values depend on the contents of register sg0fl which defines the frequency of the input pulse. for example: if the counter sg0fl generates a frequency of 32.4 khz, a value of 161 would generate a tone frequency of 100 hz. 3. the value read from this register does not necessarily reflect the current tone frequency, because this frequency is determined by the frequency compare buffer value. the buffer might not be updated yet. for details see ?updating the frequency buffer values? on page 939 . (4) sg0f - sg0 frequency register the 32-bit register sg0f combines access to the 16-bit registers sg0fl and sg0h. this makes it possible to change the values for the pwm and tone frequency with one write access. access this register is can be read/written in 32-bit units. it cannot be written if bit sg0ctl.pwr = 0. address initial value 0000 0000 h . this register is cleared by any reset. 1514131211109876543210 0000000 counter sg0fh target value rrrrrrr r/w 31 16 15 0 sg0fh sg0fl
936 chapter 25 sound generator (sg) user?s manual u17566ee5v1um00 (5) sg0pwm - sg0 volume register the 16-bit register sg0pwm is used to specify the sound volume. it holds the target value for the sound amplitude that is given by the duty cycle of the pwm signal. when the ald is switched on, this is the start value. access this register is can be read/written in 16-bit units. it cannot be written if bit sg0ctl.pwr = 0. address + 4 h initial value 0000 h . this register is cleared by any reset. the value written to this register must be considered in conjunction with the contents of register sg0fl. the register sg0fl specifies the maximum value of the counter sg0fl. for the calculation of the resulting duty cycle refer to ?pwm calculations? on page 942 . the setting takes effect after the sg0pwm buffer has been updated (see ?updating the volume buffer value? on page 941 ). note 1. the bits 15:9 are not used. 2. the value read from this register does not necessarily reflect the current volume, because the value of counter sg0fl is compared with the contents of the volume buffer. the buffer might not be updated yet or changed by the ald function. 3. the value of this register remains unchanged when the ald is switched on. 4. the sound stops immediately when this register is cleared. 1514131211109876543210 0000000 sound volume target value rrrrrrr r/w
937 sound generator (sg) chapter 25 user?s manual u17566ee5v1um00 (6) sg0sdf - sg0 sound duration factor register the 8-bit register sg0sdf is used to specify the duration of the sound when the ald is switched on. it defines the number of tone signal edges between two successive volume reductions. access this register can be read/written in 8-bit or 1-bit units. address + 6 h initial value 00 h . this register is cleared by any reset. the ald is synchronized with the tone signal. with this register, the ald is instructed to reduce the volume at every nth edge (falling or rising) of the tone signal. the correspondence between the value written to sg0sdf and n is shown in the following table. because both edges are counted, the maximum time between two successive volume reductions is 128 times the tone period. note change the contents of this register only when the sound is stopped (register sg0pwm cleared). 76543210 no. of edges between two volume reductions r/w r/w r/w r/w r/w r/w r/w r/w table 25-4 ald cycle rate sg0sdf value n 0000 0000 b 1 0000 0001 b 2 ... ... 1111 1111 b 256
938 chapter 25 sound generator (sg) user?s manual u17566ee5v1um00 (7) sg0ith - sg0 interrupt threshold register the 16-bit register sg0ith is used to specify the volume level for the interrupt request intsg0. when the ald is switched on, the sound volume is stepwise reduced. this is done by reducing the value of the volume buffer. intsg0 is generated when the value of the volume buffer is equal to or less than the value written to sg0ith. intsg0 is never generated when the ald is switched off. access this register is can be read/written in 16-bit units. address + 8 h initial value 0000 h . this register is cleared by any reset. to avoid glitches, the intsg0 interrupt is only generated at a falling edge of the tone signal. if the condition is met at a rising edge, the interrupt will be generated at the next falling edge of the tone signal. note 1. the bits 15:9 are not used. 2. change the contents of this register only when the sound is stopped (register sg0pwm cleared). when the ald is switched on, a write access to the sg0pwm volume register starts the comparison of the sg0ith register contents with the volume buffer. the comparison ends after intsg0 has been generated. to revive the comparison, you must first write to sg0pwm. this restarts the tone. 1514131211109876543210 0000000 interrupt threshold value rrrrrrr r/w
939 sound generator (sg) chapter 25 user?s manual u17566ee5v1um00 25.3 sound generator operation this section explains the details of the sound generator. 25.3.1 generating the tone the tone signal is generated by the compare match signal of the sg0fh counter value with the value of the sg0fh buffer, followed by a by-two-divider. at each compare match, the counter is reset to zero. remember that the sg0fh counter is clocked by the output of the sg0fl counter. (1) updating the frequency buffer values the values of the frequency buffers can be changed by writing to the associated frequency registers sg0fl and sg0fh. both registers can be written together via sg0f. changing the value of the sg0fl (equivalent to sg0f[15:0]) register would also yield a change of the pwm frequency, i.e. the sound volume. therefore it is obligatory to write the correct pwm value to sg0pwm before a new sg0f value is copied to the frequency buffers. the sg0f register contents is copied to the buffers when the following sequence is detected: 1. cpu write access to sg0pwm register occurred. 2. sg0fh counter value and sg0fh buffer value have matched. this match is equivalent to the next edge (rising or falling) of the tone signal. the following figure shows an example (not to scale). figure 25-3 update timing of the frequency buffers up to the next match, frequency registers and associated buffers can hold different values. if a 309 hz tone is generated, as in the above example, the time span between writing to the sg0pwm register and updating the buffer can be up to 3.24 ms. sg0f (32 bit) 000 h 03b h 003b 01ae h 0027 01ae h 003b h 0027 h 001 h sg0clk write sg0pwm sg0fh buffer sg0fh compare match sg0fh counter (step 1) (step 2) 03a h 039 h 038 h
940 chapter 25 sound generator (sg) user?s manual u17566ee5v1um00 (2) tone frequency calculation the tone frequency can be calculated as: f tone = f sg0clk / (([sg0fl buffer] + 1) ([sg0fh buffer] + 1) 2) where: f sg0clk = frequency of the sg0 input clock [sg0fl buffer] = contents of the sg0fl buffer [sg0fh buffer] = contents of the sg0fh buffer example if: ?f sg0clk = 16 mhz ? [sg0fl buffer] = 255 (00ff h ) (this yields a pwm frequency of 62.5 khz) ? [sg0fh buffer] = 32 (0020 h ) then: ?f tone = 947 hz note note that the buffer contents can differ from the contents of the associated register until the next compare match. 25.3.2 generating the volume information the sound volume information is generated by comparing the sg0fl counter value with the contents of the sg0pwm volume buffer. an rs flipflop is set when the counter matches the sg0fl buffer and reset when the counter reaches the value of the volume buffer sg0pwm. figure 25-4 pwm signal generation the duty cycle of the pwm signal is determined by the difference between the contents of the sg0fl counter buffer and the contents of the sg0pwm volume buffer. the larger the difference, the smaller the duty cycle. the pwm signal is continually high when the value of the volume buffer is higher than the value of the frequency compare buffer. pwm signal (rs flip- flop output ) t sg0fl counter value sg0fl buffer value (when reached, sets the ff) sg0pwm buffer value (when reached, resets the ff)
941 sound generator (sg) chapter 25 user?s manual u17566ee5v1um00 note to achieve 100 % duty cycle for all pwm frequencies, sgofl must not be set to a value above 1fe h . the pwm signal is continually low when the value of the volume buffer is zero ? the sound has stopped. (1) updating the volume buffer value the value of the volume compare buffer can be changed by writing to the volume register sg0pwm. it is also changed by the ald function. ? if the register is cleared by writing 0000 h , the register value is copied to the volume compare buffer with the next rising edge of sg0clk. ? as a result, the sound stops at the latest after one period of sg0clk. ? if a non-zero value is written to the register, the buffer is updated with the next falling or rising edge of the tone frequency (match between sg0fh counter value and sg0fh buffer value). when the ald is switched on (sg0ctl.alds = 1) and no write access to the sg0pwm register occurred, the ald reduces the contents of the volume buffer gradually. if sg0pwm is written between two reductions, the new value takes precedence over the ald, and the volume buffer is updated.
942 chapter 25 sound generator (sg) user?s manual u17566ee5v1um00 (2) pwm calculations pwm frequency the pwm frequency is generated by the counter sg0fl. it can be calculated as: f pwm = f sg0clk / (([sg0fl buffer] + 1) where: f sg0clk = frequency of the sg0 input clock [sg0fl buffer] = contents of the sg0fl buffer duty cycle the duty cycle of the pwm signal is calculated as follows: ? if [sg0pwm buffer] > [sg0fl buffer]: duty cycle = 100 % ?if 0  [sg0pwm buffer]  [sg0fl buffer]: duty cycle = [sg0pwm buffer] / ([sg0fl buffer] + 1) where: [sg0pwm buffer] = contents of sg0pwm buffer [sg0fl buffer] = contents of sg0fl buffer example if [sg0fl] is set to 240 (00f0 h ), the following table applies: the table shows, how the contents of register sg0fl affects the achievable volume resolution. table 25-5 duty cycle calculation example [sg0pwm] calculation duty cycle [%] 01ff h 100 ... 100 00f1 h 241 / 241 100 00f0 h 240 / 241 99.6 00ef h 239 / 241 99.2 ... ... ... 0001 h 1 / 241 0.41 0000 h 0 / 241 0
943 sound generator (sg) chapter 25 user?s manual u17566ee5v1um00 (3) automatic fading the built-in automatic logarithmic decrement function (ald) can be used to reduce the volume gradually to zero without cpu intervention. the logarithmic decrease matches the sensitivity of the human ear and creates the impression of a linearly decaying sound. a sound started with sg0ctl.alds = 1 will automatically fade away. the fading can be stopped by writing to the sg0pwm register. the speed of the volume reduction is controlled by the sound duration factor register sg0sdf. depending on the value written to sg0sdf, a new amplitude value is calculated at every nth edge (rising or falling) of the tone signal. the range of n is 1 to 256. scthe calculation of the volume reduction uses 13-bit arithmetic and follows below procedure: pwm8[0] = sg0pwm;// initial pwm output ov13[0] = sg0pwm << 5 + 31;// in 13-bit fo r (n=1, n< n+1; n++){ nv13[n] = ov13[n-1]-(ov13[n-1]>>5);// dec r ement in 13-bit pwm8[n] = nv13[n] >> 5;// new pwm output } where: pwm8[n]: 8-bit pwm output value ov13[n]: internal old value in 13-bit nv13[n]: internal new value in 13-bit n: number of volume reduction steps because the sg0pwm register is not affected, the present volume value cannot be read from that register. the sound stops when the volume buffer value becomes zero. the number of repetitions depends on the start value set in register sg0pwm. to avoid an initial delay with apparently no effect, the start value shall not exceed the value of register sg0fl by more than 1. the total sound duration depends on ? the start value, ? the sound duration factor set in register sg0sdf, ? the tone frequency. example the subsequent table shows two examples of the sound duration for minimum and maximum tone frequency.
944 chapter 25 sound generator (sg) user?s manual u17566ee5v1um00 the following settings are assumed: ?f sg0clk = 16 mhz ? [sg0fl] = 332 (this yields a pwm frequency of 48.048 khz) ? [sg0pwm] = 333 (100 % volume) ? a) [sg0fh] = 3 (this yields a tone frequency of 6.006 khz) ? b) [sg0fh] = 240 (this yields a tone frequency of 99.69 hz) table 25-6 sound duration example tone frequency reduced at every tone edge reduced at every 2nd tone edge ... reduced at every 256th tone edge sound duration [roughly sec] 6006 hz 0.018 0.035 ... 4.58 99.69 hz 1.08 2.15 ... 275
945 sound generator (sg) chapter 25 user?s manual u17566ee5v1um00 25.4 sound generator application hints this section provides supplementary programming information. 25.4.1 initialization to enable the sound generator, set sg0ctl.pwr to 1. this connects the sg0 to the clock sg0clk. check bit sg0ctl.os. when sg0ctl.os is 0, the signal at pin sgo is a symmetrical square waveform with the frequency f tone . when sg0ctl.os is 1, the signal at pin sgo is composed of the tone signal and pwm pulses. the frequency data registers sg0fl and sg0fh provide the buffer values for the counters. the combined value represents the frequency of the tone. 25.4.2 start and stop sound the sound is started by writing a non-zero value to the volume register sg0pwm. before starting the sound, all other register settings must be made. the sound is stopped by writing 0000 h to the volume register sg0pwm. the sound is stopped regardless of the current value of amplitude output or frequency output. thus, the sound can be stopped quickly, even if a very low sound frequency is chosen. when the ald is switched on, the sound stops automatically when the contents of the volume buffer reaches zero. 25.4.3 change sound volume the sound volume is changed by writing a new value to register sg0pwm. the new volume takes effect with the next edge of the tone pulse (rising or falling). note when the ald is switched on, the current volume value cannot be read from register sg0pwm. 25.4.4 intsg0 interrupt the interrupt intsg0 is only generated when the ald is active (sg0ctl.alds = 1). intsg0 is generated when the value of the volume buffer is equal to or less than the value written to sg0ith. this can be used to reconfigure the sound generator when a certain volume level is reached. the interrupt does not stop the ald sound.
946 chapter 25 sound generator (sg) user?s manual u17566ee5v1um00 25.4.5 constant sound volume a sound started with sg0ctl.alds = 0 is output with the volume value written to sg0pwm. the sound is output continually and does not stop automatically. it has to be stopped by writing 0000 h to the sg0pwm register. 25.4.6 generate special sounds to generate special sounds (like blinker clicks etc.), frequency and volume can be changed simultaneously. to change the frequency of a sound that has already started: 1. write to frequency register sg0fl in 32-bit mode (or to sg0fl and sg0fh separately in 16-bit mode). 2. write to volume register sg0pwm.
947 user?s manual u17566ee5v1um00 chapter 26 power supply scheme the microcontroller has general power supply pins for its core, internal memory and peripherals. these pins are connected to internal voltage regulators. the microcontroller also has dedicated power supply pins for certain i/o modules. these pins provide the power for the i/o operations. 26.1 overview the following table gives the naming convention of the pins: dedicated function v dd or v ss 5 n cpu core, internal memory and peripherals ? vdd: voltage drain drain ? vss: voltage for substrate and source level 5 v (nominative) instance number a a/d converter, voltage comparators b standard i/o buffer d ? pd70f3421, pd70f3422, pd70f3423: lcd controller/driver driver i/o ? pd70f3424, pd70f3425, pd70f3426a: lcd bus interface i/o ? pd70f3427: d[31:16] ports, includes lcd bus interface i/o sm stepper motor controller/driver i/o m ? pd70f3427: external memory i/f pins (except d[31:16] ports)
948 chapter 26 power supply scheme user?s manual u17566ee5v1um00 the following pins belong to the power supply scheme: note for electrical characteristics refer to the data sheet. table 26-1 power supply pins pin connected to pd70f3421, pd70f3422, pd70f3423 pd70f3424, pd70f3425, pd70f3426a pd70f3427 vdd50 / vss50 cpu core pin pair is connected to voltage regulator 0. regc0 capacitor for voltage regulator 0 for pin pair vdd50 / vss50. vdd51 / vss51 cpu core pin pair is connected to voltage regulator 0. regc1 capacitor for voltage regulator 1 for pin pair vdd51 / vss51 vdd52 / vss52 clock generation circuit and peripherals power-on-clear circuit pin pair is connected to a voltage regulator 1. regc2 capacitor for voltage regulator 2 for pin pair vdd52 / vss52 avdd / avss a/d converter (power supply) voltage comparators avref a/d converter (reference input level) bvdd5n / bvss5n i/o buffer (n = 0, 1) dvdd50 / dvss50 lcd controller/driver i/o lcd bus interface i/o d[31:16] ports, including lcd bus interface i/o dvdd51 / dvss51 ?? smvdd5n / smvss5n stepper motor controller/driver (n = 0, 1) mvdd5n / mvss5n ?? external memory i/f, except d[31:16] (n = 0 to 4)
949 power supply scheme chapter 26 user?s manual u17566ee5v1um00 26.2 description 26.2.1 devices pd70f3421, pd70f3422, pd70f3423 figure 26-1 gives an overview of the allocation of power supply pins of the pd70f3421, pd70f3422, pd70f3423 devices. their functional assignment is depicted in more detail in figure 26-2 . note the diagrams do not show the exact pin location. figure 26-1 power supply pins for pd70f3421, pd70f3422, pd70f3423 figure 26-2 functional assignment of power supply pins (pd70f3421, pd70f3422, pd70f3423) adc vc avref avdd avss smvs s50 smvdd50 smvs s51 smvdd51 bvss50 bvdd50 cpu ram flash standard i/o regulator 0 vss50 vdd50 regc0 vdd52 regc2 vss52 vss51 regc1 vdd51 bvss50 bvdd50 stepper motor i/o clockgen peripherals poc regulator 1 lcd-c/d com/seg dvdd50 dvss50 bvdd51 bvss51 vdd50 vdd51 vss50 vss51 vdd52 vss52 bvdd50 bvdd51 bvss50 bvss51 dvdd50 dvss50 stepper motor buffer smvdd50 smvdd51 smvss50 smvss51 adc avdd avref avss voltage compa- rators i/o buffer lcd i/o buffer lcd i/o buffer lcd voltage generation reg 0 regc2 regc1 regc0 peripherals clockgen poc core reg 1
950 chapter 26 power supply scheme user?s manual u17566ee5v1um00 26.2.2 devices pd70f3424, pd70f3425, pd70f3426a figure 26-3 gives an overview of the allocation of power supply pins of the pd70f3424, pd70f3425, pd70f3426a devices. their functional assignment is depicted in more detail in figure 26-4 . note the diagrams do not show the exact pin location. figure 26-3 power supply pins for pd70f3424, pd70f3425, pd70f3426a figure 26-4 functional assignment of power supply pins for pd70f3424, pd70f3425, pd70f3426a adc vc a v r e f a v d d a v s s cpu ram flash standard i/o regulator 0 b v d d 5 0 b v s s 5 0 vss50 vdd50 regc0 s m v s s 5 1 s m v d d 5 1 s m v s s 5 0 s m v d d 5 0 vdd52 regc2 vss52 vss51 regc1 vdd51 bvss50 bvdd50 stepper motor i/o clockgen peripherals poc regulator 1 lcd bus i/f i/o dvdd50 dvss50 bvdd51 bvss51 reg 0 regc2 regc1 regc0 vdd50 vdd51 vss50 vss51 peripherals clockgen poc vdd52 vss52 i/o buffer bvdd50 bvdd51 bvss50 bvss51 lcd-i/f i/o buffer dvdd50 dvss50 stepper motor buffer smvdd50 smvdd51 smvss50 smvss51 adc avdd a vref avss core voltage compa- rators reg 1
951 power supply scheme chapter 26 user?s manual u17566ee5v1um00 26.2.3 device pd70f3427 figure 26-5 gives an overview of the allocation of power supply pins of the pd70f3427 devices. their functional assignment is depicted in more detail in figure 26-6 . note the diagrams do not show the exact pin location. figure 26-5 power supply pins for pd70f3427 figure 26-6 functional assignment of power supply pins for pd70f3427 adc vc a v r e f a v d d a v s s cpu ram flash standard i/o regulator 0 b v d d 5 0 b v s s 5 0 vss50 vdd50 regc0 s m v s s 5 1 s m v d d 5 1 s m v s s 5 0 s m v d d 5 0 vss51 regc1 vdd51 bvss50 bvdd50 stepper motor i/o clockgen peripherals poc vdd52 regc2 vss52 regulator 1 bvdd51 bvss51 dvdd51 dvss51 lcd bus i/f i/o dvdd50 d[31:16] dvss50 ext. mem. i/f i/o mvss50 to mvss54 mvss50 to mvss54 vdd50 vdd51 vss50 vss51 vdd52 vss52 bvdd50 bvdd51 bvss50 bvss51 dvdd50 dvss50 stepper motor buffer smvdd50 smvdd51 smvss50 smvss51 adc avdd avref avss voltage compa- rators i/o buffer lcd i/o buffer lcd i/o buffer lcd voltage generation reg 0 regc2 regc1 regc0 peripherals clockgen poc core reg 1
952 chapter 26 power supply scheme user?s manual u17566ee5v1um00 26.3 voltage regulators the on-chip voltage regulators generate the voltages for the internal circuitry (cpu core, clock generation circuit and peripherals), refer to figure 26-2 , figure 26-4 and figure 26-6 . the regulators operate per default in all operation modes (normal operation, halt, idle, stop, watch, sub-watch, and during reset). during power save modes the voltage regulators can be optionally disabled by setting the stbctl register (refer to ?control registers for power save modes? on page 169 ). note to stabilize the output voltage of the regulator, connect a capacitor to the regc pin. refer to the data sheet.
953 user?s manual u17566ee5v1um00 chapter 27 reset several system reset functions are provided in order to initialize hardware and registers. 27.1 overview features summary a reset can be caused by the following events: ? external reset signal reset noise in the external reset signal is eliminated by an analog filter. ? power-on-clear (internal signal respoc) ? overflow of the watchdog timer (internal signal reswdt) ? main or sub-oscillator fails (internal signals rescmm, rescms) ? software reset (internal signal ressw) as output, the reset function provides two internal reset signals: ? sysres (system reset) ? sysreswdt (watchdog timer reset)
954 chapter 27 reset user?s manual u17566ee5v1um00 27.1.1 general reset performance the following figure shows the signals involved in the reset function: figure 27-1 reset function signal diagram all resets are applied asynchronously. that means, resets are not synchronized to any internal clock. this ensures that the microcontroller can be kept in reset state even if all internal clocks fail to operate. the reset function provides two internal reset signals: ? system reset sysres sysres is activated by all reset sources. ? watchdog reset sysreswdt sysreswdt is activated by power-on-clear and external reset only. both resets provoke different reset behaviour of the watchdog timer. for details refer to the ?watchdog timer (wdt)? on page 565 . (1) variable reset vector the flash memory devices allow to program the start address of the user?s program, instead of starting at address 0000 0000 h . the variable reset vector is stored in the extra area of the flash memory and can be written by an external flash programmer or in self-programming mode. re s poc re s et re s cmm re s cm s re s wdt re ss w s y s re s s y s re s wdt re ss tat intern a l bus re s et re s poc: re ss tat = 01 h re s ext: re ss tat = 02 h
955 reset chapter 27 user?s manual u17566ee5v1um00 (2) hardware status with each reset function the hardware is initialized (including the watchdog). when the reset status is released, program execution is started. the following table describes the status of the clocks during reset and after reset release. note that the clock status "operates" does not inevitably mean that any function using this clock source operates as well. the function may additionally require to be enabled by other means. table 27-1 hardware status during and after reset item during reset after reset main oscillator stops oscillation stopped a a) the main oscillator is started by the internal firmware. however the application software has to ensure stable main oscillation before utilizing this clock for any purpose. sscg and pll must be started by the application software. assure also here that the stabilization time has passed. see chapter ?clock generator? on page 139 for details. sub oscillator operates starts oscillation internal oscillator operates starts oscillation the internal oscillator clock is the default clock source after reset release. sscg clock stops operation stopped a pll clock stops operation stopped a cpu system clock (vbclk) stops operation starts oscillation based on the internal oscillator clock. cpu initialized program execution starts after oscillation stabilization time. watchdog timer (wdtclk) stops operation starts operation based on internal oscillator clock watch timer (wtclk) stops operation starts operation based on internal oscillator clock peripheral clocks stop operation ? pclk0?2: operating based on internal-osc ? pclk3-15: stopped ? spclk0?2: operating based on internal-osc ? spclk3-15: stopped on-chip peripheral functions stop operation depends on availability of peripheral clock and default status of the peripheral function. i/o pins (port/alternative function pins) all pins are in input port mode b . see chapter ?pin functions? on page 27 for a description. b) the status of the n-wire debug interface pins drst (p05), ddi (p52), ddo (p53), dck (p54), dms (p55) after reset depends on the reset value of the ocdm register, and therefore on the reset source. see chapter ?pin functions? on page 27 for details.
956 chapter 27 reset user?s manual u17566ee5v1um00 (3) register status with each reset function the registers of the cpu, internal ram, and on-chip peripheral i/os are initialized. since after reset the internal firmware is processed, some resources hold a different value as after reset, when the user?s program is started. after a reset, make sure to set the registers to the values needed within your program. table 27-2 initial values of cpu and internal ram after reset on-chip hardware register name initial value after reset at start of user?s program cpu program registers general-purpose register (r0) 0000 0000 h 0000 0000 h general-purpose registers (r1 to r31) undefined undefined program counter (pc) 0000 0000 h variable reset vector programmed to flash extra area system registers status save registers during interrupt (eipc, eipsw) undefined undefined status save registers during non- maskable interrupt (nmi) (fepc, fepsw) undefined undefined interrupt cause register (ecr) 0000 0000 h 0000 0000 h program status word (psw) 0000 0020 h ? 0000 0020 h : if no security flags or variable reset vector are set ? 0000 0021 h : else status save registers during callt execution (ctpc, ctpsw) undefined undefined status save registers during exception/debug trap (dbpc, dbpsw) undefined undefined callt base pointer (ctbp) undefined undefined internal ram after power-on after power-on-clear reset the entire ram contents is undefined. undefined undefined after reset if a reset occurs while writing to a ram memory block, the contents of that ram memory block may be corrupted. all other ram memory blocks are not affected. refer also to the note below the table. all data in previous state ?03ff0000 h -03ff07ff h : undefined all other data in previous state or undefined (refer to note below). after any other reset any internal generated reset does not change the ram contents. all data in previous state ?03ff0000 h -03ff07ff h : undefined all other data in previous state. peripherals macro internal registers the reset values of the various registers are given in the chapters of the peripheral functions
957 reset chapter 27 user?s manual u17566ee5v1um00 note in the table above, ?undefined? means either undefined at the time of a power-on reset, or undefined due to data destruction when the falling edge of the external reset signal corrupts an ongoing ram write access. the internal ram of the microcontroller comprises several separate ram blocks. in case writing to one ram block while a reset occurs the contents of only this ram block may be corrupted. the other ram blocks remain unchanged. 27.1.2 reset at power-on the power-on-clear circuit (poc) permanently compares the power supply voltage v dd with an internal reference voltage (v ip ). it ensures that the microcontroller only operates as long as the power supply exceeds a well- defined limit. when the power supply voltage falls below the internal reference voltage (v dd 958 chapter 27 reset user?s manual u17566ee5v1um00 27.1.3 external reset reset is performed when a low level signal is applied to the reset pin. the reset status is released when the signal applied to the reset pin changes from low to high. after the external reset is released, the resstat register is cleared and the resstat.resext bit is set (resstat = 02 h , refer also to ?resstat - reset source flag register? on page 960 for the interaction between power-on-clear and external reset ). the system reset signals sysres and sysreswdt are generated. the reset pin incorporates a noise eliminator, which is applied to the reset signal reset . to prevent erroneous external reset due to noise, it uses an analog filter. even if no clock is active in the controller the external reset can keep the controller in reset state. note the internal system reset signals sysres and sysreswdt keep their active level for at least four system clock cycles after the reset pin is released. the following figure shows the timing when an external reset is performed. it explains the effect of the noise eliminator. the noise eliminator uses the analog delay to prevent the generation of an external reset due to noise. the analog delay is caused by the analog input filter. the filter regards pulses up to a certain width as noise and suppresses them. for the minimum reset pulse width refer to the data sheet. figure 27-3 external reset timing min. 4 roclk cycles internal system reset signal analog delay (eliminated as noise) reset cpu clock main oscillator (moclk) analog delay analog delay internal oscillator (roclk)
959 reset chapter 27 user?s manual u17566ee5v1um00 27.1.4 reset by watchdog timer the watchdog timer can be configured to generate a reset if the watchdog time expires. after watchdog reset, the resstat.reswdt bit is set. the system reset signal sysres is generated. after watchdog timer overflow, the reset status lasts for a specific time. then the reset status is automatically released. 27.1.5 reset by clock monitor the two clock monitors generate a reset when either the main oscillator or the sub-oscillator fails. after a clock monitor reset, the corresponding bit (resstat.rescmm or resstat.rescms) is set. the system reset signal sysres is generated. after a clock monitor reset, the reset status lasts for a specific time. then the reset status is automatically released. 27.1.6 software reset software reset is generated by two consecutive write accesses: 1. suspend write protection of resswt register: byte write access to register rescmd (content of the data is not relevant) 2. generate software reset: byte write access to register resswt (content of the data is not relevant) these two steps are required in order to prevent an unintentional software reset. the registers rescmd and resswt are always read as 00 h . after software reset, the resstat.ressw bit is set. the system reset signal sysres is generated.
960 chapter 27 reset user?s manual u17566ee5v1um00 27.2 reset registers the reset functions are controlled and operated by means of the following registers: (1) resstat - reset source flag register the 8-bit resstat register contains information about which type of resets occurred since the last power-on-clear or external reset or after the last software clear of the register. each following reset condition sets the corresponding flag in the register. for example, if a power-on-clear reset is finished and then a watchdog timer reset occurs, the resstat reads xxx1 0001 b . access the register can be read/written in 8-bit units. address ffff ff20 h initial value power-on-clear reset sets this register to 01 h . external reset sets this register to 02 h . table 27-3 reset function registers overview register name shortcut address reset source flag register resstat ffff ff20 h software reset register resswt ffff ff22 h software reset enable register rescmd ffff ff24 h reset status register res ffff ff26 h 76543210 x x ressw reswdt rescm2 rescm1 resext respoc rrr/w a a) any write clears this register, independent of the data written. r/w a r/w a r/w a r/w a r/w a table 27-4 resstat register contents (1/2) bit position bit name function 5 ressw software reset 0: not generated. 1: generated. 4 reswdt reset by watchdog timer 0: not generated. 1: generated. 3 rescm2 reset by clock monitor of sub oscillator 0: not generated. 1: generated.
961 reset chapter 27 user?s manual u17566ee5v1um00 note if clearing this register by writing and flag setting (occurrence of reset) conflict, flag setting takes precedence. respoc and resext both power-on-clear and external reset set resstat to different initial states. ? power-on-clear reset sets resstat = 01 h ? external reset sets resstat = 02 h special caution is required if both reset events are active concurrently: ? if the power-on-clear reset is longer active than the external reset : resstat = 01 h . that means resstat indicates only the occurrence of the power-on-clear reset. ? if the external reset is longer active than the power-on-clear reset: resstat = 02 h .that means resstat indicates only the occurrence of the external reset . ? if the power-on-clear reset and external reset has been released simultaneously: resstat = 03 h . that means resstat indicate the occurrence of both reset events. all other reset events just set their respective bit in resstat and do not change the others. (2) resswt - software reset register write operation to the 8-bit resswt register generates a software reset. the content of data written to resswt is not relevant. writing to this register is protected by a special sequence of instructions. to enable write access to resswt, first write to rescmd. please refer to ?write protected registers? on page 135 for details. the register is always read as 00 h . access this register can only be written in 8-bit units. address ffff ff22 h initial value 00 h 2 rescm1 reset by clock monitor of main oscillator 0: not generated. 1: generated. 1 resext external reset 0: not generated. 1: generated. 0 respoc reset at power-on-clear 0: not generated. 1: generated. table 27-4 resstat register contents (2/2) bit position bit name function 76543210 00000000 wwwwwwww
962 chapter 27 reset user?s manual u17566ee5v1um00 (3) rescmd - software reset enable register immediately after writing data to the 8-bit rescmd register, write access to the resswt register is enabled. the content of data written to rescmd register is not relevant. the register is always read as 00 h . access this register can only be written in 8-bit units. address ffff ff24 h initial value 00 h caution in case a high level programming language is used, make sure that the compiler translates the two write instructions to rescmd and resswt into two consecutive assembler ?store? instructions. (4) res - reset status register the 8-bit res register indicates the status of a write attempt to a register protected by rescmd (see also ?rescmd - software reset enable register? on page 962 ). the register is always read as 00 h . access this register can be read/written in 8-bit units. address ffff ff26 h initial value 00 h note res.rerr is set, if a write access to register resmd is not directly followed by a write access to one of the write-protected registers. 76543210 00000000 wwwwwwww 76543210 0000000rerr r a a) these bits may be written, but write is ignored. r a r a r a r a r a r a r/w table 27-5 res register contents bit position bit name function 0 rerr write error status: 0: write access was successful. 1: write access failed. you can clear this register by writing 0 to it. setting this register to 1 by software is not possible.
963 user?s manual u17566ee5v1um00 chapter 28 voltage comparator the microcontroller has two instances of a voltage comparator. note throughout this chapter, the individual instances of the voltage comparator are identified by ?n?, for example intvcn for the generated interrupt signal. 28.1 overview the voltage comparator compares an external voltage v cmpn at pin vcmpn and the internal reference voltage v lv i and generates an interrupt if v cmpn 964 chapter 28 voltage comparator user?s manual u17566ee5v1um00 28.1.1 description each voltage comparator consists of an operation amplifier and a logic block. the operation amplifier is connected to the external voltage (v cmpn ) with one input and to an internal reference voltage (v lv i ) with the other. it shares the reference voltage supply with the power regulators. the comparator output is fed into a logic block that generates the interrupt signal intvcn and sets or clears the flag vcstrn.vcfn. the comparison result is also output to the vcmpon pins. the figure below shows a block diagram of the voltage comparator. figure 28-1 voltage comparator block diagram 28.1.2 comparison results voltage comparison leads to the following results: ? output signal vcmpon and flag vcstrn.vcfn ?v cmpn v lv i : the output signal vcmpon of the voltage comparator is high and the flag vcstrn.vcfn is set. ? interrupt signal intvcn depending on the settings of bits vcctln.esn[1:0], the interrupt signal intvcn is generated upon one or both of the above transitions of v cmpn . 28.1.3 stand-by mode in order to reduce power consumption during stop mode, the voltage comparator can be set into stand-by mode. this is done by setting vcctln.vcen = 0. if the voltage comparator is set in stand-by mode it assumes that v cmpn >v lv i (vcstrn.vcfn = 1 and vcmpon = high level). logic block + - v lvi v cmpn vcmpn vcmpon intvcn vcstrn.vcfn
965 voltage comparator chapter 28 user?s manual u17566ee5v1um00 28.2 voltage comparator registers the voltage comparator is controlled by means of the following registers: (1) vcctln - voltage comparator n control register the 8-bit vcctln register controls whether the voltage comparator is operating or is in stand-by mode. further it specifies whether an interrupt is generated when v cmpn rises above or falls below v lv i or any at of both transitions. access this register can be read/written in 8-bit or 1-bit units. address initial value 00 h . this register is cleared by any reset. table 28-1 voltage comparator registers overview register name shortcut address voltage comparator n control register vcctln voltage comparator n status register vcstrn + 2 h table 28-2 base addresses of voltage comparator instances instance number base address 0 ffff ff10 h 1 ffff ff14 h 76543210 vcen00000esn1esn0 r/w r r r r r r/w r/w table 28-3 vcctln register contents bit position bit name function 7 vcen enable voltage comparator 0: stand-by (vcstrn.vcfn = 1, vcmpon = high level) 1: operating 1 to 0 esn[1:0] vcmpon edge selection for interrupt esn1 esn0 operation 00 falling edge 01 rising edge 10 reserved 11 both edges
966 chapter 28 voltage comparator user?s manual u17566ee5v1um00 caution if the voltage comparator input level v cmpn is below the reference voltage v lv i an intvcn interrupt is generated under both following conditions: ? the comparator is enabled (vcctln.vcen = 0  1) and falling or both edges are specified (vcctln.vcen = 00 b or 11 b ). ? the comparator is disabled (vcctln.vcen = 1  0) and rising or both edges are specified (vcctln.vcen = 01 b or 11 b ). (2) vcstrn - voltage comparator n status register the 8-bit vcstrn register reflects the result of the voltage comparison. access this register is read-only, in 8-bit or 1-bit units. address + 2 h initial value 01 h . this register is cleared by any reset. 76543210 0000000vcfn rrrrrrrr table 28-4 vcstrn register contents bit position bit name function 0 vcfn voltage comparator status flag 0: input voltage is below reference voltage. 1: input voltage is above reference voltage.
967 voltage comparator chapter 28 user?s manual u17566ee5v1um00 28.3 timing the following figure shows the timing of the voltage comparator. in this example, the interrupt intvcn is generated at the falling edge (vcctln.estn[1:0] = 00 b ) of the comparator?s output signal. figure 28-2 voltage comparator timing note for details on the delay time refer to the data sheet. extern a l volt a ge intern a l reference volt a ge vcmpon intvcn del a y del a y time del a y del a y del a y vc s trn.vcfn
968 chapter 28 voltage comparator user?s manual u17566ee5v1um00
969 user?s manual u17566ee5v1um00 chapter 29 on-chip debug unit the microcontroller includes an on-chip debug unit. by connecting an n-wire emulator, on-chip debugging can be executed. 29.1 functional outline 29.1.1 debug functions (1) debug interface communication with the host machine is established by using the drst , dck, dms, ddi, and ddo signals via an n-wire emulator. the communication specifications of n-wire are used for the interface. (2) on-chip debug on-chip debugging can be executed by preparing wiring and a connector for on-chip debugging on the target system. an n-wire emulator is used to connect the host pc to the on-chip debug unit. (3) forced reset function the microcontroller can be forcibly reset. (4) break reset function the cpu can be started in the debug mode immediately after reset of the cpu is released. (5) forced break function execution of the user program can be forcibly aborted. (6) hardware break function two breakpoints for instruction and data access can be used. the instruction breakpoint can abort program execution at any address. the access breakpoint can abort program execution by data access to any address. (7) software break function up to eight software breakpoints can be set in the internal flash memory area. the number of software breakpoints that can be set in the ram area differs depending on the debugger to be used. the software breakpoints utilize the ?dbtrap? rom correction function. thus following software breakpoints can be set: ? 8 breakpoints in the vfb flash memory address range ? 8 breakpoints in the vsb flash memory address range (pd70f3426a only)
970 chapter 29 on-chip debug unit user?s manual u17566ee5v1um00 (8) debug monitor function a memory space for debugging that is different from the user memory space is used during debugging (background monitor mode). the user program can be executed starting from any address. while execution of the user program is aborted, the user resources (such as memory and i/o) can be read and written, and the user program can be downloaded. (9) mask function each of the following signals can be masked. that means these signals will not be effective during debugging. the correspondence with the mask functions of the debugger (id850nwc) for the n-wire emulator (ie-v850e1-cd-nw) of nec electronics is shown below. (10) timer function the execution time of the user program can be measured. (11) peripheral macro operation/st op selection function during break depending on the debugger to be used, certain peripheral macros can be configured to continue or to stop operation upon a breakpoint hit. ? functions that are always stopped during break ? watchdog timer ? functions that can operate or be stopped during break (however, each function cannot be selected individually) ? a/d converter ? all timers p ? all timers z ?timer y ?watch timer ? peripheral functions that continue operating during break (functions that cannot be stopped) ? peripheral functions other than above (12) function during power saving modes when the device is set into a power saving mode, debug operation is not possible. when exiting the power save mode, the on-chip debug unit continues operation. the n-wire interface is still accessible during power saving modes: ? n-wire emulator can get status information from the on-chip debug unit. ? stop mode can be released by the n-wire emulator. ? nmi0 mask function: nmi pin ? nmiwdt mask function: watchdog timer interrupt nmiwdt ? reset mask function: all reset sources
971 on-chip debug unit chapter 29 user?s manual u17566ee5v1um00 29.1.2 security function this microcontroller has a n-wire security function, that demands the user to input an id code upon start of the debugger. the id code is compared to a predefined id code, written in advance to the internal flash memory by an external flash programmer. this function prevents unauthorized persons to operate the microcontroller in n-wire debug mode and to read the internal flash memory area. the id code in the internal flash memory can be written by an external flash programmer or in self-programming mode. id code be sure to write an id code when writing a program to the internal flash memory. the area of the id code is 10 bytes wide and in the range of addresses 0000 0070 h to 0000 0079 h . the id code when the memory is erased is shown below. security bit bit 7 of address 0000 0079 h enables or disables use of the n-wire emulator. ? bit 7 of address 0000 0079 h 0: disabled n-wire emulator cannot connect to the on-chip debug unit. 1: enabled n-wire emulator can connect to the on-chip debug unit if the 10-byte id code input matches the id code stored in the flash memory the security bit can be modified by an external flash programmer or in self- programming mode. after reset the entire id code area is set to ff h . this means that ? n-wire debugging is generally enabled ? the id code is ff h for all id code bytes consequently controller access is possible without any restriction. caution if access via the n-wire interface should be disabled "block erase disabled" should be configured as well. otherwise the flash memory blocks containing the id code could be erased and n-wire access could be enabled. address id code 0000 0079 h ff h 0000 0078 h ff h 0000 0077 h ff h 0000 0076 h ff h 0000 0075 h ff h 0000 0074 h ff h 0000 0073 h ff h 0000 0072 h ff h 0000 0071 h ff h 0000 0070 h ff h
972 chapter 29 on-chip debug unit user?s manual u17566ee5v1um00 security disable the entire id code, i.e. also the security bit 7 of address 0000 0079 h , can be made temporarily ineffective by software. this is achieved by setting the control bit rsudisc.dis = 1. setting rsudisc.dis = 1 does not change the security bit. thus after a power-on-clear reset the n-wire security is effective again. the n-wire security function can not be suspended when the microcontroller is operating in n-wire debug mode. (1) rsudisc- n-wire security disable control register the 8-bit rsudisc register is used to temporarily disable the n-wire security function. access this register can be read/written in 8-bit or 1-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?rsudiscp - rsudisc write protection register? on page 973 for details. address ffff f9e0 h . initial value 00 h . this register is cleared by power-on-clear reset. rsudisc.dis can not be changed, while the microcontroller is operating in n-wire debug mode, i.e. while the concerned ports are operating as n-wire debug pins (ocdm.ocdm0 = 1). thus proceed as follows to ? enable n-wire debugging (from status ocdm.ocdm0 = 0): ? set rsudisc.dis = 1 (disable n-wire security) ? set ocdm.ocdm0 = 1 (ports are n-wire pins) ? disable n-wire debugging (from status ocdm.ocdm0 = 1): ? set ocdm.ocdm0 = 0 (ports are not n-wire pins) ? set rsudisc.dis = 0 (ensable n-wire security) 76543 2 1 0 00000 0 0 dis rrrrr r r r/w table 29-1 rsudisc register contents bit position bit name function 0 dis n-wire security function disable: 0: n-wire security function enabled. 1: n-wire security function disabled.
973 on-chip debug unit chapter 29 user?s manual u17566ee5v1um00 (2) rsudiscp - rsudisc write protection register the 8-bit rsudiscp register protects the register rsudisc from inadvertent write access. after data has been written to the rsudiscp register, the first write access to register rsudisc is valid. all subsequent write accesses are ignored. thus, the value of rsudisc can only be rewritten in a specified sequence, and illegal write access is inhibited. access this register can only be written in 8-bit units. address ffff fca4 h initial value the contents of this register is undefined. after writing to the rsudiscp register, you are permitted to write once to rsudisc. the write access to rsudisc must happen with the immediately following instruction. 76543210 xxxxxxxx wwwwwwww
974 chapter 29 on-chip debug unit user?s manual u17566ee5v1um00 29.2 controlling the n-wire interface the n-wire interface pins drst , ddi, ddo, dck, dms are shared with port functions, see table 29-2. during debugging the respective device pins are forced into the n-wire interface mode and port functions are not available. note that n-wire debugging must be generally permitted by the security bit in the id code region (*0x0000 0079[bit7] = 1) of the flash memory. an internal pull-down resistor - detachable by software - is provided at the drst pin to keep the n-wire interface in reset, if no debugger is connected. (1) ocdm - on-chip debug mode register the ocdm0 control bit in the ocdm register determines the function of these device pins. the register can be read or written in 8-bit and 1-bit units. address ffff f9fc h the reset value of ocdm.ocdm0 depends on the reset source. (2) power-on-clear respoc respoc (power-on-clear) reset sets ocdm.ocdm0 = 0, i.e. the pins are defined as port pins. the debugger can not communicate with the controller and the n-wire debug circuit is disabled. the first cpu instructions after respoc can not be controlled by the debugger. the application software must set ocdm.ocdm0 = 1 in order to enable the n-wire interface and allow debugger access to the on-chip debug unit. during and after poc reset (ocdm.ocdm0 = 0) pins p05, p52?p55 are configured as input ports. table 29-2 n-wire interface pins gpio n-wire function pin direction description p05 drst input n-wire rcu reset p52 ddi input n-wire debug data in p53 ddo output n-wire debug data out p54 dck input n-wire interface clock p55 dms input n-wire mode 76543210 bit name 0000000ocdm0 reset value00000000/1 a a) reset value depends on reset source (see below) ocdm0 usage of n-wire pins 0 pins used as port/alternative function pins 1 pins used as n-wire interface pins
975 on-chip debug unit chapter 29 user?s manual u17566ee5v1um00 (3) external reset external reset by the reset pin sets ocdm.ocdm0 = 1, i.e. the pins are defined as n-wire interface pins. if connected the debugger can communicate with the on-chip debug unit and take over cpu control. during and after reset the pins p05, p52?p55 are configured as follows: ?drst , ddi, dck, dms are inputs. ? ddo is output, but in high impedance state as long as drst =0. (4) other resets resets from all other reset sources do not affect the pins p05, p52...p55. an internal pull-down resistor is provided for the pin p05/drst . during and after any reset the resistor is connected to p05/drst , ensuring that the n-wire interface is kept in reset state, if no debugger is connected. the internal pull-down resistor is connected by reset from any source and can be disconnected via the port configuration register bit pfc0.pdc05. the drst signal depicts the n-wire interface reset signal. if drst = 0 the on-chip debug unit is kept in reset state and does not impact normal controller operation. drst is driven by the debugger, if one is connected. the debugger may start communication with the controller by setting drst =1. caution if no external reset signal is available, the user software must activate the n-wire interface pins by setting ocmd.ocdm0 = 1. otherwise debugging via n-wire is not possible. pin configuration ? in n-wire debug mode the configuration of the n-wire interface pins can not be changed by the pin configuration registers. the registers contents can be changed but will have no effect on the pin configuration. ? in n-wire debug mode the output current limiting function of the ddo pin is disabled. by this means the port pin provides maximum driver capability in order to maximize the transmission data rate to the n-wire debugger. note that the settings of the port registers are not affected. note this chapter describes the n-wire interface control only. an additional security function decides, if the debugger access to the microcontroller is granted or not. please refer to ?code protection and security? on page 393 .
976 chapter 29 on-chip debug unit user?s manual u17566ee5v1um00 29.3 n-wire enabling methods 29.3.1 starting normal operation after reset and respoc for ?normal operation? it has to be assured that the pins p05, p52?p55 are available as port pins after either reset event. therefore the software has to perform ocdm.ocdm0 = 0 to make the pins available as port pins after reset . note that after any external reset via the reset pin ocdm.ocdm0 is set to "1" and the pins p05, p52?p55 are not available as application function pins until the software sets ocdm.ocdm0 = 0. figure 29-1 start without n-wire activation 29.3.2 starting debugger after reset and respoc the software has to set ocdm.ocdm0 = 1 for enabling the n-wire interface also upon a respoc event. afterwards the debugger may start to establish communication with the controller by setting the drst pin to high level and to take control over the cpu. on start of the debugger the entire controller is reset, i.e. all registers are set to their default states and the cpu's program counter is set to the reset vector 0000 0000 h respectively to the variable reset vector. note after respoc the controller is operating without debugger control. thus all cpu instructions until the software performs ocdm.ocdm0 = 1 can not be debugged. to restart the user?s program from beginning under the debugger?s control apply an external reset after the debugger has started, as shown in figure 29-2 . this will cause the program to restart. however the status of the controller might not be the same as immediately after respoc, since the internal ram may have already been initialized, when the external reset is applied. reset xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx respoc ocdm0 p05/drst reset normal operation reset normal operation ?0? ?1? application software sets ocdm.ocdm0=0
977 on-chip debug unit chapter 29 user?s manual u17566ee5v1um00 figure 29-2 start with n-wire activation 29.3.3 n-wire activation by reset pin the n-wire interface can also be activated after power up by keeping reset active for at least 2 sec after respoc release. by this ocdm.ocdm0 is set to "1", thus the n-wire interface is enabled. with this method the user's program does not need to perform ocdm.ocdm0 = 1. figure 29-3 n-wire activation by reset pin normal operation debug reset application software sets ocdm.ocdm0=1 debugger starts pc = 0 xxxxxxxxxxxxxx respoc ocdm0 p05/drst reset ?0? ?1? >= 2000ms ?0? ?1? reset debug normal operation reset respoc ocdm0 p05/drst xxxxxxxxx debugger starts pc = 0
978 chapter 29 on-chip debug unit user?s manual u17566ee5v1um00 29.4 connection to n-wire emulator to connect the n-wire emulator, a connector for emulator connection and a connection circuit must be mounted on the target system. as a connector example the kel connector is described in more detail. other connectors, like for instance mictor connector (product name: 2-767004-2, tyco electronics amp k.k.), are available as well. for the mechanical and electrical specification of these connectors refer to user?s manual of the emulator to be used. 29.4.1 kel connector kel connector product names: ? 8830e-026-170s (kel): straight type ? 8830e-026-170l (kel): right-angle type figure 29-4 connection to n-wire emulator (nec electronics ie-v850e1-cd-nw: n-wire card)
979 on-chip debug unit chapter 29 user?s manual u17566ee5v1um00 (1) pin configuration figure 29-5 shows the pin configuration of the connector for emulator connection (target system side), and table 29-3 on page 980 shows the pin functions. figure 29-5 pin configuration of connector for emulator connection (target system side) caution evaluate the dimensions of the connector when actually mounting the connector on the target board.
980 chapter 29 on-chip debug unit user?s manual u17566ee5v1um00 (2) pin functions the following table shows the pin functions of the connector for emulator connection (target system side). ?i/o? indicates the direction viewed from the device. caution 1. the connection of the pins not supported by the microcontroller is dependent upon the emulator to be used. 2. the pattern of the target board must satisfy the following conditions. ? the pattern length must be 100 mm or less. ? the clock signal must be shielded by gnd. table 29-3 pin functions of connector for emulator connection (target system side) pin no. pin name i/o pin function a1 (reserved 1) ? (connect to gnd) a2 (reserved 2) ? (connect to gnd) a3 (reserved 3) ? (connect to gnd) a4 (reserved 4) ? (connect to gnd) a5 (reserved 5) ? (connect to gnd) a6 (reserved 6) ? (connect to gnd) a7 ddi input data input for n-wire interface a8 dck input clock input for n-wire interface a9 dms input transfer mode select input for n-wire interface a10 ddo output data output for n-wire interface a11 drst input on-chip debug unit reset input a12 reset input reset input. (in a system that uses only poc reset and not pin reset, some emulators input an external reset signal as shown in figure 29-6 on page 981 to set the ocdm0 bit to 1.) a13 flmd0 a a) the flmd0 signal is not required, if the n-wire debugger serves the flmd0 signal internally by using the selfen register to enable flash self-programming (refer to ?flash self-programming? on page 275 ). howev- er the flmd0 signal may be connected. input control signal for flash download (flash memory versions only) b1 gnd ? ? b2 gnd ? ? b3 gnd ? ? b4 gnd ? ? b5 gnd ? ? b6 gnd ? ? b7 gnd ? ? b8 gnd ? ? b9 gnd ? ? b10 gnd ? ? b11 (reserved 8) ? (connect to gnd) b12 (reserved 9) ? (connect to gnd) b13 v dd ? 5 v input (for monitoring power supply to target)
981 on-chip debug unit chapter 29 user?s manual u17566ee5v1um00 (3) example of recommended circuit an example of the recommended circuit of the connector for emulator connection (target system side) is shown below. figure 29-6 example of recommended emulator connection circuit note 1. the pattern length must be 100 mm or less. 2. shield the dck signal by enclosing it with gnd. 3. this pin is used to detect power to the target board. connect the voltage of the n-wire interface to this pin. 4. in a system that uses only poc reset and not pin reset, some emulators input an external reset signal as shown in figure 29-6 to set the ocdm.ocdm0 bit to 1. 5. the flmd0 signal is not required, but may be connected. caution the n-wire emulator may not support a 5 v interface and may require a level shifter. refer to the user?s manual of the emulator to be used. v850e/dx3 flmd0 (reserved 1) (reserved 2) (reserved 3) (reserved 4) (reserved 5) (reserved 6) ddi dck dms ddo drst flmd0 reset v dd note 3 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd (reserved 8) (reserved 9) note 2 note 1 note 1 note 1 notes 1, 5 note 4 5 v 5 v a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a13 a12 b13 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 ddi dck dms ddo drst kel connector 8830e-026-170s reset note 1
982 chapter 29 on-chip debug unit user?s manual u17566ee5v1um00 29.5 restrictions and cautions on on-chip debug function ? do not mount a device that was used for debugging on a mass-produced product (this is because the flash memory was rewritten during debugging and the number of rewrites of the flash memory cannot be guaranteed). ? if a reset signal (reset input from the target system or reset by an internal reset source) is input during run (program execution), the break function may malfunction. ? even if reset is masked by using a mask function, the i/o buffer (port pin, etc.) is reset when a pin reset signal is input. ? with a debugger that can set software breakpoints in the internal flash memory, the breakpoints temporarily become invalid when pin reset or internal reset is effected. the breakpoints become valid again if a break such as a hardware break or forced break is executed. until then, no software break occurs. ?the reset signal input is masked during a break. ? the poc reset operation cannot be emulated. ? the on-chip debugging unit uses the exception vector address 60 h for software breakpoint (dbtrap, refer to ?interrupt controller (intc)? on page 201 ). thus the debugger takes over control when one of the following exceptions occur: ? debug trap (dbtrap) ? illegal opcode detection (ilgop) ? rom correction the debugger executes its own exception handler. therefore, the user's exception handler at address 60 h will not be executed. ? the maximum input clock dck of the n-wire debugger interface is limited to 10 mhz. thus on-chip debugging is not possible in case that the input clock dck is set to above 10 mhz. implement all of the following measures: ? while debugging with any n-wire based emulator, limit the maximum input clock of dck to 10 mhz. ? consult the latest tool documentation in order to verify that no on-chip debugger option is configured in your environment that will configure a higher dck input clock than 10 mhz. ? set the following environment variable: ie850_jcndreginit = 320 special hint for 850eserv: above mentioned configuration can be achieved by setting the on-chip debugger emulator option: ?-2m?. never set the on-chip debugger emulator option ?-dck20?, since it would configure a dck input clock of 20 mhz. ? execution stop of firmware at user breakpoint if during program execution a reset occurs (either from any internal reset source or from the external reset pin), the on-chip debugger may stop at the address of a previously configured s/w or h/w breakpoint during the execution of the firmware start-up code. in this case, the following error message may be output: "couldn?t read flash memory at xxx 0xc25 user system error (mask rom >area)"
983 on-chip debug unit chapter 29 user?s manual u17566ee5v1um00 to avoid this situation do not set any kind of breakpoint (neither s/w nor h/ w breakpoint) within any of the following address ranges: ?0000 h to 000f h ?06d0 h to 2b23 h special hint: reserve the address range 06d0 h to 2b23 h for constant data placement. in case using nec?s directive files, which are part of the device file package, this is the default assignment. if the program requires less constant data than that address space offers, modify the linker directive file in a way, that program code does not start before the address 2b24 h .
984 chapter 29 on-chip debug unit user?s manual u17566ee5v1um00
985 user?s manual u17566ee5v1um00 appendix a registers access times this chapter provides formulas to calculate the access time to registers, which are accessed via the peripheral i/o areas. all accesses to the peripheral i/o areas are passed over to the npb bus via the vsb - npb bus bridge bbr. read and write access times to registers via the npb depend on the register, the system clock vbclk and the setting of the vswc register. the cpu operation during an access to a register via the npb depends also on the kind of peripheral i/o area: ? fixed peripheral i/o area during a read or write access the cpu operation stops until the access via the npb is completed. ? programmable peripheral i/o area during a read access the cpu operation stops until the read access via the npb is completed. during a write access the cpu operation continues operation, provided any preceded npb access is already finished. if a preceded npb access is still ongoing the cpu stops until this access is finished and the npb is cleared. the following formulas are given to calculate the access times t a , when the cpu reads from or writes to special function registers via the npb bus. the access time depends ? on the cpu system clock frequency f vbclk ? on the setting of the internal peripheral function wait control register vswc, which determines the address set up wait suwl = vswc.suwl and data wait vswl = vswc.vswl (refer to ?vswc - internal peripheral function wait control register? on page 303 for the correct values for a certain cpu system clock vbclk) ? for some registers on the clock frequency applied to the module note ?ru[...]? in the formulas mean ?round up? the calculated value of the term in squared brackets. all formulas calculate the maximum access time. cpu access for calculating the access times for cpu accesses 1 vblck period time 1/ f vbclk has to be added to the results of the formulas. dma access for accesses of the dma controller the given formulas calculate the exact values.
986 appendix a registers access times user?s manual u17566ee5v1um00 a.1 timer p register tpnccr0, tpnccr1 access r formula access w formula register tpncnt access r formula access w formula register all other access r/w (no write access during timer operation) formula t a suwl vswl 3 ru f vbclk 2vswl + () f pclk0  --------------------------------------------------------- - 1 + 2vswl + ()  +++    1 f vbclk ------------------  = t a suwl vswl 3 ru 5f vbclk  2vswl + () f pclk0  --------------------------------------------------------- - 1 + 2vswl + ()  +++    1 f vbclk ------------------  = t a suwl vswl 3 ru f vbclk 2vswl + () f pclk0  --------------------------------------------------------- - 1 + 2vswl + ()  +++    1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  =
987 registers access times appendix a user?s manual u17566ee5v1um00 a.2 timer z register tzncnt0 access r formula register tzncnt1 access r formula register tznr access r formula access w formula register tznctl access r/w formula t a suwl 3 vswl  6 ++ () 1 f vbclk ------------------  4 5 , f pclk2 ----------------- - + = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl 3 vswl  6 ++ () 1 f vbclk ------------------  45 , f pclk2 ----------------- - + = t a suwl vswl 3 ++ () 1 f vbclk ------------------  =
988 appendix a registers access times user?s manual u17566ee5v1um00 a.3 timer y register tyncnt0 access r formula register tyncnt1 access r formula register tynr access r formula access w formula register tynctl access r/w formula t a suwl 3 vswl  6 ++ () 1 f vbclk ------------------  1 f spclk1 --------------------- + = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl 3 vswl  6 ++ () 1 f vbclk ------------------  1 f spclk1 --------------------- + = t a suwl vswl 3 ++ () 1 f vbclk ------------------  =
989 registers access times appendix a user?s manual u17566ee5v1um00 a.4 timer g register tmgn0, tmgn1 access r formula access w (no write access during timer operation) formula register gccn[5:0] access r formula access w (for gccn0 and gccn5 no write access during timer operation) formula ? for multiple write within 7 spclk0 periods ? for single write within 7 spclk0 periods register all other access r/w (no write access during timer operation) formula t a suwl vswl 3 ru f vbclk 2vswl + () f spclk0  ------------------------------------------------------------- 1 + 2vswl + ()  +++    1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ru f vbclk 2vswl + () f spclk0  ------------------------------------------------------------- 1 + 2vswl + ()  +++    1 f vbclk ------------------  = t a suwl vswl 3 ru f vbclk 2vswl + () f spclk0  ------------------------------------------------------------- 1 + 2vswl + ()  +++    1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  =
990 appendix a registers access times user?s manual u17566ee5v1um00 a.5 watch timer register wtncnt1 access r formula register wtnr access r formula access w formula register cr00 access read-modify-write formula register all other access r/w formula a.6 watch calibration timer register cr01 access r/w formula access read-modify-write formula register all other access r/w formula t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl 3 vswl  7 ++ () 1 f vbclk ------------------  = t a suwl 3 vswl  7 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl 3 vswl  7 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  =
991 registers access times appendix a user?s manual u17566ee5v1um00 a.7 watchdog timer register all access r/w formula a.8 asynchronous serial interface (uarta) register all access r/w formula a.9 clocked serial interface (csib) register all access r/w formula a.10 i 2 c bus register iicsn access r formula register all other access r/w formula t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl 3 vswl  7 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  =
992 appendix a registers access times user?s manual u17566ee5v1um00 a.11 can controller register cnmdata[7:0]m access r formula access 8-bit write formula access 16-bit write formula register cnrgpt, cntgpt, cnlipt, cnlopt access r formula register all other access r/w formula t a suwl vswl 3 ru 4 f vbclk f canmod ----------------------- - 1 + 2vswl + --------------------------------- -  2vswl + ()  +++      1 f vbclk ------------------  = t a suwl vswl 3 ru 5 f vbclk f canmod ----------------------- - 1 + 2vswl + --------------------------------- -  2vswl + ()  +++      1 f vbclk ------------------  = t a suwl vswl 3 ru 3 f vbclk f canmod ----------------------- - 1 + 2vswl + --------------------------------- -  2vswl + ()  +++      1 f vbclk ------------------  = t a suwl vswl 3 ru 4 f vbclk f canmod ----------------------- - 1 + 2vswl + --------------------------------- -  2vswl + ()  +++      1 f vbclk ------------------  = t a suwl vswl 3 ru 2 f vbclk f canmod ----------------------- - 1 + 2vswl + --------------------------------- -  2vswl + ()  +++      1 f vbclk ------------------  =
993 registers access times appendix a user?s manual u17566ee5v1um00 a.12 a/d converter register adam0[2:0], adacr0n access r formula access w formula register all other access r/w formula a.13 stepper motor controller/driver register mcntcn[1:0], mcmpcnk access r formula access w formula register all other access r/w formula a.14 lcd controller/driver register all access r/w formula t a suwl vswl 3 ru 2f vbclk  2vswl + () f spclk0  ------------------------------------------------------------- 1 + 2vswl + ()  +++    1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ru 2f vbclk  2vswl + () f spclk1  ------------------------------------------------------------- 1 + 2vswl + ()  +++    1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  =
994 appendix a registers access times user?s manual u17566ee5v1um00 a.15 lcd bus interface register all access r/w formula t a suwl vswl 3 ++ () 1 f vbclk ------------------  =
995 registers access times appendix a user?s manual u17566ee5v1um00 a.16 sound generator register sg0fl, sg0fh, sg0pwm access r formula access w formula register all other access r/w formula a.17 clock generator register cgstat access r formula access w formula register all other access r/w formula a.18 all other registers register all access r/w formula t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl 3 vswl  6 ++ () 1 f vbclk ------------------ 2 f pclk0 ----------------- - +  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl 3 vswl  7 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  = t a suwl vswl 3 ++ () 1 f vbclk ------------------  =
996 appendix a registers access times user?s manual u17566ee5v1um00
997 user?s manual u17566ee5v1um00 appendix b special function registers the following tables list all registers that are accessed via the npb (nec peripheral bus). the registers are called ?special function registers? (sfr). ta b l e b - 1 lists all can special function registers. the addresses are given as offsets to programmable peripheral base address (refer to ?can module register and message buffer addresses? on page 745 . the tables list all registers and do not distinguish between the different derivatives. b.1 can registers the can registers are accessible via the programmable peripheral area. table b-1 can special function registers (1/4) address offset register name shortcut 1 8 16 32 initial value 0x000 can0 global macro control register c0gmctrl --r/w- 0x0000 0x000 can0 global macro control register low byte c0gmctrll r/w r/w - - 0x00 0x001 can0 global macro control register high byte c0gmctrlh r/w r/w - - 0x00 0x002 can0 global macro clock selection register c0gmcs r/w r/w - - 0x0f 0x006 can0 global macro automatic block transmission register c0gmabt --r/w- 0x0000 0x006 can0 global macro automatic block transmission register low byte c0gmabtl r/w r/w - - 0x00 0x007 can0 global macro automatic block transmission register high byte c0gmabth r/w r/w - - 0x00 0x008 can0 global macro automatic block transmission delay register c0gmabtd r/w r/w - - 0x00 0x040 can0 module mask 1 register lower half word c0mask1l --r/w- undefined 0x042 can0 module mask 1 register upper half word c0mask1h --r/w- undefined 0x044 can0 module mask 2 register lower half word c0mask2l --r/w- undefined 0x046 can0 module mask 2 register upper half word c0mask2h --r/w- undefined 0x048 can0 module mask 3 register lower half word c0mask3l --r/w- undefined 0x04a can0 module mask 3 register upper half word c0mask3h --r/w- undefined 0x04c can0 module mask 4 register lower half word c0mask4l --r/w- undefined 0x04e can0 module mask 4 register upper half word c0mask4h --r/w- undefined 0x050 can0 module control register c0ctrl --r/w- 0x0000 0x052 can0 module last error code register c0lec r/w r/w - - 0x00 0x053 can0 module information register c0info rr - - 0x00 0x054 can0 module error counter c0erc --r/w- 0x0000 0x056 can0 module interrupt enable register c0ie --r/w- 0x0000
998 appendix b special function registers user?s manual u17566ee5v1um00 0x056 can0 module interrupt enable register low byte c0iel r/w r/w - - 0x00 0x057 can0 module interrupt enable register high byte c0ieh r/w r/w - - 0x00 0x058 can0 module interrupt status register c0ints --r/w- 0x0000 0x058 can0 module interrupt status register low byte c0intsl r/w r/w - - 0x00 0x05a can0 module bit-rate prescaler register c0brp r/w r/w - - 0xff 0x05c can0 bit rate register c0btr --r/w- 0x370f 0x05e can0 module last in-pointer register c0lipt -r/w- - undefined 0x060 can0 module receive history list get pointer register c0rgpt --r/w- 0x??02 (undefined) 0x060 can0 module receive history list get pointer register low byte c0rgptl r/w r/w - - 0x02 0x062 can0 module last out-pointer register c0lopt -r- - undefined 0x064 can0 module transmit history list get pointer register c0tgpt --r/w- 0x??02 (undefined) 0x064 can0 module transmit history list get pointer register low byte c0tgptl r/w r/w - - 0x02 0x066 can0 module time stamp register c0ts --r/w- 0x0000 0x066 can0 module time stamp register low byte c0tsl r/w r/w - - 0x00 0x067 can0 module time stamp register high byte c0tsh r/w r/w - - 0x00 0x100 to 0x4ef can0 message buffer registers, see table 20-20 on page 748 . 0x600 can1 global macro control register c1gmctrl --r/w- 0x0000 0x600 can1 global macro control register low byte c1gmctrll r/w r/w - - 0x00 0x601 can1 global macro control register high byte c1gmctrlh r/w r/w - - 0x00 0x602 can1 global macro clock selection register c1gmcs r/w r/w - - 0x0f 0x606 can1 global macro automatic block transmission register c1gmabt --r/w- 0x0000 0x606 can1 global macro automatic block transmission register low byte c1gmabtl r/w r/w - - 0x00 0x607 can1 global macro automatic block transmission register high byte c1gmabth r/w r/w - - 0x00 0x608 can1 global macro automatic block transmission delay register c1gmabtd r/w r/w - - 0x00 0x640 can1 module mask 1 register lower half word c1mask1l --r/w- undefined 0x642 can1 module mask 1 register upper half word c1mask1h --r/w- undefined 0x644 can1 module mask 2 register lower half word c1mask2l --r/w- undefined 0x646 can1 module mask 2 register upper half word c1mask2h --r/w- undefined 0x648 can1 module mask 3 register lower half word c1mask3l --r/w- undefined 0x64a can1 module mask 3 register upper half word c1mask3h --r/w- undefined 0x64c can1 module mask 4 register lower half word c1mask4l --r/w- undefined 0x64e can1 module mask 4 register upper half word c1mask4h --r/w- undefined 0x650 can1 module control register c1ctrl --r/w- 0x0000 0x652 can1 module last error code register c1lec r/w r/w - - 0x00 0x653 can1 module information register c1info rr - - 0x00 table b-1 can special function registers (2/4) address offset register name shortcut 1 8 16 32 initial value
999 special function registers appendix b user?s manual u17566ee5v1um00 0x654 can1 module error counter c1erc --r/w- 0x0000 0x656 can1 module interrupt enable register c1ie --r/w- 0x0000 0x656 can1 module interrupt enable register low byte c1iel r/w r/w - - 0x00 0x657 can1 module interrupt enable register high byte c1ieh r/w r/w - - 0x00 0x658 can1 module interrupt status register c1ints --r/w- 0x0000 0x658 can1 module interrupt status register low byte c1intsl r/w r/w - - 0x00 0x65a can1 module bit-rate prescaler register c1brp r/w r/w - - 0xff 0x65c can1 bit rate register c1btr --r/w- 0x370f 0x65e can1 module last in-pointer register c1lipt -r/w- - undefined 0x660 can1 module receive history list get pointer register c1rgpt --r/w- 0x??02 (undefined) 0x660 can1 module receive history list get pointer register low byte c1rgptl r/w r/w - - 0x02 0x662 can1 module last out-pointer register c1lopt -r- - undefined 0x664 can1 module transmit history list get pointer register c1tgpt --r/w- 0x??02 (undefined) 0x664 can1 module transmit history list get pointer register low byte c1tgptl r/w r/w - - 0x02 0x666 can1 module time stamp register c1ts --r/w- 0x0000 0x666 can1 module time stamp register low byte c1tsl r/w r/w - - 0x00 0x667 can1 module time stamp register high byte c1tsh r/w r/w - - 0x00 0x700 to 0xaef can1 message buffer registers, see table 20-20 on page 748 . 0xc00 can2 global macro control register c2gmctrl --r/w- 0x0000 0xc00 can2 global macro control register low byte c2gmctrll r/w r/w - - 0x00 0xc01 can2 global macro control register high byte c2gmctrlh r/w r/w - - 0x00 0xc02 can2 global macro clock selection register c2gmcs r/w r/w - - 0x0f 0xc06 can2 global macro automatic block transmission register c2gmabt --r/w- 0x0000 0xc06 can2 global macro automatic block transmission register low byte c2gmabtl r/w r/w - - 0x00 0xc07 can2 global macro automatic block transmission register high byte c2gmabth r/w r/w - - 0x00 0xc08 can2 global macro automatic block transmission delay register c2gmabtd r/w r/w - - 0x00 0xc40 can2 module mask 1 register lower half word c2mask1l --r/w- undefined 0xc42 can2 module mask 1 register upper half word c2mask1h --r/w- undefined 0xc44 can2 module mask 2 register lower half word c2mask2l --r/w- undefined 0xc46 can2 module mask 2 register upper half word c2mask2h --r/w- undefined 0xc48 can2 module mask 3 register lower half word c2mask3l --r/w- undefined 0xc4a can2 module mask 3 register upper half word c2mask3h --r/w- undefined 0xc4c can2 module mask 4 register lower half word c2mask4l --r/w- undefined 0xc4e can2 module mask 4 register upper half word c2mask4h --r/w- undefined 0xc50 can2 module control register c2ctrl --r/w- 0x0000 table b-1 can special function registers (3/4) address offset register name shortcut 1 8 16 32 initial value
1000 appendix b special function registers user?s manual u17566ee5v1um00 0xc52 can2 module last error code register c2lec r/w r/w - - 0x00 0xc53 can2 module information register c2info rr - - 0x00 0xc54 can2 module error counter c2erc --r/w- 0x0000 0xc56 can2 module interrupt enable register c2ie --r/w- 0x0000 0xc56 can2 module interrupt enable register low byte c2iel r/w r/w - - 0x00 0xc57 can2 module interrupt enable register high byte c2ieh r/w r/w - - 0x00 0xc58 can2 module interrupt status register c2ints --r/w- 0x0000 0xc58 can2 module interrupt status register low byte c2intsl r/w r/w - - 0x00 0xc5a can2 module bit-rate prescaler register c2brp r/w r/w - - 0xff 0xc5c can2 bit rate register c2btr --r/w- 0x370f 0xc5e can2 module last in-pointer register c2lipt -r/w- - undefined 0xc60 can2 module receive history list get pointer register c2rgpt --r/w- 0x??02 (undefined) 0xc60 can2 module receive history list get pointer register low byte c2rgptl r/w r/w - - 0x02 0xc62 can2 module last out-pointer register c2lopt -r- - undefined 0xc64 can2 module transmit history list get pointer register c2tgpt --r/w- 0x??02 (undefined) 0xc64 can2 module transmit history list get pointer register low byte c2tgptl r/w r/w - - 0x02 0xc66 can2 module time stamp register c2ts --r/w- 0x0000 0xc66 can2 module time stamp register low byte c2tsl r/w r/w - - 0x00 0xc67 can2 module time stamp register high byte c2tsh r/w r/w - - 0x00 0xd00 to 0x10ef can2 message buffer registers, see table 20-20 on page 748 table b-1 can special function registers (4/4) address offset register name shortcut 1 8 16 32 initial value
1001 special function registers appendix b user?s manual u17566ee5v1um00 b.2 other special function registers table b-2 other special function registers (1/20) address register name shortcut 1 8 16 32 initial value 0xfffff060 cpu: chip area select control register 0 csc0 --r/w- 0x2c11 0xfffff062 cpu: chip area select control register 1 csc1 --r/w- 0x2c11 0xfffff064 cpu: peripheral area select control register bpc --r/w- 0x0000 0xfffff068 cpu: endian configuration register bec --r/w- 0x0000 0xfffff06e cpu: vpb strobe wait control register vswc r/w r/w - - 0x77 0xfffff080 dma source address register 0l dsal0 --r/w- undefined 0xfffff082 dma source address register 0h dsah0 --r/w- undefined 0xfffff084 dma destination address register 0l ddal0 --r/w- undefined 0xfffff086 dma destination address register 0h ddah0 --r/w- undefined 0xfffff088 dma source address register 1l dsal1 --r/w- undefined 0xfffff08a dma source address register 1h dsah1 --r/w- undefined 0xfffff08c dma destination address register 1l ddal1 --r/w- undefined 0xfffff08e dma destination address register 1h ddah1 --r/w- undefined 0xfffff090 dma source address register 2l dsal2 --r/w- undefined 0xfffff092 dma source address register 2h dsah2 --r/w- undefined 0xfffff094 dma destination address register 2l ddal2 --r/w- undefined 0xfffff096 dma destination address register 2h ddah2 --r/w- undefined 0xfffff098 dma source address register 3l dsal3 --r/w- undefined 0xfffff09a dma source address register 3h dsah3 --r/w- undefined 0xfffff09c dma destination address register 3l ddal3 --r/w- undefined 0xfffff09e dma destination address register 3h ddah3 --r/w- undefined 0xfffff0c0 dma transfer count register 0 dbc0 --r/w- undefined 0xfffff0c2 dma transfer count register 1 dbc1 --r/w- undefined 0xfffff0c4 dma transfer count register 2 dbc2 --r/w- undefined 0xfffff0c6 dma transfer count register 3 dbc3 --r/w- undefined 0xfffff0d0 dma addressing control register 0 dadc0 --r/w- 0x0000 0xfffff0d2 dma addressing control register 1 dadc1 --r/w- 0x0000 0xfffff0d4 dma addressing control register 2 dadc2 --r/w- 0x0000 0xfffff0d6 dma addressing control register 3 dadc3 --r/w- 0x0000 0xfffff0e0 dma channel control register 0 dchc0 r/w r/w - - 0x00 0xfffff0e2 dma channel control register 1 dchc1 r/w r/w - - 0x00 0xfffff0e4 dma channel control register 2 dchc2 r/w r/w - - 0x00 0xfffff0e6 dma channel control register 3 dchc3 r/w r/w - - 0x00 0xfffff0f2 dma restart register drst r/w r/w - - 0x00 0xfffff100 interrupt mask register 0 imr0 --r/w- 0xffff 0xfffff100 interrupt mask register 0l imr0l r/w r/w - - 0xff 0xfffff101 interrupt mask register 0h imr0h r/w r/w - - 0xff 0xfffff102 interrupt mask register 1 imr1 --r/w- 0xffff 0xfffff102 interrupt mask register 1l imr1l r/w r/w - - 0xff
1002 appendix b special function registers user?s manual u17566ee5v1um00 0xfffff103 interrupt mask register 1h imr1h r/w r/w - - 0xff 0xfffff104 interrupt mask register 2 imr2 --r/w- 0xffff 0xfffff104 interrupt mask register 2l imr2l r/w r/w - - 0xff 0xfffff105 interrupt mask register 2h imr2h r/w r/w - - 0xff 0xfffff106 interrupt mask register 3 imr3 --r/w- 0xffff 0xfffff106 interrupt mask register 3l imr3l r/w r/w - - 0xff 0xfffff107 interrupt mask register 3h imr3h r/w r/w - - 0xff 0xfffff108 interrupt mask register 4 imr4 --r/w- 0xffff 0xfffff108 interrupt mask register 4l imr4l r/w r/w - - 0xff 0xfffff109 interrupt mask register 4h imr4h r/w r/w - - 0xff 0xfffff10a interrupt mask register 5 imr5 --r/w- 0xffff 0xfffff10a interrupt mask register 5l imr5l r/w r/w - - 0xff 0xfffff10b interrupt mask register 5h imr5h r/w r/w - - 0xff 0xfffff10c interrupt mask register 6 imr6 --r/w- 0xffff 0xfffff10c interrupt mask register 6l imr6h r/w r/w - - 0xff 0xfffff10d interrupt mask register 6h imr6l r/w r/w - - 0xff 0xfffff110 interrupt control register of intvc0 vc0ic r/w r/w - - 0x47 0xfffff112 interrupt control register of intvc1 vc1ic r/w r/w - - 0x47 0xfffff114 interrupt control register of intwt0uv wt0uvic r/w r/w - - 0x47 0xfffff116 interrupt control register of intwt1uv wt1uvic r/w r/w - - 0x47 0xfffff11a interrupt control register of inttm01 tm01ic r/w r/w - - 0x47 0xfffff11c interrupt control register of intp0 p0ic r/w r/w - - 0x47 0xfffff11e interrupt control register of intp1 p1ic r/w r/w - - 0x47 0xfffff120 interrupt control register of intp2 p2ic r/w r/w - - 0x47 0xfffff122 interrupt control register of intp3 p3ic r/w r/w - - 0x47 0xfffff124 interrupt control register of intp4 p4ic r/w r/w - - 0x47 0xfffff126 interrupt control register of intp5 p5ic r/w r/w - - 0x47 0xfffff128 interrupt control register of intp6 p6ic r/w r/w - - 0x47 0xfffff12a interrupt control register of inttz0uv tz0uvic r/w r/w - - 0x47 0xfffff12c interrupt control register of inttz1uv tz1uvic r/w r/w - - 0x47 0xfffff12e interrupt control register of inttz2uv tz2uvic r/w r/w - - 0x47 0xfffff130 interrupt control register of inttz3uv tz3uvic r/w r/w - - 0x47 0xfffff132 interrupt control register of inttz4uv tz4uvic r/w r/w - - 0x47 0xfffff134 interrupt control register of inttz5uv tz5uvic r/w r/w - - 0x47 0xfffff136 interrupt control register of inttp0ov tp0ovic r/w r/w - - 0x47 0xfffff138 interrupt control register of inttp0cc0 tp0cc0ic r/w r/w - - 0x47 0xfffff13a interrupt control register of inttp0cc1 tp0cc1ic r/w r/w - - 0x47 0xfffff13c interrupt control register of inttp1ov tp1ovic r/w r/w - - 0x47 0xfffff13e interrupt control register of inttp1cc0 tp1cc0ic r/w r/w - - 0x47 0xfffff140 interrupt control register of inttp1cc1 tp1cc1ic r/w r/w - - 0x47 0xfffff142 interrupt control register of inttp2ov tp2ovic r/w r/w - - 0x47 table b-2 other special function registers (2/20) address register name shortcut 1 8 16 32 initial value
1003 special function registers appendix b user?s manual u17566ee5v1um00 0xfffff144 interrupt control register of inttp2cc0 tp2cc0ic r/w r/w - - 0x47 0xfffff146 interrupt control register of inttp2cc1 tp2cc1ic r/w r/w - - 0x47 0xfffff148 interrupt control register of inttp3ov tp3ovic r/w r/w - - 0x47 0xfffff14a interrupt control register of inttp3cc0 tp3cc0ic r/w r/w - - 0x47 0xfffff14c interrupt control register of inttp3cc1 tp3cc1ic r/w r/w - - 0x47 0xfffff14e interrupt control register of inttg0ov0 tg0ov0ic r/w r/w - - 0x47 0xfffff150 interrupt control register of inttg0ov1 tg0ov1ic r/w r/w - - 0x47 0xfffff152 interrupt control register of inttg0cc0 tg0cc0ic r/w r/w - - 0x47 0xfffff154 interrupt control register of inttg0cc1 tg0cc1ic r/w r/w - - 0x47 0xfffff156 interrupt control register of inttg0cc2 tg0cc2ic r/w r/w - - 0x47 0xfffff158 interrupt control register of inttg0cc3 tg0cc3ic r/w r/w - - 0x47 0xfffff15a interrupt control register of inttg0cc4 tg0cc4ic r/w r/w - - 0x47 0xfffff15c interrupt control register of inttg0cc5 tg0cc5ic r/w r/w - - 0x47 0xfffff15e interrupt control register of inttg1ov0 tg1ov0ic r/w r/w - - 0x47 0xfffff160 interrupt control register of inttg1ov1 tg1ov1ic r/w r/w - - 0x47 0xfffff162 interrupt control register of inttg1cc0 tg1cc0ic r/w r/w - - 0x47 0xfffff164 interrupt control register of inttg1cc1 tg1cc1ic r/w r/w - - 0x47 0xfffff166 interrupt control register of inttg1cc2 tg1cc2ic r/w r/w - - 0x47 0xfffff168 interrupt control register of inttg1cc3 tg1cc3ic r/w r/w - - 0x47 0xfffff16a interrupt control register of inttg1cc4 tg1cc4ic r/w r/w - - 0x47 0xfffff16c interrupt control register of inttg1cc5 tg1cc5ic r/w r/w - - 0x47 0xfffff16e interrupt control register of intty0uv0 ty0uv0ic r/w r/w - - 0x47 0xfffff170 interrupt control register of intty0uv1 ty0uv1ic r/w r/w - - 0x47 0xfffff172 interrupt control register of intad adic r/w r/w - - 0x47 0xfffff174 interrupt control register of intc0err c0erric r/w r/w - - 0x47 0xfffff176 interrupt control register of intc0wup c0wupic r/w r/w - - 0x47 0xfffff178 interrupt control register of intc0rec c0recic r/w r/w - - 0x47 0xfffff17a interrupt control register of intc0trx c0trxic r/w r/w - - 0x47 0xfffff17c interrupt control register of intcb0re cb0reic r/w r/w - - 0x47 0xfffff17e interrupt control register of intcb0r cb0ric r/w r/w - - 0x47 0xfffff180 interrupt control register of intcb0t cb0tic r/w r/w - - 0x47 0xfffff182 interrupt control register of intua0re ua0reic r/w r/w - - 0x47 0xfffff184 interrupt control register of intua0r ua0ric r/w r/w - - 0x47 0xfffff186 interrupt control register of intua0t ua0tic r/w r/w - - 0x47 0xfffff188 interrupt control register of intua1re ua1reic r/w r/w - - 0x47 0xfffff18a interrupt control register of intua1r ua1ric r/w r/w - - 0x47 0xfffff18c interrupt control register of intua1t ua1tic r/w r/w - - 0x47 0xfffff18e interrupt control register of intiic0 iic0ic r/w r/w - - 0x47 0xfffff190 interrupt control register of intiic1 iic1ic r/w r/w - - 0x47 0xfffff192 interrupt control register of intsg0 sg0ic r/w r/w - - 0x47 0xfffff194 interrupt control register of intdma0 dma0ic r/w r/w - - 0x47 table b-2 other special function registers (3/20) address register name shortcut 1 8 16 32 initial value
1004 appendix b special function registers user?s manual u17566ee5v1um00 0xfffff196 interrupt control register of intdma1 dma1ic r/w r/w - - 0x47 0xfffff198 interrupt control register of intdma2 dma2ic r/w r/w - - 0x47 0xfffff19a interrupt control register of intdma3 dma3ic r/w r/w - - 0x47 0xfffff19c interrupt control register of intsw0 sw0ic r/w r/w - - 0x47 0xfffff19e interrupt control register of intsw1 sw11ic r/w r/w - - 0x47 0xfffff1a0 interrupt control register of intp7 p7ic r/w r/w - - 0x47 0xfffff1a2 interrupt control register of intc1err c1erric r/w r/w - - 0x47 0xfffff1a4 interrupt control register of intc1wup c1wupic r/w r/w - - 0x47 0xfffff1a6 interrupt control register of intc1rec c1recic r/w r/w - - 0x47 0xfffff1a8 interrupt control register of intc1trx c1trxic r/w r/w - - 0x47 0xfffff1aa interrupt control register of inttz6uv tz6uvic r/w r/w - - 0x47 0xfffff1ac interrupt control register of inttz7uv tz7uvic r/w r/w - - 0x47 0xfffff1ae interrupt control register of inttz8uv tz8uvic r/w r/w - - 0x47 0xfffff1b0 interrupt control register of inttz9uv tz9uvic r/w r/w - - 0x47 0xfffff1b2 interrupt control register of inttg2ov0 tg2ov0ic r/w r/w - - 0x47 0xfffff1b4 interrupt control register of inttg2ov1 tg2ov1ic r/w r/w - - 0x47 0xfffff1b6 interrupt control register of inttg2cc0 tg2cc0ic r/w r/w - - 0x47 0xfffff1b8 interrupt control register of inttg2cc1 tg2cc1ic r/w r/w - - 0x47 0xfffff1ba interrupt control register of inttg2cc2 tg2cc2ic r/w r/w - - 0x47 0xfffff1bc interrupt control register of inttg2cc3 tg2cc3ic r/w r/w - - 0x47 0xfffff1be interrupt control register of inttg2cc4 tg2cc4ic r/w r/w - - 0x47 0xfffff1c0 interrupt control register of inttg2cc5 tg2cc5ic r/w r/w - - 0x47 0xfffff1c2 interrupt control register of intcb1re cb1reic r/w r/w - - 0x47 0xfffff1c4 interrupt control register of intcb1r cb1ric r/w r/w - - 0x47 0xfffff1c6 interrupt control register of intcb1t cb1tic r/w r/w - - 0x47 0xfffff1c8 interrupt control register of intcb2re cb2reic r/w r/w - - 0x47 0xfffff1ca interrupt control register of intcb2r cb2ric r/w r/w - - 0x47 0xfffff1cc interrupt control register of intcb2t cb2tic r/w r/w - - 0x47 0xfffff1ce interrupt control register of intlcd lcdic r/w r/w - - 0x47 0xfffff1d0 interrupt control register of intc2err c2erric r/w r/w - - 0x47 0xfffff1d2 interrupt control register of intc2wup c2wupic r/w r/w - - 0x47 0xfffff1d4 interrupt control register of intc2rec c2recic r/w r/w - - 0x47 0xfffff1d6 interrupt control register of intc2trx c2trxic r/w r/w - - 0x47 0xfffff1fa in-service priority register ispr rr - - 0x00 0xfffff1fc command register prcmd -w- - undefined 0xfffff1fe power save control register psc r/w r/w - - 0x00 0xfffff200 adc mode register 0 ada0m0 r/w r/w - - 0x00 0xfffff201 adc mode register 1 ada0m1 r/w r/w - - 0x00 0xfffff202 adc channel select register ada0s r/w r/w - - 0x00 0xfffff203 adc mode register 2 ada0m2 r/w r/w - - 0x00 0xfffff204 adc power fail comparison mode register ada0pfm r/w r/w - - 0x00 table b-2 other special function registers (4/20) address register name shortcut 1 8 16 32 initial value
1005 special function registers appendix b user?s manual u17566ee5v1um00 0xfffff205 adc power fail threshold register ada0pft r/w r/w - - 0x00 0xfffff210 adc result register channel 0 adcr00 --r- undefined 0xfffff211 adc result register high byte channel 0 adcr0h0 rr - - undefined 0xfffff212 adc result register channel 1 adcr01 --r- undefined 0xfffff213 adc result register high byte channel 1 adcr0h1 rr - - undefined 0xfffff214 adc result register channel 2 adcr02 --r- undefined 0xfffff215 adc result register high byte channel 2 adcr0h2 rr - - undefined 0xfffff216 adc result register channel 3 adcr03 --r- undefined 0xfffff217 adc result register high byte channel 3 adcr0h3 rr - - undefined 0xfffff218 adc result register channel 4 adcr04 --r- undefined 0xfffff219 adc result register high byte channel 4 adcr0h4 rr - - undefined 0xfffff21a adc result register channel 5 adcr05 --r- undefined 0xfffff21b adc result register high byte channel 5 adcr0h5 rr - - undefined 0xfffff21c adc result register channel 6 adcr06 --r- undefined 0xfffff21d adc result register high byte channel 6 adcr0h6 rr - - undefined 0xfffff21e adc result register channel 7 adcr07 --r- undefined 0xfffff21f adc result register high byte channel 7 adcr0h7 rr - - undefined 0xfffff220 adc result register channel 8 adcr08 --r- undefined 0xfffff221 adc result register high byte channel 8 adcrh08 rr - - undefined 0xfffff222 adc result register channel 9 adcr09 --r- undefined 0xfffff223 adc result register high byte channel 9 adcr0h9 rr - - undefined 0xfffff224 adc result register channel 10 adcr010 --r- undefined 0xfffff225 adc result register high byte channel 10 adcr0h10 rr - - undefined 0xfffff226 adc result register channel 11 adcr011 --r- undefined 0xfffff227 adc result register high byte channel 11 adcr0h11 rr - - undefined 0xfffff228 adc result register channel 12 adcr012 --r- undefined 0xfffff229 adc result register high byte channel 12 adcr0h12 rr - - undefined 0xfffff22a adc result register channel 13 adcr013 --r- undefined 0xfffff22b adc result register high byte channel 13 adcr0h13 rr - - undefined 0xfffff22c adc result register channel 14 adcr014 --r- undefined 0xfffff22d adc result register high byte channel 14 adcr0h14 rr - - undefined 0xfffff22e adc result register channel 15 adcr015 --r- undefined 0xfffff22f adc result register high byte channel 15 adcr0h15 rr - - undefined 0xfffff300 port drive strength control register p0 pdsc0 r/w r/w - - 0x00 0xfffff302 port drive strength control register p1 pdsc1 r/w r/w - - 0x00 0xfffff304 port drive strength control register p2 pdsc2 r/w r/w - - 0x00 0xfffff306 port drive strength control register p3 pdsc3 r/w r/w - - 0x00 0xfffff308 port drive strength control register p4 pdsc4 r/w r/w - - 0x00 0xfffff30a port drive strength control register p5 pdsc5 r/w r/w - - 0x00 0xfffff30c port drive strength control register p6 pdsc6 r/w r/w - - 0x00 0xfffff310 port drive strength control register p8 pdsc8 r/w r/w - - 0x00 table b-2 other special function registers (5/20) address register name shortcut 1 8 16 32 initial value
1006 appendix b special function registers user?s manual u17566ee5v1um00 0xfffff312 port drive strength control register p9 pdsc9 r/w r/w - - 0x00 0xfffff314 port drive strength control register p10 pdsc10 r/w r/w - - 0x00 0xfffff344 port lcd control register p2 plcdc2 r/w r/w - - 0x00 0xfffff346 port lcd control register p3 plcdc3 r/w r/w - - 0x00 0xfffff348 port lcd control register p4 plcdc4 r/w r/w - - 0x00 0xfffff34c port lcd control register port 6 plcdc6 r/w r/w - - 0x00 0xfffff350 port lcd control register port 8 plcdc8 r/w r/w - - 0x00 0xfffff352 port lcd control register port 9 plcdc9 r/w r/w - - 0x00 0xfffff354 port lcd control register port 10 plcdc10 r/w r/w - - 0x00 0xfffff360 port open drain control register p0 podc0 r/w r/w - - 0x00 0xfffff362 port open drain control register p1 podc1 r/w r/w - - 0x00 0xfffff364 port open drain control register p2 podc2 r/w r/w - - 0x00 0xfffff366 port open drain control register p3 podc3 r/w r/w - - 0x00 0xfffff368 port open drain control register p4 podc4 r/w r/w - - 0x00 0xfffff36a port open drain control register p5 podc5 r/w r/w - - 0x00 0xfffff36c port open drain control register p6 podc6 r/w r/w - - 0x00 0xfffff370 port open drain control register p8 podc8 r/w r/w - - 0x00 0xfffff372 port open drain control register p9 podc9 r/w r/w - - 0x00 0xfffff374 port open drain control register p10 podc10 r/w r/w - - 0x00 0xfffff376 port open drain control register p11 podc11 r/w r/w - - 0x00 0xfffff378 port open drain control register p12 podc12 r/w r/w - - 0x00 0xfffff37a port open drain control register p13 podc13 r/w r/w - - 0x00 0xfffff380 port input characteristic control register p0 picc0 r/w r/w - - 0xff 0xfffff382 port input characteristic control register p1 picc1 r/w r/w - - 0xff 0xfffff384 port input characteristic control register p2 picc2 r/w r/w - - 0xff 0xfffff386 port input characteristic control register p3 picc3 r/w r/w - - 0xff 0xfffff388 port input characteristic control register p4 picc4 r/w r/w - - 0xff 0xfffff38a port input characteristic control register p5 picc5 r/w r/w - - 0xff 0xfffff38c port input characteristic control register p6 picc6 r/w r/w - - 0xff 0xfffff390 port input characteristic control register p8 picc8 r/w r/w - - 0xff 0xfffff392 port input characteristic control register p9 picc9 r/w r/w - - 0xff 0xfffff394 port input characteristic control register p10 picc10 r/w r/w - - 0xff 0xfffff396 port input characteristic control register p11 picc11 r/w r/w - - 0xff 0xfffff398 port input characteristic control register p12 picc12 r/w r/w - - 0xff 0xfffff39a port input characteristic control register p13 picc13 r/w r/w - - 0xff 0xfffff3a0 port input level control register p0 pilc0 r/w r/w - - 0x00 0xfffff3a2 port input level control register p1 pilc1 r/w r/w - - 0x00 0xfffff3a4 port input level control register p2 pilc2 r/w r/w - - 0x00 0xfffff3a6 port input level control register p3 pilc3 r/w r/w - - 0x00 0xfffff3a8 port input level control register p4 pilc4 r/w r/w - - 0x00 0xfffff3aa port input level control register p5 pilc5 r/w r/w - - 0x00 table b-2 other special function registers (6/20) address register name shortcut 1 8 16 32 initial value
1007 special function registers appendix b user?s manual u17566ee5v1um00 0xfffff3ac port input level control register p6 pilc6 r/w r/w - - 0x00 0xfffff3ae port input level control register p7 pilc7 --r/w- 0x0000 0xfffff3ae port input level control register p7 low byte pilc7l r/w r/w - - 0x00 0xfffff3af port input level control register p7 high byte pilc7h r/w r/w - - 0x00 0xfffff3b0 port input level control register p8 pilc8 r/w r/w - - 0x00 0xfffff3b2 port input level control register p9 pilc9 r/w r/w - - 0x00 0xfffff3b4 port input level control register p10 pilc10 r/w r/w - - 0x00 0xfffff3b6 port input level control register p11 pilc11 r/w r/w - - 0x00 0xfffff3b8 port input level control register p12 pilc12 r/w r/w - - 0x00 0xfffff3ba port input level control register p13 pilc13 r/w r/w - - 0x00 0xfffff3c0 port pin read register p0 ppr0 rr - - 0x00 0xfffff3c2 port pin read register p1 ppr1 rr - - 0x00 0xfffff3c4 port pin read register p2 ppr2 rr - - 0x00 0xfffff3c6 port pin read register p3 ppr3 rr - - 0x00 0xfffff3c8 port pin read register p4 ppr4 rr - - 0x00 0xfffff3ca port pin read register p5 ppr5 rr - - 0x00 0xfffff3cc port pin read register p6 ppr6 rr - - 0x00 0xfffff3d0 port pin read register p8 ppr8 rr - - 0x00 0xfffff3d2 port pin read register p9 ppr9 rr - - 0x00 0xfffff3d4 port pin read register p10 ppr10 rr - - 0x00 0xfffff3d6 port pin read register p11 ppr11 rr - - 0x00 0xfffff3d8 port pin read register p12 ppr12 rr - - 0x00 0xfffff3da port pin read register p13 ppr13 rr - - 0x00 0xfffff3dc port pin read register p14 ppr14 rr - - 0x00 0xfffff3e0 port read control register p0 prc0 r/w r/w - - 0x00 0xfffff3e2 port read control register p1 prc1 r/w r/w - - 0x00 0xfffff3e4 port read control register p2 prc2 r/w r/w - - 0x00 0xfffff3e6 port read control register p3 prc3 r/w r/w - - 0x00 0xfffff3e8 port read control register p4 prc4 r/w r/w - - 0x00 0xfffff3ea port read control register p5 prc5 r/w r/w - - 0x00 0xfffff3ec port read control register p6 prc6 r/w r/w - - 0x00 0xfffff3f0 port read control register p8 prc8 r/w r/w - - 0x00 0xfffff3f2 port read control register p9 prc9 r/w r/w - - 0x00 0xfffff3f4 port read control register p10 prc10 r/w r/w - - 0x00 0xfffff3f6 port read control register p11 prc11 r/w r/w - - 0x00 0xfffff3f8 port read control register p12 prc12 r/w r/w - - 0x00 0xfffff3fa port read control register p13 prc13 r/w r/w - - 0x00 0xfffff3fc port read control register p14 prc14 r/w r/w - - 0x00 0xfffff400 port register port 0 p0 r/w r/w - - 0x00 0xfffff402 port register port 1 p1 r/w r/w - - 0x00 0xfffff404 port register port 2 p2 r/w r/w - - 0x00 table b-2 other special function registers (7/20) address register name shortcut 1 8 16 32 initial value
1008 appendix b special function registers user?s manual u17566ee5v1um00 0xfffff406 port register port 3 p3 r/w r/w - - 0x00 0xfffff408 port register port 4 p4 r/w r/w - - 0x00 0xfffff40a port register port 5 p5 r/w r/w - - 0x00 0xfffff40c port register port 6 p6 r/w r/w - - 0x00 0xfffff40e port register port 7 p7 --r/w- 0x0000 0xfffff40e port register port 7 low byte p7l r/w r/w - - 0x00 0xfffff40f port register port 7 high byte p7h r/w r/w - - 0x00 0xfffff410 port register port 8 p8 r/w r/w - - 0x00 0xfffff412 port register port 9 p9 r/w r/w - - 0x00 0xfffff414 port register port 10 p10 r/w r/w - - 0x00 0xfffff416 port register port 11 p11 r/w r/w - - 0x00 0xfffff418 port register port 12 p12 r/w r/w - - 0x00 0xfffff41a port register port 13 p13 r/w r/w - - 0x00 0xfffff41c port register port 14 p14 r/w r/w - - 0x00 0xfffff420 port mode register port 0 pm0 r/w r/w - - 0xff 0xfffff422 port mode register port 1 pm1 r/w r/w - - 0xff 0xfffff424 port mode register port 2 pm2 r/w r/w - - 0xff 0xfffff426 port mode register port 3 pm3 r/w r/w - - 0xff 0xfffff428 port mode register port 4 pm4 r/w r/w - - 0xff 0xfffff42a port mode register port 5 pm5 r/w r/w - - 0xff 0xfffff42c port mode register port 6 pm6 r/w r/w - - 0xff 0xfffff430 port mode register port 8 pm8 r/w r/w - - 0xff 0xfffff432 port mode register port 9 pm9 r/w r/w - - 0xff 0xfffff434 port mode register port 10 pm10 r/w r/w - - 0xff 0xfffff436 port mode register port 11 pm11 r/w r/w - - 0xff 0xfffff438 port mode register port 12 pm12 r/w r/w - - 0xff 0xfffff43a port mode register port 13 pm13 r/w r/w - - 0xff 0xfffff43c port mode register port 14 pm14 r/w r/w - - 0xff 0xfffff440 port mode control register port 0 pmc0 r/w r/w - - 0x00 0xfffff442 port mode control register port 1 pmc1 r/w r/w - - 0x00 0xfffff444 port mode control register port 2 pmc2 r/w r/w - - 0x00 0xfffff446 port mode control register port 3 pmc3 r/w r/w - - 0x00 0xfffff448 port mode control register port 4 pmc4 r/w r/w - - 0x00 0xfffff44a port mode control register port 5 pmc5 r/w r/w - - 0x00 0xfffff44c port mode control register port 6 pmc6 r/w r/w - - 0x00 0xfffff44e port mode control register port 7 pmc7 --r/w- 0x0000 0xfffff44e port mode control register port 7 low byte pmc7l r/w r/w - - 0x00 0xfffff44f port mode control register port 7 high byte pmc7h r/w r/w - - 0x00 0xfffff450 port mode control register port 8 pmc8 r/w r/w - - 0x00 0xfffff452 port mode control register port 9 pmc9 r/w r/w - - 0x00 0xfffff454 port mode control register port 10 pmc10 r/w r/w - - 0x00 table b-2 other special function registers (8/20) address register name shortcut 1 8 16 32 initial value
1009 special function registers appendix b user?s manual u17566ee5v1um00 0xfffff456 port mode control register port 11 pmc11 r/w r/w - - 0x00 0xfffff458 port mode control register port 12 pmc12 r/w r/w - - 0x00 0xfffff45a port mode control register port 13 pmc13 r/w r/w - - 0x00 0xfffff45c port mode control register port 14 pmc14 r/w r/w - - 0x00 0xfffff460 port function control register port 0 pfc0 r/w r/w - - 0x20 0xfffff462 port function control register port 1 pfc1 r/w r/w - - 0x00 0xfffff464 port function control register port 2 pfc2 r/w r/w - - 0x00 0xfffff466 port function control register port 3 pfc3 r/w r/w - - 0x00 0xfffff46a port function control register port 5 pfc5 r/w r/w - - 0x00 0xfffff46c port function control register port 6 pfc6 r/w r/w - - 0x00 0xfffff470 port function control register port 8 pfc8 r/w r/w - - 0x00 0xfffff472 port function control register port 9 pfc9 r/w r/w - - 0x00 0xfffff474 port function control register port 10 pfc10 r/w r/w - - 0x00 0xfffff476 port function control register port 11 pfc11 r/w r/w - - 0x00 0xfffff47a port function control register port 13 pfc13 r/w r/w - - 0x00 0xfffff480 bus cycle type configuration register 0 bct0 --r/w- 0x0000 0xfffff482 bus cycle type configuration register 1 bct1 --r/w- 0x0000 0xfffff484 data wait control register 0 dwc0 --r/w- 0x7777 0xfffff486 data wait control register 1 dwc1 --r/w- 0x7777 0xfffff488 bus cycle control register bcc --r/w- 0xffff 0xfffff48a address setting wait control register asc --r/w- 0xffff 0xfffff48e local bus size control register lbs --r/w- 0xaaaa 0xfffff498 bus mode control register bmc r/w - - - 0x00 0xfffff49a page rom control register prc --r/w- 0x7000 0xfffff560 synchronized counter read register wt0 wt0cnt0 --r- 0x0000 0xfffff562 non-synchronized counter read register wt0 wt0cnt1 --r- 0x0000 0xfffff564 counter reload register wt0 wt0r --r/w- 0x0000 0xfffff566 control register wt0 wt0ctl r/w r/w - - 0x00 0xfffff570 synchronized counter read register wt1 wt1cnt0 --r- 0x0000 0xfffff572 non-synchronized counter read register wt1 wt1cnt1 --r- 0x0000 0xfffff574 counter reload register wt1 wt1r --r/w- 0x0000 0xfffff576 control register wt1 wt1ctl r/w r/w - - 0x00 0xfffff580 synchronized counter 0 read register tmy0 ty0cnt00 --r- 0x0000 0xfffff582 non-synchronized counter 0 read register tmy0 ty0cnt01 --r- 0x0000 0xfffff584 synchronized counter 1 read register tmy0 ty0cnt10 --r- 0x0000 0xfffff586 non-synchronized counter 1 read register tmy0 ty0cnt11 --r- 0x0000 0xfffff588 counter 0 reload register tmy0 ty0r0 --r/w- 0x0000 0xfffff58a counter 1 reload register tmy0 ty0r1 --r/w- 0x0000 0xfffff58c i/o control register tmy0 ty0ioc r/w r/w - - 0x00 0xfffff58d control register 0 tmy0 ty0ctl r/w r/w - - 0x00 0xfffff590 watchdog timer frequency select register wdcs r/w r/w - - 0x07 table b-2 other special function registers (9/20) address register name shortcut 1 8 16 32 initial value
1010 appendix b special function registers user?s manual u17566ee5v1um00 0xfffff592 watchdog timer security register wcmd r/w r/w - - undefined 0xfffff594 watchdog timer mode register wdtm r/w r/w - - 0x00 0xfffff596 watchdog timer error register wphs r/w r/w - - 0x00 0xfffff5a0 sg0 frequency register sg0f - - - r/w 0x00000000 0xfffff5a0 sg0 frequency register low sg0fl --r/w- 0x0000 0xfffff5a2 sg0 frequency register high sg0fh --r/w- 0x0000 0xfffff5a4 sg0 amplitude register sg0pwm --r/w- 0x0000 0xfffff5a6 sg0 duration factor register sg0sdf r/w r/w - - 0x00 0xfffff5a7 sg0 control register sg0ctl r/w r/w - - 0x00 0xfffff5a8 sg0 interrupt threshold register sg0ith --r/w- 0x0000 0xfffff5c0 timer mode control register 0 mcntc00 r/w r/w - - 0x00 0xfffff5c2 compare register 1hw mcmp01hw --r/w- 0x0000 0xfffff5c2 compare register 10 mcmp010 -r/w- - 0x00 0xfffff5c3 compare register 11 mcmp011 -r/w- - 0x00 0xfffff5c4 compare register 2hw mcmp02hw --r/w- 0x0000 0xfffff5c4 compare register 20 mcmp020 -r/w- - 0x00 0xfffff5c5 compare register 21 mcmp021 -r/w- - 0x00 0xfffff5c6 compare register 3hw mcmp03hw --r/w- 0x0000 0xfffff5c6 compare register 30 mcmp030 -r/w- - 0x00 0xfffff5c7 compare register 31 mcmp031 -r/w- - 0x00 0xfffff5c8 compare register 4hw mcmp04hw --r/w- 0x0000 0xfffff5c8 compare register 40 mcmp040 -r/w- - 0x00 0xfffff5c9 compare register 41 mcmp041 -r/w- - 0x00 0xfffff5ca compare control register 1 mcmpc01 r/w r/w - - 0x00 0xfffff5cc compare control register 2 mcmpc02 r/w r/w - - 0x00 0xfffff5ce compare control register 3 mcmpc03 r/w r/w - - 0x00 0xfffff5d0 compare control register 4 mcmpc04 r/w r/w - - 0x00 0xfffff5d4 timer mode control register 1 mcntc01 r/w r/w - - 0x00 0xfffff5d6 compare register 5hw mcmp05hw --r/w- 0x0000 0xfffff5d6 compare register 50 mcmp050 -r/w- - 0x00 0xfffff5d7 compare register 51 mcmp051 -r/w- - 0x00 0xfffff5d8 compare register 6hw mcmp06hw --r/w- 0x0000 0xfffff5d8 compare register 60 mcmp060 -r/w- - 0x00 0xfffff5d9 compare register 61 mcmp061 -r/w- - 0x00 0xfffff5da compare control register 5 mcmpc05 r/w r/w - - 0x00 0xfffff5dc compare control register 6 mcmpc06 r/w r/w - - 0x00 0xfffff5e4 tm00 16-bit capture/compare register 0 cr001 --r/w- 0x0000 0xfffff5e6 tm00 control register tmc00 r/w r/w - - 0x00 0xfffff5e7 tm00 prescaler mode register prm00 r/w r/w - - 0x00 0xfffff5e8 tm00 capture/compare control register crc00 r/w r/w - - 0x00 0xfffff600 tmz0 synchronized counter read register tz0cnt0 --r- 0x0000 table b-2 other special function registers (10/20) address register name shortcut 1 8 16 32 initial value
1011 special function registers appendix b user?s manual u17566ee5v1um00 0xfffff602 tmz0 non-synchronized counter read register tz0cnt1 --r- 0x0000 0xfffff604 tmz0 counter reload register tz0r --r/w- 0x0000 0xfffff606 tmz0 control register tz0ctl r/w r/w - - 0x00 0xfffff608 tmz1 synchronized counter read register tz1cnt0 --r- 0x0000 0xfffff60a tmz1 non-synchronized counter read register tz1cnt1 --r- 0x0000 0xfffff60c tmz1 counter reload register tz1r --r/w- 0x0000 0xfffff60e tmz1 control register tz1ctl r/w r/w - - 0x00 0xfffff610 tmz2 synchronized counter read register tz2cnt0 --r- 0x0000 0xfffff612 tmz2 non-synchronized counter read register tz2cnt1 --r- 0x0000 0xfffff614 tmz2 counter reload register tz2r --r/w- 0x0000 0xfffff616 tmz2 control register tz2ctl r/w r/w - - 0x00 0xfffff618 tmz3 synchronized counter read register tz3cnt0 --r- 0x0000 0xfffff61a tmz3 non-synchronized counter read register tz3cnt1 --r- 0x0000 0xfffff61c tmz3 counter reload register tz3r --r/w- 0x0000 0xfffff61e tmz3 control register tz3ctl r/w r/w - - 0x00 0xfffff620 tmz4 synchronized counter read register tz4cnt0 --r- 0x0000 0xfffff622 tmz4 non-synchronized counter read register tz4cnt1 --r- 0x0000 0xfffff624 tmz4 counter reload register tz4r --r/w- 0x0000 0xfffff626 tmz4 control register tz4ctl r/w r/w - - 0x00 0xfffff628 tmz5 synchronized counter read register tz5cnt0 --r- 0x0000 0xfffff62a tmz5 non-synchronized counter read register tz5cnt1 --r- 0x0000 0xfffff62c tmz5 counter reload register tz5r --r/w- 0x0000 0xfffff62e tmz5 control register tz5ctl r/w r/w - - 0x00 0xfffff630 tmz6 synchronized counter read register tz6cnt0 --r- 0x0000 0xfffff632 tmz6 non-synchronized counter read register tz6cnt1 --r- 0x0000 0xfffff634 tmz6 counter reload register tz6r --r/w- 0x0000 0xfffff636 tmz6 control register tz6ctl r/w r/w - - 0x00 0xfffff638 tmz7 synchronized counter read register tz7cnt0 --r- 0x0000 0xfffff63a tmz7 non-synchronized counter read register tz7cnt1 --r- 0x0000 0xfffff63c tmz7 counter reload register tz7r --r/w- 0x0000 0xfffff63e tmz7 control register tz7ctl r/w r/w - - 0x00 0xfffff640 tmz8 synchronized counter read register tz8cnt0 --r- 0x0000 0xfffff642 tmz8 non-synchronized counter read register tz8cnt1 --r- 0x0000 0xfffff644 tmz8 counter reload register tz8r --r/w- 0x0000 0xfffff646 tmz8 control register tz8ctl r/w r/w - - 0x00 0xfffff648 tmz9 synchronized counter read register tz9cnt0 --r- 0x0000 0xfffff64a tmz9 non-synchronized counter read register tz9cnt1 --r- 0x0000 0xfffff64c tmz9 counter reload register tz9r --r/w- 0x0000 0xfffff64e tmz9 control register tz9ctl r/w r/w - - 0x00 0xfffff660 tmp0 timer control register 0 tp0ctl0 r/w r/w - - 0x00 0xfffff661 tmp0 timer control register 1 tp0ctl1 r/w r/w - - 0x00 table b-2 other special function registers (11/20) address register name shortcut 1 8 16 32 initial value
1012 appendix b special function registers user?s manual u17566ee5v1um00 0xfffff662 tmp0 timer-specific i/o control register 0 tp0ioc0 r/w r/w - - 0x00 0xfffff663 tmp0 timer-specific i/o control register 1 tp0ioc1 r/w r/w - - 0x00 0xfffff664 tmp0 timer-specific i/o control register 2 tp0ioc2 r/w r/w - - 0x00 0xfffff665 tmp0 option register tp0opt0 r/w r/w - - 0x00 0xfffff666 tmp0 capture/compare register 0 tp0ccr0 --r/w- 0x0000 0xfffff668 tmp0 capture/compare register 1 tp0ccr1 --r/w- 0x0000 0xfffff66a tmp0 count register tp0cnt --r- 0x0000 0xfffff670 tmp1 timer control register 0 tp1ctl0 r/w r/w - - 0x00 0xfffff671 tmp1 timer control register 1 tp1ctl1 r/w r/w - - 0x00 0xfffff672 tmp1 timer-specific i/o control register 0 tp1ioc0 r/w r/w - - 0x00 0xfffff673 tmp1 timer-specific i/o control register 1 tp1ioc1 r/w r/w - - 0x00 0xfffff674 tmp1 timer-specific i/o control register 2 tp1ioc2 r/w r/w - - 0x00 0xfffff675 tmp1 option register tp1opt0 r/w r/w - - 0x00 0xfffff676 tmp1 capture/compare register 0 tp1ccr0 --r/w- 0x0000 0xfffff678 tmp1 capture/compare register 1 tp1ccr1 --r/w- 0x0000 0xfffff67a tmp1 count register tp1cnt --r- 0x0000 0xfffff680 tmp2 timer control register 0 tp2ctl0 r/w r/w - - 0x00 0xfffff681 tmp2 timer control register 1 tp2ctl1 r/w r/w - - 0x00 0xfffff682 tmp2 timer-specific i/o control register 0 tp2ioc0 r/w r/w - - 0x00 0xfffff683 tmp2 timer-specific i/o control register 1 tp2ioc1 r/w r/w - - 0x00 0xfffff684 tmp2 timer-specific i/o control register 2 tp2ioc2 r/w r/w - - 0x00 0xfffff685 tmp2 option register tp2opt0 r/w r/w - - 0x00 0xfffff686 tmp2 capture/compare register 0 tp2ccr0 --r/w- 0x0000 0xfffff688 tmp2 capture/compare register 1 tp2ccr1 --r/w- 0x0000 0xfffff68a tmp2 count register tp2cnt --r- 0x0000 0xfffff690 tmp3 timer control register 0 tp3ctl0 r/w r/w - - 0x00 0xfffff691 tmp3 timer control register 1 tp3ctl1 r/w r/w - - 0x00 0xfffff692 tmp3 timer-specific i/o control register 0 tp3ioc0 r/w r/w - - 0x00 0xfffff693 tmp3 timer-specific i/o control register 1 tp3ioc1 r/w r/w - - 0x00 0xfffff694 tmp3 timer-specific i/o control register 2 tp3ioc2 r/w r/w - - 0x00 0xfffff695 tmp3 option register tp3opt0 r/w r/w - - 0x00 0xfffff696 tmp3 capture/compare register 0 tp3ccr0 --r/w- 0x0000 0xfffff698 tmp3 capture/compare register 1 tp3ccr1 --r/w- 0x0000 0xfffff69a tmp3 count register tp3cnt --r- 0x0000 0xfffff6a0 timer mode register tmg 0 tmgm0 --r/w- 0x0000 0xfffff6a0 timer mode register tmg 0 low byte tmgm0l r/w r/w - - 0x00 0xfffff6a1 timer mode register tmg 0 high byte tmgm0h r/w r/w - - 0x00 0xfffff6a2 channel mode register tmg 0 tmgcm0 --r/w- 0x0000 0xfffff6a2 channel mode register tmg 0 low byte tmgcm0l r/w r/w - - 0x00 0xfffff6a3 channel mode register tmg 0 high byte tmgcm0h r/w r/w - - 0x00 0xfffff6a4 output control register tmg 0 octlg0 --r/w- 0x4444 table b-2 other special function registers (12/20) address register name shortcut 1 8 16 32 initial value
1013 special function registers appendix b user?s manual u17566ee5v1um00 0xfffff6a4 output control register tmg 0 low byte octlg0l r/w r/w - - 0x44 0xfffff6a5 output control register tmg 0 high byte octlg0h r/w r/w - - 0x44 0xfffff6a6 time base status register tmg 0 tmgst0 rr - - 0x00 0xfffff6a8 timer count register 0 tmg 0 tmg00 --r- 0x0000 0xfffff6aa timer count register 1 tmg 0 tmg01 --r- 0x0000 0xfffff6ac capture / compare register 0 tmg 0 gcc00 --r/w- 0x0000 0xfffff6ae capture / compare register 1 tmg 0 gcc01 --r/w- 0x0000 0xfffff6b0 capture / compare register 2 tmg 0 gcc02 --r/w- 0x0000 0xfffff6b2 capture / compare register 3 tmg 0 gcc03 --r/w- 0x0000 0xfffff6b4 capture / compare register 4 tmg 0 gcc04 --r/w- 0x0000 0xfffff6b6 capture / compare register 5 tmg 0 gcc05 --r/w- 0x0000 0xfffff6c0 timer mode register tmg 1 tmgm1 --r/w- 0x0000 0xfffff6c0 timer mode register tmg 1 low byte tmgm1l r/w r/w - - 0x00 0xfffff6c1 timer mode register tmg 1 high byte tmgm1h r/w r/w - - 0x00 0xfffff6c2 channel mode register tmg 1 tmgcm1 --r/w- 0x0000 0xfffff6c2 channel mode register tmg 1 low byte tmgcm1l r/w r/w - - 0x00 0xfffff6c3 channel mode register tmg 1 high byte tmgcm1h r/w r/w - - 0x00 0xfffff6c4 output control register tmg 1 octlg1 --r/w- 0x4444 0xfffff6c4 output control register tmg 1 low byte octlg1l r/w r/w - - 0x44 0xfffff6c5 output control register tmg 1 high byte octlg1h r/w r/w - - 0x44 0xfffff6c6 time base status tmg 1 tmgst1 rr - - 0x00 0xfffff6c8 timer count register 0 tmg 1 tmg10 --r- 0x0000 0xfffff6ca timer count register 1 tmg 1 tmg11 --r- 0x0000 0xfffff6cc capture / compare register 0 tmg 1 gcc10 --r/w- 0x0000 0xfffff6ce capture / compare register 1 tmg 1 gcc11 --r/w- 0x0000 0xfffff6d0 capture / compare register 2 tmg 1 gcc12 --r/w- 0x0000 0xfffff6d2 capture / compare register 3 tmg 1 gcc13 --r/w- 0x0000 0xfffff6d4 capture / compare register 4 tmg 1 gcc14 --r/w- 0x0000 0xfffff6d6 capture / compare register 5 tmg 1 gcc15 --r/w- 0x0000 0xfffff6e0 timer mode register tmg 2 tmgm2 --r/w- 0x0000 0xfffff6e0 timer mode register tmg 2 low byte tmgm2l r/w r/w - - 0x00 0xfffff6e1 timer mode register tmg 2 high byte tmgm2h r/w r/w - - 0x00 0xfffff6e2 channel mode register tmg 2 tmgcm2 --r/w- 0x0000 0xfffff6e2 channel mode register tmg 2 low byte tmgcm2l r/w r/w - - 0x00 0xfffff6e3 channel mode register tmg 2 high byte tmgcm2h r/w r/w - - 0x00 0xfffff6e4 output control register tmg 2 octlg2 --r/w- 0x4444 0xfffff6e4 output control register tmg 2 low byte octlg2l r/w r/w - - 0x44 0xfffff6e5 output control register tmg 2 high byte octlg2h r/w r/w - - 0x44 0xfffff6e6 time base status tmg 2 tmgst2 rr - - 0x00 0xfffff6e8 timer count register 0 tmg 2 tmg20 --r- 0x0000 0xfffff6ea timer count register 1 tmg 2 tmg21 --r- 0x0000 table b-2 other special function registers (13/20) address register name shortcut 1 8 16 32 initial value
1014 appendix b special function registers user?s manual u17566ee5v1um00 0xfffff6ec capture / compare register 0 tmg 2 gcc20 --r/w- 0x0000 0xfffff6ee capture / compare register 1 tmg 2 gcc21 --r/w- 0x0000 0xfffff6f0 capture / compare register 2 tmg 2 gcc22 --r/w- 0x0000 0xfffff6f2 capture / compare register 3 tmg 2 gcc23 --r/w- 0x0000 0xfffff6f4 capture / compare register 4 tmg 2 gcc24 --r/w- 0x0000 0xfffff6f6 capture / compare register 5 tmg 2 gcc25 --r/w- 0x0000 0xfffff700 interrupt mode register 0 intm0 r/w r/w - - 0x00 0xfffff702 interrupt mode register 1 intm1 r/w r/w - - 0x00 0xfffff704 interrupt mode register 2 intm2 r/w r/w - - 0x00 0xfffff706 interrupt mode register 3 intm3 r/w r/w - - 0x00 0xfffff710 digital filter enable register 0 dfen0 --r/w- 0x0000 0xfffff710 digital filter enable register 0 low byte dfen0l r/w r/w - - 0x00 0xfffff711 digital filter enable register 0 high byte dfen0h r/w r/w - - 0x00 0xfffff712 digital filter enable register 1 dfen1 --r/w- 0x0000 0xfffff712 digital filter enable register 1 low byte dfen1l r/w r/w - - 0x00 0xfffff713 digital filter enable register 1 high byte dfen1h r/w r/w - - 0x00 0xfffff71a sub oscillator clock monitor control register clmcs r/w r/w - - 0x00 0xfffff720 peripheral function select register 0 pfsr0 r/w r/w - - 0x01 0xfffff726 peripheral function select register 3 pfsr3 r/w r/w - - 0x01 0xfffff800 protection register phcmd -r/w- - undefined 0xfffff802 peripheral status phs r/w r/w - - 0x00 0xfffff820 power save mode psm r/w r/w - - 0x08/0x00 0xfffff822 clock control ckc -r/w- - 0x00 0xfffff824 clock generator status cgstat -r- - 0x0d 0xfffff826 watch dog clock control wcc -r/w- - 0x00 0xfffff828 processor clock control pcc -r/w- - 0x10 0xfffff82a frequency modulation control scfmc r/w r/w - - 0x00 0xfffff82c frequency control 0 scfc0 r/w r/w - - 0x52 0xfffff82e frequency control 1 scfc1 r/w r/w - - 0xeb 0xfffff830 sscg postscaler control scps r/w r/w - - 0x21 0xfffff832 spclk control scc r/w r/w - - 0x00 0xfffff834 foutclk control fcc r/w r/w - - 0x00 0xfffff836 watch timer clock control tcc r/w r/w - - 0x00 0xfffff838 iic clock control icc r/w r/w - - 0x00 0xfffff83c set default clock sdc -r/w- - 0x00 0xfffff840 vfb flash/rom correction address register 0 corad0 - - - r/w 0x00000000 0xfffff840 vfb flash/rom correction address register 0l corad0l --r/w- 0x0000 0xfffff842 vfb flash/rom correction address register 0h corad0h --r/w- 0x0000 0xfffff844 vfb flash/rom correction address register 1 corad1 - - - r/w 0x00000000 0xfffff844 vfb flash/rom correction address register 1l corad1l --r/w- 0x0000 0xfffff846 vfb flash/rom correction address register 1h corad1h --r/w- 0x0000 table b-2 other special function registers (14/20) address register name shortcut 1 8 16 32 initial value
1015 special function registers appendix b user?s manual u17566ee5v1um00 0xfffff848 vfb flash/rom correction address register 2 corad2 - - - r/w 0x00000000 0xfffff848 vfb flash/rom correction address register 2l corad2l --r/w- 0x0000 0xfffff84a vfb flash/rom correction address register 2h corad2h --r/w- 0x0000 0xfffff84c vfb flash/rom correction address register 3 corad3 - - - r/w 0x00000000 0xfffff84c vfb flash/rom correction address register 3l corad3l --r/w- 0x0000 0xfffff84e vfb flash/rom correction address register 3h corad3h --r/w- 0x0000 0xfffff850 vfb flash/rom correction address register 4 corad4 - - - r/w 0x00000000 0xfffff850 vfb flash/rom correction address register 4l corad4l --r/w- 0x0000 0xfffff852 vfb flash/rom correction address register 4h corad4h --r/w- 0x0000 0xfffff854 vfb flash/rom correction address register 5 corad5 - - - r/w 0x00000000 0xfffff854 vfb flash/rom correction address register 5l corad5l --r/w- 0x0000 0xfffff856 vfb flash/rom correction address register 5h corad5h --r/w- 0x0000 0xfffff858 vfb flash/rom correction address register 6 corad6 - - - r/w 0x00000000 0xfffff858 vfb flash/rom correction address register 6l corad6l --r/w- 0x0000 0xfffff85a vfb flash/rom correction address register 6h corad6h --r/w- 0x0000 0xfffff85c vfb flash/rom correction address register 7 corad7 - - - r/w 0x00000000 0xfffff85c vfb flash/rom correction address register 7l corad7l --r/w- 0x0000 0xfffff85e vfb flash/rom correction address register 7l corad7h --r/w- 0x0000 0xfffff870 main oscillator clock monitor mode register clmm r/w r/w - - 0x00 0xfffff878 sub oscillator clock monitor mode register clms r/w r/w - - 0x00 0xfffff880 vfb flash/rom correction control register corcn -r/w- - 0x0000 0xfffff8a0 vsb flash correction address register 0 cor2ad0 - - - r/w 0x00000000 0xfffff8a0 vsb flash correction address register 0l cor2ad0l --r/w- 0x0000 0xfffff8a2 vsb flash correction address register 0h cor2ad0h --r/w- 0x0000 0xfffff8a4 vsb flash correction address register 1 cor2ad1 - - - r/w 0x00000000 0xfffff8a4 vsb flash correction address register 1l cor2ad1l --r/w- 0x0000 0xfffff8a6 vsb flash correction address register 1h cor2ad1h --r/w- 0x0000 0xfffff8a8 vsb flash correction address register 2 cor2ad2 - - - r/w 0x00000000 0xfffff8a8 vsb flash correction address register 2l cor2ad2l --r/w- 0x0000 0xfffff8aa vsb flash correction address register 2h cor2ad2h --r/w- 0x0000 0xfffff8ac vsb flash correction address register 3 cor2ad3 - - - r/w 0x00000000 0xfffff8ac vsb flash correction address register 3l cor2ad3l --r/w- 0x0000 0xfffff8ae vsb flash correction address register 3h cor2ad3h --r/w- 0x0000 0xfffff8b0 vsb flash correction address register 4 cor2ad4 - - - r/w 0x00000000 0xfffff8b0 vsb flash correction address register 4l cor2ad4l --r/w- 0x0000 0xfffff8b2 vsb flash correction address register 4h cor2ad4h --r/w- 0x0000 0xfffff8b4 vsb flash correction address register 5 cor2ad5 - - - r/w 0x00000000 0xfffff8b4 vsb flash correction address register 5l cor2ad5l --r/w- 0x0000 0xfffff8b6 vsb flash correction address register 5h cor2ad5h --r/w- 0x0000 0xfffff8b8 vsb flash correction address register 6 cor2ad6 - - - r/w 0x00000000 0xfffff8b8 vsb flash correction address register 6l cor2ad6l --r/w- 0x0000 table b-2 other special function registers (15/20) address register name shortcut 1 8 16 32 initial value
1016 appendix b special function registers user?s manual u17566ee5v1um00 0xfffff8ba vsb flash correction address register 6h cor2ad6h --r/w- 0x0000 0xfffff8bc vsb flash correction address register 7 cor2ad7 - - - r/w 0x00000000 0xfffff8bc vsb flash correction address register 7l cor2ad7l --r/w- 0x0000 0xfffff8be vsb flash correction address register 7l cor2ad7h --r/w- 0x0000 0xfffff900 vfb flash/rom correction control register 0 corctl0 -r/w- - 0x00 0xfffff901 vfb flash/rom correction control register 1 corctl1 -r/w- - 0x00 0xfffff910 vfb flash/rom correction address register 0l coradr0l - - r/w - 0x0000 0xfffff910 vfb flash/rom correction address register 0ll coradr0ll - r/w - - 0x00 0xfffff911 vfb flash/rom correction address register 0lh coradr0lh - r/w - - 0x00 0xfffff912 vfb flash/rom correction address register 0h coradr0h - - r/w - 0x0000 0xfffff912 vfb flash/rom correction address register 0hl coradr0hl - r/w - - 0x00 0xfffff913 vfb flash/rom correction address register 0hh coradr0hh - r/w - - 0x00 0xfffff914 vfb flash/rom correction address register 1l coradr1l - - r/w - 0x0000 0xfffff914 vfb flash/rom correction address register 1ll coradr1ll - r/w - - 0x00 0xfffff915 vfb flash/rom correction address register 1lh coradr1lh - r/w - - 0x00 0xfffff916 vfb flash/rom correction address register 1h coradr1h - - r/w - 0x0000 0xfffff916 vfb flash/rom correction address register 1hl coradr1hl - r/w - - 0x00 0xfffff917 vfb flash/rom correction address register 1hh coradr1hh - r/w - - 0x00 0xfffff918 vfb flash/rom correction address register 2l coradr2l - - r/w - 0x0000 0xfffff918 vfb flash/rom correction address register 2ll coradr2ll - r/w - - 0x00 0xfffff919 vfb flash/rom correction address register 2lh coradr2lh - r/w - - 0x00 0xfffff91a vfb flash/rom correction address register 2h coradr2h - - r/w - 0x0000 0xfffff91a vfb flash/rom correction address register 2hl coradr2hl - r/w - - 0x00 0xfffff91b vfb flash/rom correction address register 2hh coradr2hh - r/w - - 0x00 0xfffff91c vfb flash/rom correction address register 3l coradr3l - - r/w - 0x0000 0xfffff91c vfb flash/rom correction address register 3ll coradr3ll - r/w - - 0x00 0xfffff91d vfb flash/rom correction address register 3lh coradr3lh - r/w - - 0x00 0xfffff91e vfb flash/rom correction address register 3h coradr3h - - r/w - 0x0000 0xfffff91e vfb flash/rom correction address register 3hl coradr3hl - r/w - - 0x00 0xfffff91f vfb flash/rom correction address register 3hh coradr3hh - r/w - - 0x00 0xfffff920 vfb flash/rom correction address register 4l coradr4l - - r/w - 0x0000 0xfffff920 vfb flash/rom correction address register 4ll coradr4ll - r/w - - 0x00 0xfffff921 vfb flash/rom correction address register 4lh coradr4lh - r/w - - 0x00 0xfffff922 vfb flash/rom correction address register 4h coradr4h - - r/w - 0x0000 0xfffff922 vfb flash/rom correction address register 4hl coradr4hl - r/w - - 0x00 0xfffff923 vfb flash/rom correction address register 4hh coradr4hh - r/w - - 0x00 0xfffff924 vfb flash/rom correction address register 5l coradr5l - - r/w - 0x0000 0xfffff924 vfb flash/rom correction address register 5ll coradr5ll - r/w - - 0x00 0xfffff925 vfb flash/rom correction address register 5lh coradr5lh - r/w - - 0x00 0xfffff926 vfb flash/rom correction address register 5h coradr5h - - r/w - 0x0000 0xfffff926 vfb flash/rom correction address register 5hl coradr5hl - r/w - - 0x00 table b-2 other special function registers (16/20) address register name shortcut 1 8 16 32 initial value
1017 special function registers appendix b user?s manual u17566ee5v1um00 0xfffff927 vfb flash/rom correction address register 5hh coradr5hh - r/w - - 0x00 0xfffff930 vfb flash/rom correction value register 0l corval0l --r/w- 0x0000 0xfffff932 vfb flash/rom correction value register 0h corval0h --r/w- 0x0000 0xfffff934 vfb flash/rom correction value register 1l corval1l --r/w- 0x0000 0xfffff936 vfb flash/rom correction value register 1h corval1h --r/w- 0x0000 0xfffff938 vfb flash/rom correction value register 2l corval2l --r/w- 0x0000 0xfffff93a vfb flash/rom correction value register 2h corval2h --r/w- 0x0000 0xfffff93c vfb flash/rom correction value register 3l corval3l --r/w- 0x0000 0xfffff93e vfb flash/rom correction value register 3h corval3h --r/w- 0x0000 0xfffff940 vfb flash/rom correction value register 4l corval4l --r/w- 0x0000 0xfffff942 vfb flash/rom correction value register 4h corval4h --r/w- 0x0000 0xfffff944 vfb flash/rom correction value register 5l corval5l --r/w- 0x0000 0xfffff946 vfb flash/rom correction value register 5h corval5h --r/w- 0x0000 0xfffff9d0 vsb flash correction control register cor2cn -r/w- - 0x00 0xfffff9fc on chip debug mode register ocdm r/w r/w - - 0x00/0x01 0xfffffa00 uarta0 control register 0 ua0ctl0 r/w r/w - - 0x10 0xfffffa01 uarta0 control register 1 ua0ctl1 r/w r/w - - 0x00 0xfffffa02 uarta0 control register 2 ua0ctl2 r/w r/w - - 0xff 0xfffffa03 uarta0 option register ua0opt0 r/w r/w - - 0x14 0xfffffa04 uarta0 status register ua0str r/w r/w - - 0x00 0xfffffa06 uarta0 reception data register ua0rx -r- - 0xff 0xfffffa07 uarta0 transfer data register ua0tx r/w r/w - - 0xff 0xfffffa10 uarta1 control register 0 ua1ctl0 r/w r/w - - 0x10 0xfffffa11 uarta1 control register 1 ua1ctl1 r/w r/w - - 0x00 0xfffffa12 uarta1 control register 2 ua1ctl2 r/w r/w - - 0xff 0xfffffa13 uarta1 option register ua1opt0 r/w r/w - - 0x14 0xfffffa14 uarta1 status register ua1str r/w r/w - - 0x00 0xfffffa16 uarta1 reception data register ua1rx -r- - 0xff 0xfffffa17 uarta1 transfer data register ua1tx r/w r/w - - 0xff 0xfffffb00 lcd clock control lcdc0 r/w r/w - - 0x00 0xfffffb01 lcd display mode control lcdm0 r/w r/w - - 0x00 0xfffffb20 lcd ram data segreg000 r/w r/w - - 0x00 0xfffffb20 lcd ram data segreg020 r/w r/w - - 0x00 0xfffffb21 lcd ram data segreg001 r/w r/w - - 0x00 0xfffffb21 lcd ram data segreg021 r/w r/w - - 0x00 0xfffffb22 lcd ram data segreg002 r/w r/w - - 0x00 0xfffffb22 lcd ram data segreg022 r/w r/w - - 0x00 0xfffffb23 lcd ram data segreg003 r/w r/w - - 0x00 0xfffffb23 lcd ram data segreg023 r/w r/w - - 0x00 0xfffffb24 lcd ram data segreg004 r/w r/w - - 0x00 0xfffffb24 lcd ram data segreg024 r/w r/w - - 0x00 table b-2 other special function registers (17/20) address register name shortcut 1 8 16 32 initial value
1018 appendix b special function registers user?s manual u17566ee5v1um00 0xfffffb25 lcd ram data segreg005 r/w r/w - - 0x00 0xfffffb25 lcd ram data segreg025 r/w r/w - - 0x00 0xfffffb26 lcd ram data segreg006 r/w r/w - - 0x00 0xfffffb26 lcd ram data segreg026 r/w r/w - - 0x00 0xfffffb27 lcd ram data segreg007 r/w r/w - - 0x00 0xfffffb27 lcd ram data segreg027 r/w r/w - - 0x00 0xfffffb28 lcd ram data segreg008 r/w r/w - - 0x00 0xfffffb28 lcd ram data segreg028 r/w r/w - - 0x00 0xfffffb29 lcd ram data segreg009 r/w r/w - - 0x00 0xfffffb29 lcd ram data segreg029 r/w r/w - - 0x00 0xfffffb30 lcd ram data segreg010 r/w r/w - - 0x00 0xfffffb30 lcd ram data segreg030 r/w r/w - - 0x00 0xfffffb31 lcd ram data segreg011 r/w r/w - - 0x00 0xfffffb31 lcd ram data segreg031 r/w r/w - - 0x00 0xfffffb32 lcd ram data segreg012 r/w r/w - - 0x00 0xfffffb33 lcd ram data segreg013 r/w r/w - - 0x00 0xfffffb34 lcd ram data segreg014 r/w r/w - - 0x00 0xfffffb35 lcd ram data segreg015 r/w r/w - - 0x00 0xfffffb36 lcd ram data segreg016 r/w r/w - - 0x00 0xfffffb37 lcd ram data segreg017 r/w r/w - - 0x00 0xfffffb38 lcd ram data segreg018 r/w r/w - - 0x00 0xfffffb39 lcd ram data segreg019 r/w r/w - - 0x00 0xfffffb40 lcd ram data segreg032 r/w r/w - - 0x00 0xfffffb41 lcd ram data segreg033 r/w r/w - - 0x00 0xfffffb42 lcd ram data segreg034 r/w r/w - - 0x00 0xfffffb43 lcd ram data segreg035 r/w r/w - - 0x00 0xfffffb44 lcd ram data segreg036 r/w r/w - - 0x00 0xfffffb45 lcd ram data segreg037 r/w r/w - - 0x00 0xfffffb46 lcd ram data segreg038 r/w r/w - - 0x00 0xfffffb47 lcd ram data segreg039 r/w r/w - - 0x00 0xfffffb60 lcd bus interface control lbctl0 r/w r/w - - 0x00 0xfffffb61 lcd bus interface cycle time lbcyc0 r/w r/w - - 0x02 0xfffffb62 lcd bus interface wait states lbwst0 r/w r/w - - 0x00 0xfffffb70 lcd bus interface data lbdata0w - - - r/w 0x00000000 0xfffffb70 lcd bus interface data lbdata0 --r/w- 0x0000 0xfffffb70 lcd bus interface data lbdata0l -r/w- - 0x00 0xfffffb74 lcd bus interface data lbdatar0w - - - r 0x00000000 0xfffffb74 lcd bus interface data lbdatar0 --r- 0x0000 0xfffffb74 lcd bus interface data lbdatar0l -r- - 0x00 0xfffffca0 self-programming enable control register selfen r/w r/w - - 0x00 0xfffffca2 stand-by control register stbctl r/w r/w 0x00 table b-2 other special function registers (18/20) address register name shortcut 1 8 16 32 initial value
1019 special function registers appendix b user?s manual u17566ee5v1um00 0xfffffca8 self-programming enable protection register selfenp -w- - undefined 0xfffffcaa stand-by control protection register stbctlp -w undefined 0xfffffcb0 clmm write protection register prcmdcmm - w - - undefined 0xfffffcb2 clms write protection register prcmdcms - w - - undefined 0xfffffd00 csib0 control register 0 cb0ctl0 r/w r/w - - 0x01 0xfffffd01 csib0 control register 1 cb0ctl1 r/w r/w - - 0x00 0xfffffd02 csib0 control register 2 cb0ctl2 -r/w- - 0x00 0xfffffd03 csib0 status register cb0str r/w r/w - - 0x00 0xfffffd04 csib0 received data register cb0rx0 --r- 0x0000 0xfffffd04 csib0 received data register low byte cb0rx0l -r- - 0x00 0xfffffd06 csib0 send data register cb0tx0 --r/w- 0x0000 0xfffffd06 csib0 send data register low byte cb0tx0l -r/w- - 0x00 0xfffffd10 csib1 control register 0 cb1ctl0 r/w r/w - - 0x01 0xfffffd11 csib1 control register 1 cb1ctl1 r/w r/w - - 0x00 0xfffffd12 csib1 control register 2 cb1ctl2 -r/w- - 0x00 0xfffffd13 csib1 status register cb1str r/w r/w - - 0x00 0xfffffd14 csib1 received data register cb1rx0 --r- 0x0000 0xfffffd14 csib1 received data register low byte cb1rx0l -r- - 0x00 0xfffffd16 csib1 send data register cb1tx0 --r/w- 0x0000 0xfffffd16 csib1 send data register low byte cb1tx0l -r/w- - 0x00 0xfffffd20 csib2 control register 0 cb2ctl0 r/w r/w - - 0x01 0xfffffd21 csib2 control register 1 cb2ctl1 r/w r/w - - 0x00 0xfffffd22 csib2 control register 2 cb2ctl2 -r/w- - 0x00 0xfffffd23 csib2 status register cb2str r/w r/w - - 0x00 0xfffffd24 csib2 received data register cb2rx0 --r- 0x0000 0xfffffd24 csib2 received data register low byte cb2rx0l -r- - 0x00 0xfffffd26 csib2 send data register cb2tx0 --r/w- 0x0000 0xfffffd26 csib2 send data register low byte cb2tx0l -r/w- - 0x00 0xfffffd80 iic0 shift register iic0 -r/w- - 0x00 0xfffffd82 iic0 control register iicc0 r/w r/w - - 0x00 0xfffffd83 iic0 slave address register sva0 -r/w- - 0x00 0xfffffd84 iic0 combined iiccl0 and iicx0 register iiccl0iicx0 --r/w- 0x0000 0xfffffd84 iic0 clock selection register iiccl0 r/w r/w - - 0x00 0xfffffd85 iic0 function expansion register iicx0 r/w r/w - - 0x00 0xfffffd86 iic0 state register iics0 rr - - 0x00 0xfffffd87 iic0 state register (for emulation only) iicse0 rr - - 0x00 0xfffffd8a iic0 flag register iicf0 r/w r/w - - 0x00 0xfffffd90 iic1 shift register iic1 -r/w- - 0x00 0xfffffd92 iic1 control register iicc1 r/w r/w - - 0x00 0xfffffd93 iic1 slave address register sva1 -r/w- - 0x00 0xfffffd94 iic1 combined iiccl0 and iicx0 register iiccl1iicx1 --r/w- 0x0000 table b-2 other special function registers (19/20) address register name shortcut 1 8 16 32 initial value
1020 appendix b special function registers user?s manual u17566ee5v1um00 0xfffffd94 iic1 clock selection register iiccl1 r/w r/w - - 0x00 0xfffffd95 iic1 function expansion register iicx1 r/w r/w - - 0x00 0xfffffd96 iic1 state register iics1 rr - - 0x00 0xfffffd97 iic1 state register (for emulation only) iicse1 rr - - 0x00 0xfffffd9a iic1 flag register iicf1 r/w r/w - - 0x00 0xfffffda0 clock selection register odd prescaler 0 ocks0 r/w r/w - - 0x00 0xfffffdb0 clock selection register odd prescaler 1 ocks1 r/w r/w - - 0x00 0xfffffdc0 pre-scalar mode register prsm0 r/w r/w - - 0x00 0xfffffdc1 pre-scalar compare register prscm0 r/w r/w - - 0x00 0xfffffde0 pre-scalar mode register prsm1 r/w r/w - - 0x00 0xfffffde1 pre-scalar co mpare register prscm1 r/w r/w - - 0x00 0xfffffdf0 pre-scalar mode register prsm2 r/w r/w - - 0x00 0xfffffdf1 pre-scalar co mpare register prscm2 r/w r/w - - 0x00 0xfffffe00 dma trigger source select register 0 dtfr0 r/w r/w - - 0x00 0xfffffe02 dma trigger source select register 1 dtfr1 r/w r/w - - 0x00 0xfffffe04 dma trigger source select register 2 dtfr2 r/w r/w - - 0x00 0xfffffe06 dma trigger source select register 3 dtfr3 r/w r/w - - 0x00 0xffffff00 read delay control register rddly r/w r/w - - 0x00 0xffffff10 voltage comparator 0 control vcctl0 r/w r/w - - 0x00 0xffffff12 voltage comparator 0 status vcstr0 r/w r/w - - 0x01 0xffffff14 voltage comparator 1 control vcctl1 r/w r/w - - 0x00 0xffffff16 voltage comparator 1 status vcstr1 r/w r/w - - 0x01 0xffffff20 reset source flag register resstat r/w r/w - - 0x02/0x01 0xffffff22 software reset register resswt ww - - 0x00 0xffffff24 software reset enable register rescmd ww - - 0x00 0xffffff26 reset status register res -r/w- - 0x00 table b-2 other special function registers (20/20) address register name shortcut 1 8 16 32 initial value
1021 user?s manual u17566ee5v1um00 revision history this revision list shows all functional changes of this document u17566ee5v1um00 compared to the previous manual version u17566ee4v0um00 (date published 5/6/09) and u17566ee5v0um00 (date published 6/10/09) revison history compared to u17566ee4v0um00 chapter page description 118 3rd can channel (can2) added for pd70f3421, pd70f3422, pd70f3423, pd70f3424, pd70f3425, pd70f3427 1 18 3rd tmg channel (tmg2) added for pd70f3421, pd70f3422, and pd70f3423 120 3rd can channel (can2) added for pd70f3421, pd70f3422, pd70f3423, pd70f3424, pd70f3425, pd70f3427 121 block diagram of v850e/dj3 updated and corrected:- can 2 added- tmg2 inputs corrected to tig20 to tig25 1 22 note for tmg2 removed from table 1 22 note for can2 channel added to table 1 23 block diagram of v850e/dl3 updated:- can2 added 2 35 description of 16-bit access for pmn registers removed 2 40 description of 16-bit access for pprn registers removed 2 42 description of 16-bit access for pilcn registers added 2 55 alternative output ctxd2 added to p16 2 55 alternative input crxd2 added to p17 2 55 alternative outputs tog21 to tog24 added to p34 to p37 2 55 alternative inputs tig21 to tig24 added to p34 to p37 2 56 alternative input tig20 added to p60 2 56 alternative output tog21 added to p61 2 56 alternative input tig21 added to p61 2 56 alternative input tig25 added to p62 2 56 alternative output tog24 added to p63 2 56 alternative input tig24 added to p63 2 56 alternative output tog22 added to p66 2 56 alternative input tig22 added to p66 2 56 alternative output tog23 added to p67 2 56 alternative input tig23 added to p67 2 57 alternative outputs tog21 to tog24 added to p110 to p113 2 58 alternative output ctxd2 added to p16 2 58 alternative input crxd2 added to p17 262 alternative input crxd2 added to list of pd70f3421, pd70f3422, pd70f3423, pd70f3424, pd70f3425, and pd70f3427 262 alternative output ctxd2 added to list of pd70f3421, pd70f3422, pd70f3423, pd70f3424, pd70f3425, and pd70f3427 266 alternative inputs tig20 to tig25 added to list of pd70f3421, pd70f3422, and pd70f3423 266 alternative outputs tog21 to tog24 added to list of pd70f3421, pd70f3422, and pd70f3423
1022 user?s manual u17566ee5v1um00 2 71 alternative output ctxd2 added to p16 2 71 alternative input crxd2 added to p17 2 71 pfc1 register added 2 75 pfc34 to pfc37 bits available on all devices 2 81 pfc61, pfc63, pfc66 and pfc67 bits available on all devices 2 91 pfc111 to pfc113 bits available on all devices 2 91 pfc111 to pfc113 bits available on all devices 2110 tig20 to tig25, tog21 to tog24, crxd2, ctxd2 added to pin overview of of pd70f3421, pd70f3422, pd70f3423 2111 crxd2, ctxd2 added to pin overview of of pd70f3424, pd70f3425, pd70f3426a 2 112 crxd2, ctxd2 added to pin overview of pd70f3427 5217 tmg2 interrupts (inttg2ov0, inttg2ov1, inttg2cc0, inttg2cc1, inttg2cc2, inttg2cc3, inttg2cc4, inttg2cc5) added to interrupt/exeception source list of pd70f3421, pd70f3422, pd70f3423 5217 can2 interrupts (int2err, intc2wup, in tc2rec, intc2trx) added to interrupt/ exeception source list of pd70f3421, pd70f3422, pd70f3423 5221 tmg2 interrupts (inttg2ov0, inttg2ov1, inttg2cc0, inttg2cc1, inttg2cc2, inttg2cc3, inttg2cc4, inttg2cc5) added to interrupt/exeception source list of pd70f3424, pd70f3425, pd70f3426a, pd70f3427 5221 can2 interrupts (int2err, intc2wup, in tc2rec, intc2trx) added to interrupt/ exeception source list of pd70f3424, pd70f3425, pd70f3426a, pd70f3427 5249 can2 interrupt control registers (c2erric, c2wupic, c2recic, c2trxic) added to tabel of addresses and bits of interrupt control registers 5253 mask bits tg2ov0mk, tg2ov1mk, tg2cc0mk to tg2cc5mk added to imr5 register of pd70f3421, pd70f3422, pd70f3423 7 292 vsb ram memory size corrected to 24 kb 7 292 end address of vsb ram adress range corrected to 00605fffh 9 380 coraddrn corrected to coradrn 9 381 coraddrn corrected to coradrn 9 382 description of cor3ctl0 register removed 9 383 description of cor3ctl1 register removed 9 384 description of cor3adrnl registers removed 9 385 description of cor3adrnh registers removed 9 386 description of cor3valnl registers removed 9 386 description of cor3valnh registers removed 13 493 tmg2 added for pd70f3421, pd70f3422, and pd70f3423 18 632 flow chart of csib single transmission/reception corrected: - "intcbnt bit = 1?" replaced by "intcbnr generated"? - checking of cbntsf bit removed 18 633 flow chart of csib single reception corrected: - "intcbnr bit = 1?" replaced by "intcbnr generated"? 18 634 flow chart of csib single transmission/reception corrected: - "intcbnr bit = 1?" replaced by "intcbnr generated"? revison history compared to u17566ee4v0um00 chapter page description
1023 user?s manual u17566ee5v1um00 18 635 flow chart of csib continuous transmission corrected: - "intcbnt bit = 1?" replaced by "intcbnt generated"? - "cbntsf bit = 1?" replaced by "cbntsf bit = 0" 18 636 flow chart of continuous reception replaced 18 637 flow chart of continuous transmission/reception replaced 20 719 3rd can channel (can2) added for pd70f3427, pd70f3425, pd70f3424, pd70f3423, pd70f3422, pd70f3421 20 745 can2 added to can module base addresses table 25 935 unused bits in sg0fh register corrected to [15:9] b 997 initial values added to list of can special function registers b 999 can2 registers added to list of can special function registers b 1001 initial values added to list of other special function registers b 1002 imr6, imr6l, imr6h registers register added to list of other special function registers b 1004 c2erric register added to list of other special function registers b 1004 c2wupic register added to list of other special function registers b 1004 c2recic register added to list of other special function registers b 1004 c2trxic register added to list of other special function registers b 1007 pilc7 register access corrected to 16-bit access b 1007 pilc7l register added to list of other special function registers b 1007 pilc7h register added to list of other special function registers b 1008 p14 register added to list of other special function registers b 1008 pmc7 register access corrected to 16-bit access b 1008 pmc7l register added to list of other special function registers b 1008 pmc7h register added to list of other special function registers b 1009 pfc0 register added to list of other special function registers b 1009 pfc1register added to list of other special function registers b 1009 pfc2 register added to list of other special function registers b 1017 cor2cn register added to list of other special function registers revison history compared to u17566ee5v0um00 chapter page description 286 limitation of lcd bus i/f pins (dbd[7:0]) to "pd70f3424, pd70f3425, pd70f3426a, pd70f3427 only" removed 2110 sib2, sob2 and sck2 removed from port p80 to p82 (pin no. 97 to 95) in pin overview of pd70f3421, pd70f3422, pd70f3423 2111 sib2, sob2 and sck2 added to port p94 to p96 (pin no. 111 to 113) in pin overview of pd70f3424, pd70f3425, pd70f3426a 4145 set up of the sscg post clock divider after start of sscg removed from start-up guideline (sscg post clock divider setting only permitted when sscg is off) 4155 sub chapter of sscg control registers corrected (mistakenly inserted twice; former sub chapter 4.2.2 removed) 9 392 empty sub chapter 9.4 removed revison history compared to u17566ee4v0um00 chapter page description
1024 user?s manual u17566ee5v1um00
1025 user?s manual u17566ee5v1um00 index numerics 16-bit data busses access to 342 8-bit data busses access to 336 a a/d conversion result register hn (adcr0hn) 859, 866 a/d conversion result register n (adcr0n) 859, 866 a/d converter 857 basic operation 869 cautions 876 configuration 859 control registers 861 how to read a/d converter characteristics table 878 operation mode 871 power-fail compare mode 873 trigger mode 870 access to 16-bit data busses 342 8-bit data busses 336 external devices (initialization) 299 ada0m0 862 ada0m1 863 ada0m2 864 ada0pfm 868 ada0pft 860, 868 ada0s 865 adc channel specification register 0 (ada0s) 865 adc mode register 0 (ada0m0) 862 adc mode register 1 (ada0m1) 863 adc mode register 2 (ada0m2) 864 adcr0hn 859, 866 adcr0n 859, 866 address setup wait control register (asc) 313 address space 126 cpu 126 images 126 physical 126 adic 239 analog filtered inputs 104 asc 313 asynchronous serial interface see uarta automatic pwm phase shift 895 b baud rate generator csib 638 uarta 599 bcc 315 bctn 311 bcu (bus control unit) 289 bcu registers 301 bec 309 bmc 316 boundary operation conditions 298 bpc 301 bus and memory control 289 registers 300 bus cycle configuration register (bctn) 311 bus cycle control register (bcc) 315 bus mode control register (bmc) 316 c callt base pointer (ctbp) 124 can (controller area network) 719 can controller 719 baud rate settings 821 bit set/clear function 752 configuration 722 connection with target system 744 control registers 754 diagnosis functions 816 functions 732 initialization 790 internal registers 745 interrupt function 815 message reception 794 message transmission 802 operation 829 overview of functions 721 power saving modes 810 register access type 747 register bit configuration 749 special operational modes 816 time stamp function 820 transition from initialization mode to opera- tion mode 792 can protocol 723 cann global automatic block transmission control register (cngmabt) 757 cann global automatic block transmission delay register (cngmabtd) 759 cann global clock selection register (cngmcs) 756 cann global control register (cngmctrl) 754
1026 index user?s manual u17566ee5v1um00 cann message configuration register m (cnmconfm) 784 cann message control register m (cnmctrlm) 787 cann message data byte register (cnmdataxm) 781 cann message data length register m (cnmdlcm) 783 cann message id register m (cnmidlm, cnmidhm) 786 cann module bit rate prescaler register (cnbrp) 772 cann module bit rate register (cnbtr) 773 cann module control register (cnctrl) 762 cann module error counter register (cnerc) 768 cann module information register (cninfo) 767 cann module interrupt enable register (cnie) 769 cann module interrupt status register (cnints) 771 cann module last error information register (cnlec) 766 cann module last in-pointer register (cnlipt) 774 cann module last out-pointer register (cnlopt) 776 cann module mask control register (cnmaskal, cnmaskah) 760 cann module receive history list register (cnrgpt) 775 cann module time stamp register (cnts) 779 cann module transmit history list register (cntgpt) 777 cbnctl0 612 cbnctl1 614 cbnctl2 616 cbnreic 239 cbnric 239 cbnrx 619 cbnstr 618 cbntic 239 cbntx 619 cgstat 149 chip area select control registers (cscn) 305 chip select signals 292 ckc 148 clmcs 178 clmm 175 clmm write protection register (prcmdcmm) 176 clms 177 clms write protection register (prcmdcms) 177 clock generator 139 default setup 197 operation 196 registers 146 start conditions 144 clock generator control register (ckc) 148 clock generator registers 146 general 148 peripheral clock 161 sscg control 155 clock generator status register (cgstat) 149 clock monitors 142 operation 198 registers 175 clock output foutclk 196 clocked serial interface see csib clocks cpu 141 peripheral 141 special clocks 142 cnbrp 772 cnbtr 773 cnctrl 762 cnerc 768 cnerric 239 cngmabt 757 cngmabtd 759 cngmcs 756 cngmctrl 754 cnie 769 cninfo 767 cnints 771 cnlec 766 cnlipt 774 cnlopt 776 cnmaskah 760 cnmaskal 760 cnmconfm 784 cnmctrlm 787 cnmdataxm 781 cnmdlcm 783 cnmidhm 786 cnmidlm 786 cnrecic 239 cnrgpt 775 cntgpt 777 cntrxic 239
1027 index user?s manual u17566ee5v1um00 cnts 779 cnwupic 239 combined compare control registers (mcmpnkhw) 889 command protection register (phcmd) 150 command register (prcmd) 173, 267 common signals (lcd controller/driver) 904 compare control registers (mcmpcnk) 890 compare registers for cosine side (mcmpnk1) 889 compare registers for sine side (mcmpnk0) 888 control registers for peripheral clocks 161 cor2adn 392 cor2cn 390 coradn 391 coradrnh 384 coradrnl 383 corcn 390 corctl0 382 corctl1 382 corvalnh 386 corvalnl 385 cpu address space 126 clocks 141 core 16 functions 113 operation after power save mode release 193 register set 115 cr001 561 crc0 560 cs 292 cscn 305 csib baud rate generator 638 control registers 611 operation 620 operation flow 632 output pins 631 csib (clocked serial interface) 609 csib transmit data register (cbntx) 619 csibn control register 0 (cbnctl0) 612 csibn control register 1 (cbnctl1) 614 csibn control register 2 (cbnctl2) 616 csibn receive data register (cbnrx) 619 csibn status register (cbnstr) 618 ctbp 124 ctpc 119 ctpsw 122 d dadcn 358 data access order 336 data address space recommended use 134 data busses access order 336 data space 128 data wait control registers (dwcn) 314 dbcn 357 dbpc 119, 261, 262, 263, 264 dbpsw 122, 261, 262, 263, 264 dchcn 360 ddahn 355 ddaln 356 debug function (on-chip) restrictions and cautions 982 debug function (on-chip) 969 code protection 393 debug trap 263 default clock setting 194 dfen0 106 dfen1 107 digital filter enable register (dfen0) 106 digital filter enable register (dfen1) 107 digitally filtered inputs 104 dma (direct memory access) 349 dma addressing control registers n (dadcn) 358 dma channel control registers n (dchcn) 360 dma controller 349 automatic restart function 366 channel priorities 368 control registers 353 forcible interruption 368 forcible termination 369 transfer completion 371 transfer mode 371 transfer object 367 transfer start factors 368 transfer type 367 dma destination address registers hn (ddahn) 355 dma destination address registers ln (ddaln) 356 dma functions 349 dma restart register (drst) 361 dma source address registers hn (dsahn) 353 dma source address registers ln (dsaln) 354 dma transfer count registers n (dbcn) 357
1028 index user?s manual u17566ee5v1um00 dma trigger source select register n (dtfrn) 362 dmanic 239 drst 361 dsahn 353 dsaln 354 dtfrn 362 duty factor (pulse width modulation) 892 dwcn 314 e ecr 123 eipc 119, 232, 234, 238, 259, 260, 264, 265 eipsw 122, 232, 234, 238, 259, 260, 264, 265 element pointer (ep) 115, 117 endian configuration register (bec) 309 endian format 322 exception status flag (ep) 261 exception trap 261 external bus properties 297 bus access 298 bus priority order 297 bus width 297 external devices initialization for access 299 interface timing 324 external interrupt configuration registers (intmn) 257 external memory area 131 external reset 958 f fcc 166 fepc 119, 226, 229, 230 fepsw 122, 226, 229, 230 fixed peripheral i/o area 295 flash area 130, 131 flash memory 269 address assignment 271 checksum 396 id-field 396 protection 393 self-programming 275 flash programmer 279 communication mode 280 pin connection 283 programming method 285 flash programming mode 126 via n-wire 278 with flash programmer 279 foutclk control register (fcc) 166 g gccn0 503 gccn5 503 gccnm 504 general purpose registers (r0 to r31) 117 global pointer (gp) 115, 117 h halt mode 181 i i 2 c bus 645 acknowledge signal 672 address match detection method 696 arbitration 698 cautions 705 communication operations 706 control registers 654 definitions and control methods 669 error detection 696 extension code 697 interrupt request signal (intiicn) generation timing and wait control 695 interrupt request signals (intiicn) 677 pin configuration 669 stop condition 674 timing of data communication 712 transfer direction specification 672 wait signal 675 wakeup function 699 icc 168 id code 971 idle mode 182 idle pins recommended connection 109 idle state insertion (access to external devices) 324 iic clock control register (icc) 168 iic clock select registers (iiccln) 664 iic control registers (iiccn) 655 iic division clock select registers (ocksn) 665 iic flag registers (iicfn) 662 iic function expansion registers (iicx0n) 665 iic shift registers (iicn) 668 iic status registers (iicsn) 659 iiccln 664 iiccn 655 iicfn 662 iicn 668
1029 index user?s manual u17566ee5v1um00 iicnic 239 iicsn 659 iicx0n 665 illegal opcode definition 261 images in address space 126 imrn 252 initialization for access to external devices 299 in-service priority register (ispr) 255, 267 instruction set 16 int70ic 239 int71ic 239 intc (interrupt controller) 201 internal oscillator operation after power save mode 196 internal peripheral function wait control register (vswc) 303 internal ram area 130 internal vfb flash and rom area 130 internal vsb flash area 131 internal vsb ram area 131 interrupt maskable 232 non-maskable 226 processing (multiple interrupts) 264 response time 266 interrupt control register (plcn) 267 interrupt controller 201 debug trap 263 edge and level detection configuration 257 exception trap 261 periods in which interrupts are not acknowledged 267 software exception 259 interrupt mask registers imrn 252 interrupt/exception source register (ecr) 123 intmn 257 ispr 255, 267 l lbctl 916 lbcyc 917 lbdata 919 lbdata register access types 913 lbdatar 921 lbs 312 lbwst 918 lcd activation of segments 906 panel addressing 899 lcd bus interface 911 access modes 913 interrupt generation 914 registers 915 timing 922 lcd bus interface control register (lbctl) 916 lcd bus interface cycle time register (lbcyc) 917 lcd bus interface data register (lbdata) 919 lcd bus interface data register (lbdatar) 921 lcd bus interface wait state register (lbwst) 918 lcd clock control register (lcdc0) 901 lcd controller/driver 897 common signals 904 registers 900 segment signals 905 lcd display control register (segreg0k) 903 lcd mode control register (lcdm0) 903 lcdc0 901 lcdic 239 lcdm0 903 link pointer (lp) 115, 117 local bus size configuration register (lbs) 312 m main oscillator clock monitor register (clmm) 175 maskable interrupt status flag (id) 255 maskable interrupts 232 maskable interrupts control register (xxic) 239 mcmpcnk 890 mcmpnk0 888 mcmpnk1 889 mcmpnkhw 889 mcntcn0 887 mcntcn1 887 memc (memory controller) 289 memory 130 access configuration 322 areas 130 banks 292 controller registers 311 n noise elimination pin input 104 timer g 529 non-maskable interrupts 226 normal operation mode 125 n-wire
1030 index user?s manual u17566ee5v1um00 code protection 393 connection to emulator 978 controlling the interface 974 emulator 969 enabling methods 976 flash programming 278 id code 971 security disabling 972 security function 971 n-wire security disable control register (rsudis) 972 o ocdm 38 ocksn 665 octlgn 501 octlgnh 501 octlgnl 501 on-chip debug mode register (ocdm) 38 operation modes 125 flash programming mode 126 normal operation mode 125 p package pins assignment 110 page rom access timing 331 controller 320 page rom configuration register (prc) 318 page rom controller 320 pc 119 pc saving registers 119 pcc 152 pdscn 41 peripheral area selection control register (bpc) 301 peripheral clocks 141 control registers 161 peripheral function select register (pfsr0) 45 peripheral function select register (pfsr1) 46 peripheral function select register (pfsr2) 47 peripheral function select register (pfsr3) 48 peripheral i/o area 295 fixed 295 programmable 133, 296 peripheral status register (phs) 151 pfcn 36 pfsr0 45 pfsr1 46 pfsr2 47 pfsr3 48 phcmd 150 phs 151 physical address space 126 piccn 41 pilcn 42 pin functions 27 after reset/in stand-by modes 108 unused pins 109 plcdcn 37 pmcn 36 pmn 35 pn 39 pnic 239 poc (power-on clear) 957 podcn 43 port drive strength control register (pdscn) 41 port function control register (pfcn) 36 port groups 28 configuration 54 configuration registers 33 port input characteristic control register (piccn) 41 port input level control register (pilcn) 42 port lcd control register (plcdcn) 37 port mode control register (pmcn) 36 port mode register (pmn) 35 port open drain control register (podcn) 43 port pin read register (pprn) 40 port read control register (prcn) 40 port register (pn) 39 power save control register (psc) 172 power save mode control register (psm) 169 power save modes 179 power save modes 143 activation 191 control registers 169 cpu operation after release 193 description 179 power supply scheme 947 power-fail compare mode register (ada0pfm) 868 power-fail compare threshold value register (ada0pft) 860, 868 power-on clear reset 957 ppa (programmable peripheral i/o area) 296 pprn 40 prc 318 prcmd 173, 267 prcmdcmm 176
1031 index user?s manual u17566ee5v1um00 prcmdcms 177 prcn 40 prescaler compare registers (prscmn) 639 prescaler mode registers (prsmn) 639 prm0 559 processor clock control register (pcc) 152 program counter (pc) 119 program space 128 program status word (psw) 120 programmable peripheral i/o area 133, 296 prscmn 639 prsmn 639 psc 172 psm 169 psw 120 psw saving registers 122 pwm (pulse width modulation) 448 pwm phase shift (automatic) 895 r ram area 130, 131 rddly 317 read delay control register (rddly) 317 regid (system register number) 118 reload register timer y (tynrm) 539 timer z (tznr) 489 watch timer (wtnr) 553 reset 953 at power-on 957 by clock monitor 959 by software 959 by watchdog timer 959 external reset 958 hardware status after reset 955 register status after reset 956 registers 960 variable vector 396 reset source flag register (resstat) 960 resstat 960 resswt 961 rom area 130 rom correction data replacement 376 dbtrap 387 rom correction address registers cor2adn 392 coradn 391 coradrnh 384 coradrnl 383 rom correction control registers cor2cn 390 corcn 390 corctl0 382 corctl1 382 rom correction function 375 dbtrap operation and program flow 388 rom correction value registers corvalnh 386 corvalnl 385 romc (rom controller) 292 rsudis write protection register (rsudis) 973 rsudisc 972 rsudiscp 973 s sar 859 saturated operation instructions 121 scc 165 scfc0 156 scfc1 157 scfmc 158 scps 160 sdc 154 segment signals (lcd controller/driver) 905 segreg0k 903 selfen 275, 276 selfenp 275, 276 self-programming enable control register (selfen) 275, 276 self-programming enable protection register (selfenp) 275, 276 set default clock register (sdc) 154 sfr (special function register) 997 sg0 control register (sg0ctl) 933 sg0 frequency high register (sg0fh) 935 sg0 frequency low register (sg0fl) 934 sg0 interrupt threshold register (sg0ith) 938 sg0 sound duration factor register (sg0sdf) 937 sg0 volume register (sg0pwm) 936 sg0ctl 933 sg0fh 935 sg0fl 934 sg0ic 239 sg0ith 938 sg0pwm 936 sg0sdf 937 slave address registers (svan) 668 software exception 259 software reset register (resswt) 961
1032 index user?s manual u17566ee5v1um00 sound generator 929 application hints 945 operation 939 registers 932 spclk control register (scc) 165 special clocks 142 special function registers (list) 997 sscg control registers 155 sscg frequency control register 0 (scfc0) 156 sscg frequency control register 1 (scfc1) 157 sscg frequency modulation control register (scfmc) 158 sscg post scaler control register (scps) 160 stack pointer (sp) 115, 117 stand-by control 142 mode of voltage comparator 964 stand-by control protection register (stbctlp) 174 stand-by control register (stbctl) 174 stbctl 174 stbctlp 174 stepper motor controller/driver 883 operation 891 registers 886 stop mode 185 sub oscillator operation after power save mode 196 sub oscillator clock monitor control register (clmcs) 178 sub oscillator clock monitor register (clms) 177 sub-chapter "default clock generator setup" added 197 sub-watch mode 184 successive approximation register (sar) 859 svan 668 system register set 118 t tcc 163 test pointer (tp) 115 text pointer (tp) 117 tgnccmic 239 tgnov0ic 239 tgnov1ic 239 time base status register (tmgstn) 502 timer g 493 basic operation 506 control registers 497 edge noise elimination 529 match and clear mode 518 operation in free-run mode 507 output delay operation 505 precautions 530 timer g capture/compare registers with external pww-output function (gccnm) 504 timer gn 16-bit counter registers (tmgn0, tmgn1) 502 timer gn capture/compare registers (gccn0, gccn5) 503 timer gn channel mode register (tmgcmn/tm- gcmnl/tmgcmnh) 500 timer gn mode register (tmgmn/tmgmnl/ tmgmnh) 498 timer gn output control register (octlgn/oc- tlgnl/octlgnh) 501 timer mode control registers (mcntcn0, mcntcn1) 887 timer y 533 output timing calculations 541 registers 535 timing 540 timer z 483 registers 485 timer z timing 490 steady operation 490 timer start and stop 491 timer/event counter p 397 configuration 398 external event count mode 421 external trigger pulse output mode 430 free-running timer mode 457 interval timer mode 412 one-shot pulse output mode 441 operation 412 pulse width measurement mode 474 pwm output mode 448 timer output operations 480 tm0 561 tm01ic 239 tmc0 558 tmg (timer g) 494 tmgcmn 500 tmgcmnh 500 tmgcmnl 500 tmgmn 498 tmgmnh 498 tmgmnl 498 tmgn0 502 tmgn1 502 tmgstn 502 tmp (timer/event counter p) 397
1033 index user?s manual u17566ee5v1um00 tmpn capture/compare register 0 (tpnccr0) 408 tmpn capture/compare register 1 (tpnccr1) 410 tmpn control register 0 (tpnctl0) 402 tmpn control register 1 (tpnctl1) 403 tmpn counter read buffer register (tpncnt) 411 tmpn i/o control register 0 (tpnioc0) 404 tmpn i/o control register 1 (tpnioc1) 405 tmpn i/o control register 2 (tpnioc2) 406 tmpn option register 0 (tpnopt0) 407 tmy (timer y) 533 tmy i/o control register (tynioc) 537 tmy non-synchronized counter registers (tyncntm1) 538 tmy synchronized counter registers (tyncntm0) 537 tmy timer control register (tynctl) 536 tmz (timer z) 483 tmzn non-synchronized counter register (tzncnt1) 488 tmzn synchronized counter register (tzncnt0) 487 tmzn timer control register (tznctl) 486 tpncc0ic 239 tpncc1ic 239 tpnccr0 408 tpnccr1 410 tpncnt 411 tpnctl0 402 tpnctl1 403 tpnioc0 404 tpnioc1 405 tpnioc2 406 tpnopt0 407 tpnovic 239 ty0ccnic 239 tyncntm0 537 tyncntm1 538 tynctl 536 tynioc 537 tynrm 539 tzncnt0 487 tzncnt1 488 tznctl 486 tznr 489 tznuvic 239 u uanctl0 579 uanctl1 600 uanctl2 601 uanopt0 581 uanreic 239 uanric 239 uanrx 584 uanstr 582 uantic 239 uantx 584 uarta cautions 606 dedicated baud rate generator 599 interrupt request signals 585 operation 586 uartan control register 0 (uanctl0) 579 uartan control register 1 (uanctl1) 600 uartan control register 2 (uanctl2) 601 uartan option control register 0 (uanopt0) 581 uartan receive data register (uanrx) 584 uartan receive shift register 577 uartan status register (uanstr) 582 uartan transmit data register (uantx) 584 uartan transmit shift register 577 v vcctln 965 vcnic 239 vcstrn 966 voltage comparator 963 registers 965 voltage comparator n control register (vcctln) 965 voltage comparator n status register (vcstrn) 966 voltage regulators 952 vswc 303 w wait functions (access to external devices) 322 watch calibration timer operation 549, 562 registers 557 watch mode 183 watch timer 545 operation control (wt0) 548 operation of wt1 548 registers 550 watch timer clock control register (tcc) 163 watch timer operation 554 start-up 555 steady operation 554
1034 index user?s manual u17566ee5v1um00 watchdog timer 565 clock 567 registers 569 watchdog timer clock control register (wcc) 161 watchdog timer clock selection register (wdcs) 570 watchdog timer command protection register (wcmd) 573 watchdog timer command status register (wphs) 574 watchdog timer mode register (wdtm) 572 wcc 161 wcmd 573 wct (watch calibration timer) 545 wct capture / compare control register (crc0) 560 wct capture / compare register 1 (cr001) 561 wct mode control register (tmc0) 558 wct prescaler mode register (prm0) 559 wct timer / counter read register (tm0) 561 wdcs 570 wdtm 572 wphs 574 write protected registers 135 wt (watch timer) 545 wt0 (watch timer 0) 545 wt1 (watch timer 1) 545 wtn non-synchronized counter read register (wtncnt1) 552 wtn synchronized counter register (wtncnt0) 551 wtn timer control register (wtnctl) 550 wtncnt0 551 wtncnt1 552 wtnctl 550 wtnr 553 wtnuvic 239 z zero register 115, 117
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